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am335x evm: Enable support for spi0
Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
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4c0620bf42
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3 changed files with 30 additions and 0 deletions
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@ -310,6 +310,16 @@ static struct module_pin_mux i2c1_pin_mux[] = {
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{-1},
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{-1},
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};
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};
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static struct module_pin_mux spi0_pin_mux[] = {
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{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
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{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
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PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
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{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
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{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
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PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
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{-1},
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};
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static struct module_pin_mux gpio0_7_pin_mux[] = {
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static struct module_pin_mux gpio0_7_pin_mux[] = {
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{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
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{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
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{-1},
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{-1},
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@ -430,6 +440,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
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configure_module_pin_mux(i2c1_pin_mux);
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configure_module_pin_mux(i2c1_pin_mux);
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else if (profile == PROFILE_2) {
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else if (profile == PROFILE_2) {
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configure_module_pin_mux(mmc1_pin_mux);
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configure_module_pin_mux(mmc1_pin_mux);
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configure_module_pin_mux(spi0_pin_mux);
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}
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}
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} else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
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} else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
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/* Starter Kit EVM */
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/* Starter Kit EVM */
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@ -173,8 +173,18 @@ int spi_claim_bus(struct spi_slave *slave)
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/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
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/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
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* REVISIT: this controller could support SPI_3WIRE mode.
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* REVISIT: this controller could support SPI_3WIRE mode.
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*/
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*/
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#ifdef CONFIG_AM33XX
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/*
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* The reference design on AM33xx has D0 and D1 wired up opposite
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* of how it has been done on previous platforms. We assume that
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* custom hardware will also follow this convention.
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*/
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conf &= OMAP3_MCSPI_CHCONF_DPE0;
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conf |= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
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#else
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conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
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conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
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conf |= OMAP3_MCSPI_CHCONF_DPE0;
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conf |= OMAP3_MCSPI_CHCONF_DPE0;
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#endif
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/* wordlength */
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/* wordlength */
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conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
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conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
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@ -134,6 +134,14 @@
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_EXT2
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#define CONFIG_SPI
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#define CONFIG_OMAP3_SPI
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#define CONFIG_MTD_DEVICE
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_SPEED (24000000)
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/* Physical Memory Map */
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
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#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
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#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
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#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
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@ -163,6 +171,7 @@
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_DRIVER_OMAP24XX_I2C
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#define CONFIG_DRIVER_OMAP24XX_I2C
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_EEPROM
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#define CONFIG_ENV_EEPROM_IS_ON_I2C
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_I2C_MULTI_EEPROMS
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#define CONFIG_SYS_I2C_MULTI_EEPROMS
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