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FEC: Abstract out register setup

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Abstract out common register setup. This also configured r_cntrl
to correct value at registration time.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Marek Vasut 2012-05-01 11:09:41 +00:00 • committed by Albert ARIBAUD
parent c4559daa91
commit a5990b2674
1 changed files with 38 additions and 46 deletions
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84
drivers/net/fec_mxc.c
View file

@ -400,6 +400,42 @@ static void fec_eth_phy_config(struct eth_device *dev)
#endif #endif
} }
/*
* Do initial configuration of the FEC registers
*/
static void fec_reg_setup(struct fec_priv *fec)
{
uint32_t rcntrl;
/*
* Set interrupt mask register
*/
writel(0x00000000, &fec->eth->imask);
/*
* Clear FEC-Lite interrupt event register(IEVENT)
*/
writel(0xffffffff, &fec->eth->ievent);
/*
* Set FEC-Lite receive control register(R_CNTRL):
*/
/* Start with frame length = 1518, common for all modes. */
rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
if (fec->xcv_type == SEVENWIRE)
rcntrl |= FEC_RCNTRL_FCE;
else if (fec->xcv_type == RGMII)
rcntrl |= FEC_RCNTRL_RGMII;
else if (fec->xcv_type == RMII)
rcntrl |= FEC_RCNTRL_RMII;
else /* MII mode */
rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
writel(rcntrl, &fec->eth->r_cntrl);
}
/** /**
* Start the FEC engine * Start the FEC engine
* @param[in] dev Our device to handle * @param[in] dev Our device to handle
@ -514,7 +550,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
{ {
struct fec_priv *fec = (struct fec_priv *)dev->priv; struct fec_priv *fec = (struct fec_priv *)dev->priv;
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
uint32_t rcntrl;
uint32_t size; uint32_t size;
int i, ret; int i, ret;
@ -562,33 +597,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
(unsigned)fec->rbd_base + size); (unsigned)fec->rbd_base + size);
} }
/* fec_reg_setup(fec);
* Set interrupt mask register
*/
writel(0x00000000, &fec->eth->imask);
/*
* Clear FEC-Lite interrupt event register(IEVENT)
*/
writel(0xffffffff, &fec->eth->ievent);
/*
* Set FEC-Lite receive control register(R_CNTRL):
*/
/* Start with frame length = 1518, common for all modes. */
rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
if (fec->xcv_type == SEVENWIRE)
rcntrl |= FEC_RCNTRL_FCE;
else if (fec->xcv_type == RGMII)
rcntrl |= FEC_RCNTRL_RGMII;
else if (fec->xcv_type == RMII)
rcntrl |= FEC_RCNTRL_RMII;
else /* MII mode */
rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
writel(rcntrl, &fec->eth->r_cntrl);
if (fec->xcv_type == MII10 || fec->xcv_type == MII100) if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
fec_mii_setspeed(fec); fec_mii_setspeed(fec);
@ -935,24 +944,7 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
udelay(10); udelay(10);
} }
/* fec_reg_setup(fec);
* Set interrupt mask register
*/
writel(0x00000000, &fec->eth->imask);
/*
* Clear FEC-Lite interrupt event register(IEVENT)
*/
writel(0xffffffff, &fec->eth->ievent);
/*
* Set FEC-Lite receive control register(R_CNTRL):
*/
/*
* Frame length=1518; MII mode;
*/
writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE |
FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl);
fec_mii_setspeed(fec); fec_mii_setspeed(fec);
if (dev_id == -1) { if (dev_id == -1) {