mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-28 01:51:33 +00:00
arm: rmobile: alt: Update to QoS revision 0.31 and 0.321
This updates r8a7794 QoS to revision 0.31 for ES1 and revision 0.321 for ES2. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
parent
98c3322c4e
commit
a5aef73206
3 changed files with 68 additions and 14 deletions
|
@ -52,7 +52,7 @@ config RMOBILE_EXTRAM_BOOT
|
||||||
|
|
||||||
choice
|
choice
|
||||||
prompt "Qos setting primary"
|
prompt "Qos setting primary"
|
||||||
depends on TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
|
depends on TARGET_ALT || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
|
||||||
default QOS_PRI_NORMAL
|
default QOS_PRI_NORMAL
|
||||||
|
|
||||||
config QOS_PRI_NORMAL
|
config QOS_PRI_NORMAL
|
||||||
|
|
|
@ -32,4 +32,8 @@
|
||||||
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
|
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
|
||||||
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
|
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
|
||||||
|
|
||||||
|
#define R8A7794_CUT_ES2 2
|
||||||
|
#define IS_R8A7794_ES2() \
|
||||||
|
(rmobile_get_cpu_rev_integer() == R8A7794_CUT_ES2)
|
||||||
|
|
||||||
#endif /* __ASM_ARCH_R8A7794_H */
|
#endif /* __ASM_ARCH_R8A7794_H */
|
||||||
|
|
|
@ -14,7 +14,7 @@
|
||||||
#include <asm/arch/rmobile.h>
|
#include <asm/arch/rmobile.h>
|
||||||
|
|
||||||
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
|
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
|
||||||
/* QoS version 0.11 */
|
/* QoS version 0.311 for ES1 and version 0.321 for ES2 */
|
||||||
|
|
||||||
enum {
|
enum {
|
||||||
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
|
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
|
||||||
|
@ -62,6 +62,24 @@ static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
|
||||||
[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
|
[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#if defined(CONFIG_QOS_PRI_MEDIA)
|
||||||
|
#define is_qos_pri_media() 1
|
||||||
|
#else
|
||||||
|
#define is_qos_pri_media() 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_QOS_PRI_NORMAL)
|
||||||
|
#define is_qos_pri_normal() 1
|
||||||
|
#else
|
||||||
|
#define is_qos_pri_normal() 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_QOS_PRI_GFX)
|
||||||
|
#define is_qos_pri_gfx() 1
|
||||||
|
#else
|
||||||
|
#define is_qos_pri_gfx() 0
|
||||||
|
#endif
|
||||||
|
|
||||||
void qos_init(void)
|
void qos_init(void)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
|
@ -77,30 +95,57 @@ void qos_init(void)
|
||||||
|
|
||||||
/* S3C -QoS */
|
/* S3C -QoS */
|
||||||
s3c = (struct rcar_s3c *)S3C_BASE;
|
s3c = (struct rcar_s3c *)S3C_BASE;
|
||||||
writel(0x1F0D0B0A, &s3c->s3crorr);
|
if (is_qos_pri_media()) {
|
||||||
writel(0x1F0D0B09, &s3c->s3cworr);
|
writel(0x1F0B0604, &s3c->s3crorr);
|
||||||
|
writel(0x1F0E0705, &s3c->s3cworr);
|
||||||
|
} else if (is_qos_pri_normal()) {
|
||||||
|
writel(0x1F0B0908, &s3c->s3crorr);
|
||||||
|
writel(0x1F0E0A08, &s3c->s3cworr);
|
||||||
|
} else if (is_qos_pri_media()) {
|
||||||
|
writel(0x1F0B0B0B, &s3c->s3crorr);
|
||||||
|
writel(0x1F0E0C0C, &s3c->s3cworr);
|
||||||
|
}
|
||||||
/* QoS Control Registers */
|
/* QoS Control Registers */
|
||||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
|
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
|
||||||
writel(0x00890089, &s3c_qos->s3cqos0);
|
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
if (is_qos_pri_media())
|
||||||
|
writel(0x20AA2300, &s3c_qos->s3cqos3);
|
||||||
|
else if (is_qos_pri_normal())
|
||||||
|
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||||
|
else if (is_qos_pri_media())
|
||||||
|
writel(0x20AA2100, &s3c_qos->s3cqos3);
|
||||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
if (is_qos_pri_media())
|
||||||
|
writel(0x20AA2300, &s3c_qos->s3cqos7);
|
||||||
|
else if (is_qos_pri_normal())
|
||||||
|
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||||
|
else if (is_qos_pri_gfx())
|
||||||
|
writel(0x20AA2100, &s3c_qos->s3cqos7);
|
||||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||||
|
|
||||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
|
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
|
||||||
writel(0x00890089, &s3c_qos->s3cqos0);
|
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
if (is_qos_pri_media())
|
||||||
|
writel(0x20AA2300, &s3c_qos->s3cqos3);
|
||||||
|
else if (is_qos_pri_normal())
|
||||||
|
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||||
|
else if (is_qos_pri_gfx())
|
||||||
|
writel(0x20AA2100, &s3c_qos->s3cqos3);
|
||||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
if (is_qos_pri_media())
|
||||||
|
writel(0x20AA2300, &s3c_qos->s3cqos7);
|
||||||
|
else if (is_qos_pri_media())
|
||||||
|
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||||
|
else if (is_qos_pri_media())
|
||||||
|
writel(0x20AA2100, &s3c_qos->s3cqos7);
|
||||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||||
|
|
||||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
|
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
|
||||||
|
@ -115,7 +160,7 @@ void qos_init(void)
|
||||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||||
|
|
||||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
|
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
|
||||||
writel(0x00820082, &s3c_qos->s3cqos0);
|
writel(0x00820092, &s3c_qos->s3cqos0);
|
||||||
writel(0x20960020, &s3c_qos->s3cqos1);
|
writel(0x20960020, &s3c_qos->s3cqos1);
|
||||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||||
writel(0x20AA20FA, &s3c_qos->s3cqos3);
|
writel(0x20AA20FA, &s3c_qos->s3cqos3);
|
||||||
|
@ -157,8 +202,13 @@ void qos_init(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* CCI-400 -QoS */
|
/* CCI-400 -QoS */
|
||||||
writel(0x20000800, CCI_400_MAXOT_1);
|
if (IS_R8A7794_ES2()) {
|
||||||
writel(0x20000800, CCI_400_MAXOT_2);
|
writel(0x20001000, CCI_400_MAXOT_1);
|
||||||
|
writel(0x20001000, CCI_400_MAXOT_2);
|
||||||
|
} else {
|
||||||
|
writel(0x20000800, CCI_400_MAXOT_1);
|
||||||
|
writel(0x20000800, CCI_400_MAXOT_2);
|
||||||
|
}
|
||||||
writel(0x0000000C, CCI_400_QOSCNTL_1);
|
writel(0x0000000C, CCI_400_QOSCNTL_1);
|
||||||
writel(0x0000000C, CCI_400_QOSCNTL_2);
|
writel(0x0000000C, CCI_400_QOSCNTL_2);
|
||||||
|
|
||||||
|
@ -166,7 +216,7 @@ void qos_init(void)
|
||||||
/* Transaction Control (MXI) */
|
/* Transaction Control (MXI) */
|
||||||
mxi = (struct rcar_mxi *)MXI_BASE;
|
mxi = (struct rcar_mxi *)MXI_BASE;
|
||||||
writel(0x00000013, &mxi->mxrtcr);
|
writel(0x00000013, &mxi->mxrtcr);
|
||||||
writel(0x00000013, &mxi->mxwtcr);
|
writel(0x00000016, &mxi->mxwtcr);
|
||||||
writel(0x00780080, &mxi->mxsaar0);
|
writel(0x00780080, &mxi->mxsaar0);
|
||||||
writel(0x02000800, &mxi->mxsaar1);
|
writel(0x02000800, &mxi->mxsaar1);
|
||||||
|
|
||||||
|
@ -449,7 +499,7 @@ void qos_init(void)
|
||||||
|
|
||||||
/* QoS Register (RT-AXI) */
|
/* QoS Register (RT-AXI) */
|
||||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
|
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
|
||||||
writel(0x00000000, &axi_qos->qosconf);
|
writel(0x00000001, &axi_qos->qosconf);
|
||||||
writel(0x00002053, &axi_qos->qosctset0);
|
writel(0x00002053, &axi_qos->qosctset0);
|
||||||
writel(0x00002096, &axi_qos->qosctset1);
|
writel(0x00002096, &axi_qos->qosctset1);
|
||||||
writel(0x00002030, &axi_qos->qosctset2);
|
writel(0x00002030, &axi_qos->qosctset2);
|
||||||
|
|
Loading…
Add table
Reference in a new issue