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arm, at91: corvus board updates

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- corvus board fix problems with toshiba nand chips
  on the corvus board problems with toshiba chips
  Manufacturer ID: 0x98 Chip ID: 0xdc encounterd.

  Solve this in the following way:
  - set other nand timings
  - enable CONFIG_SYS_NAND_READY_PIN

- correct the MACH_TYPE setting

Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher 2014-11-18 11:53:53 +01:00 • committed by Andreas Bießmann
parent a1655bb2e1
commit a5f8ccaeab
2 changed files with 9 additions and 7 deletions
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12
board/siemens/corvus/board.c
View file

@ -43,13 +43,13 @@ static void corvus_nand_hw_init(void)
writel(csa, &matrix->ebicsa); writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */ /* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup); &smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
&smc->cs[3].pulse); &smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
&smc->cs[3].cycle); &smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE | AT91_SMC_MODE_EXNW_DISABLE |
@ -62,9 +62,11 @@ static void corvus_nand_hw_init(void)
&smc->cs[3].mode); &smc->cs[3].mode);
at91_periph_clk_enable(ATMEL_ID_PIOC); at91_periph_clk_enable(ATMEL_ID_PIOC);
at91_periph_clk_enable(ATMEL_ID_PIOA);
/* Enable NandFlash */ /* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
} }
#if defined(CONFIG_SPL_BUILD) #if defined(CONFIG_SPL_BUILD)

4
include/configs/corvus.h
View file

@ -18,6 +18,7 @@
#define MACH_TYPE_CORVUS 2066 #define MACH_TYPE_CORVUS 2066
#define CONFIG_MACH_TYPE MACH_TYPE_CORVUS
#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_GENERIC_BOARD
/* /*
* Warning: changing CONFIG_SYS_TEXT_BASE requires * Warning: changing CONFIG_SYS_TEXT_BASE requires
@ -106,6 +107,7 @@
/* our CLE is AD22 */ /* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
#endif #endif
/* Ethernet */ /* Ethernet */
@ -171,7 +173,6 @@
#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_BASE
@ -184,7 +185,6 @@
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_SIZE (256*1024*1024)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \