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arm: dts: imx8mq-evk: add phy-reset-gpios for fec1
Instead of resetting the ethernet phy through functions in imx8mq_evk.c, let the driver reset the phy via dts description adding a reset duration of 10 ms following atheros 8031's datasheet recommendation. Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
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parent
02ee7a4aa5
commit
a604b67b87
2 changed files with 2 additions and 18 deletions
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@ -104,6 +104,8 @@
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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fsl,magic-packet;
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status = "okay";
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@ -64,29 +64,11 @@ int dram_init(void)
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}
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#ifdef CONFIG_FEC_MXC
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#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
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static iomux_v3_cfg_t const fec1_rst_pads[] = {
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IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
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ARRAY_SIZE(fec1_rst_pads));
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gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
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gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
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udelay(500);
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gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
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}
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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setup_iomux_fec();
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/* Use 125M anatop REF_CLK1 for ENET1, not from external */
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clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
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return set_clk_enet(ENET_125MHZ);
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