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fpga: arria10: Fix error in fpga pin configuration

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Pin configuration of the FPGA devicetree block should be done
after core configuration in the arria10 fpga driver.  This fix
corrects the check of status, and ensures that the fpga pin mux
is configured on correct configuration of the core fpga image.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
This commit is contained in:
Dalon Westergreen 2019-07-16 09:28:10 -07:00 • committed by Marek Vasut
parent a8b5031108
commit a89c2adc3d
1 changed files with 5 additions and 4 deletions
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9
drivers/fpga/socfpga_arria10.c
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@ -936,10 +936,11 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
fpgamgr_program_write(rbf_data, rbf_size);
status = fpgamgr_program_finish();
if (status) {
config_pins(gd->fdt_blob, "fpga");
puts("FPGA: Enter user mode.\n");
}
if (status)
return status;
config_pins(gd->fdt_blob, "fpga");
puts("FPGA: Enter user mode.\n");
return status;
}