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ARM: tegra186: call secure monitor for all cache-wide ops

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An SMC call is required for all cache-wide operations on Tegra186. This
patch implements the two missing hooks now that U-Boot supports them, and
fixes the mapping of "hook name" to SMC call code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2016-10-19 15:18:47 -06:00 • committed by Tom Warren
parent 1ab557a074
commit a8d0526133
1 changed files with 21 additions and 3 deletions
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24
arch/arm/mach-tegra/tegra186/cache.S
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@ -9,10 +9,10 @@
#define SMC_SIP_INVOKE_MCE 0x82FFFF00 #define SMC_SIP_INVOKE_MCE 0x82FFFF00
#define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11) #define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11)
#define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14)
#define MCE_SMC_ROC_CLEAN_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 15)
ENTRY(__asm_flush_l3_dcache) ENTRY(__asm_tegra_cache_smc)
mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
mov x1, #0 mov x1, #0
mov x2, #0 mov x2, #0
mov x3, #0 mov x3, #0
@ -22,4 +22,22 @@ ENTRY(__asm_flush_l3_dcache)
smc #0 smc #0
mov x0, #0 mov x0, #0
ret ret
ENDPROC(__asm_invalidate_l3_dcache)
ENTRY(__asm_invalidate_l3_dcache)
mov x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff)
movk x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16
b __asm_tegra_cache_smc
ENDPROC(__asm_invalidate_l3_dcache)
ENTRY(__asm_flush_l3_dcache)
mov x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff)
movk x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16
b __asm_tegra_cache_smc
ENDPROC(__asm_flush_l3_dcache) ENDPROC(__asm_flush_l3_dcache)
ENTRY(__asm_invalidate_l3_icache)
mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
b __asm_tegra_cache_smc
ENDPROC(__asm_invalidate_l3_icache)