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m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

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Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Jason Jin <jason.jin@freescale.com>
This commit is contained in:
Anton Staaf 2011-10-17 16:46:04 -07:00 • committed by Wolfgang Denk
parent 44d6cbb6a7
commit a8fc12eb8e
1 changed files with 10 additions and 0 deletions
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10
arch/m68k/include/asm/cache.h
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@ -207,4 +207,14 @@ void dcache_invalid(void);
#endif
/*
* m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer
* alignment unless the board configuration has specified a new value.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 16
#endif
#endif /* __CACHE_H */