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x86: dts: Add SPI flash MRC details for chromebook_link
Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass <sjg@chromium.org>
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1 changed files with 14 additions and 1 deletions
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@ -7,6 +7,10 @@
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model = "Google Link";
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compatible = "google,link", "intel,celeron-ivybridge";
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aliases {
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spi0 = "/spi";
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};
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config {
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silent_console = <0>;
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};
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@ -150,11 +154,20 @@
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich9";
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compatible = "intel,ich-spi";
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spi-flash@0 {
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#size-cells = <1>;
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#address-cells = <1>;
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reg = <0>;
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compatible = "winbond,w25q64", "spi-flash";
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memory-map = <0xff800000 0x00800000>;
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rw-mrc-cache {
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label = "rw-mrc-cache";
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/* Alignment: 4k (for updating) */
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reg = <0x003e0000 0x00010000>;
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type = "wiped";
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wipe-value = [ff];
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};
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};
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};
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