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x86: dts: Add SPI flash MRC details for chromebook_link

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Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2015-01-19 22:16:13 -07:00
parent 146251f87e
commit a9aff2f46a
1 changed files with 14 additions and 1 deletions
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15
arch/x86/dts/chromebook_link.dts
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@ -7,6 +7,10 @@
model = "Google Link"; model = "Google Link";
compatible = "google,link", "intel,celeron-ivybridge"; compatible = "google,link", "intel,celeron-ivybridge";
aliases {
spi0 = "/spi";
};
config { config {
silent_console = <0>; silent_console = <0>;
}; };
@ -150,11 +154,20 @@
spi { spi {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "intel,ich9"; compatible = "intel,ich-spi";
spi-flash@0 { spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
reg = <0>; reg = <0>;
compatible = "winbond,w25q64", "spi-flash"; compatible = "winbond,w25q64", "spi-flash";
memory-map = <0xff800000 0x00800000>; memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
/* Alignment: 4k (for updating) */
reg = <0x003e0000 0x00010000>;
type = "wiped";
wipe-value = [ff];
};
}; };
}; };