mirror of
https://github.com/Fishwaldo/u-boot.git
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- Add emmc hs200 support - Few bug fixes related to serdes, I2C, ethernet, etc
This commit is contained in:
commit
a9fa70b7b7
23 changed files with 275 additions and 52 deletions
|
@ -501,6 +501,10 @@ config SYS_FSL_I2C_CLK_DIV
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config SYS_FSL_IFC_CLK_DIV
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int "IFC clock divider"
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default 1 if ARCH_LS1043A
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default 4 if ARCH_LS1012A
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default 4 if ARCH_LS1028A
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default 8 if ARCH_LX2160A
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default 8 if ARCH_LS1088A
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default 2
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help
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This is the divider that is used to derive IFC clock from Platform
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@ -1154,7 +1154,8 @@ int timer_init(void)
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#ifdef CONFIG_FSL_LSCH3
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u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
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#endif
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
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defined(CONFIG_ARCH_LS1028A)
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u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
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u32 svr_dev_id;
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#endif
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@ -1173,7 +1174,8 @@ int timer_init(void)
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out_le32(cltbenr, 0xf);
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#endif
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
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defined(CONFIG_ARCH_LS1028A)
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/*
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* In certain Layerscape SoCs, the clock for each core's
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* has an enable bit in the PMU Physical Core Time Base Enable
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@ -435,7 +435,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
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do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
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CONFIG_SYS_CLK_FREQ, 1);
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#ifdef CONFIG_PCI_LAYERSCAPE
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#if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
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ft_pci_setup(blob, bd);
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#endif
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@ -22,10 +22,12 @@ DECLARE_GLOBAL_DATA_PTR;
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void get_sys_info(struct sys_info *sys_info)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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#if (defined(CONFIG_FSL_ESDHC) &&\
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defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
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defined(CONFIG_SYS_DPAA_FMAN)
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/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
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* mux 2 clock for LS1043A/LS1046A.
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*/
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#if defined(CONFIG_SYS_DPAA_FMAN) || \
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defined(CONFIG_TARGET_LS1046ARDB) || \
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defined(CONFIG_TARGET_LS1043ARDB)
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u32 rcw_tmp;
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#endif
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struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
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@ -122,32 +124,32 @@ void get_sys_info(struct sys_info *sys_info)
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}
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#endif
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#ifdef CONFIG_FSL_ESDHC
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#define HWA_CGA_M2_CLK_SEL 0x00000007
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#define HWA_CGA_M2_CLK_SHIFT 0
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#ifdef CONFIG_FSL_ESDHC
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#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
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#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
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rcw_tmp = in_be32(&gur->rcwsr[15]);
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switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
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case 1:
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sys_info->freq_sdhc = freq_c_pll[1];
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sys_info->freq_cga_m2 = freq_c_pll[1];
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break;
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#if defined(CONFIG_TARGET_LS1046ARDB)
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case 2:
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sys_info->freq_sdhc = freq_c_pll[1] / 2;
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sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
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break;
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#endif
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case 3:
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sys_info->freq_sdhc = freq_c_pll[1] / 3;
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sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
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break;
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#if defined(CONFIG_TARGET_LS1046ARDB)
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case 6:
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sys_info->freq_sdhc = freq_c_pll[0] / 2;
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sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
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break;
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#endif
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default:
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printf("Error: Unknown ESDHC clock select!\n");
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printf("Error: Unknown peripheral clock select!\n");
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break;
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}
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#else
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sys_info->freq_sdhc = (sys_info->freq_systembus /
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CONFIG_SYS_FSL_PCLK_DIV) /
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CONFIG_SYS_FSL_SDHC_CLK_DIV;
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#endif
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#endif
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@ -183,9 +185,22 @@ int get_clocks(void)
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gd->mem_clk = sys_info.freq_ddrbus;
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#ifdef CONFIG_FSL_ESDHC
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gd->arch.sdhc_clk = sys_info.freq_sdhc;
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#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
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#if defined(CONFIG_TARGET_LS1046ARDB)
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gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
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#endif
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#if defined(CONFIG_TARGET_LS1043ARDB)
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gd->arch.sdhc_clk = sys_info.freq_cga_m2;
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#endif
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#if defined(CONFIG_TARGET_LS1012ARDB)
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gd->arch.sdhc_clk = sys_info.freq_systembus;
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#endif
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#else
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gd->arch.sdhc_clk = (sys_info.freq_systembus /
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CONFIG_SYS_FSL_PCLK_DIV) /
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CONFIG_SYS_FSL_SDHC_CLK_DIV;
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#endif
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#endif
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if (gd->cpu_clk != 0)
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return 0;
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else
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@ -64,6 +64,9 @@ void get_sys_info(struct sys_info *sys_info)
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};
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uint i, cluster;
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#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
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uint rcw_tmp;
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#endif
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uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
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uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
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unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
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@ -127,8 +130,39 @@ void get_sys_info(struct sys_info *sys_info)
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sys_info->freq_localbus = sys_info->freq_systembus /
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CONFIG_SYS_FSL_IFC_CLK_DIV;
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#endif
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}
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#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
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#define HWA_CGA_M2_CLK_SEL 0x00380000
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#define HWA_CGA_M2_CLK_SHIFT 19
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rcw_tmp = in_le32(&gur->rcwsr[5]);
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switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
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case 1:
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sys_info->freq_cga_m2 = freq_c_pll[1];
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break;
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case 2:
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sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
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break;
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case 3:
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sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
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break;
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case 4:
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sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
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break;
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case 6:
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sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
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break;
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case 7:
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sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
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break;
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default:
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printf("Error: Unknown peripheral clock select!\n");
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break;
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}
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#endif
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#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB)
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sys_info->freq_cga_m2 = sys_info->freq_systembus;
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#endif
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}
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int get_clocks(void)
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{
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@ -141,7 +175,16 @@ int get_clocks(void)
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gd->arch.mem2_clk = sys_info.freq_ddrbus2;
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#endif
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#if defined(CONFIG_FSL_ESDHC)
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#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
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#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB)
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gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
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#endif
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#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
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gd->arch.sdhc_clk = sys_info.freq_cga_m2;
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#endif
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#else
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gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
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#endif
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#endif /* defined(CONFIG_FSL_ESDHC) */
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if (gd->cpu_clk != 0)
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@ -24,7 +24,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
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{0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
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{0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
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{0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
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{0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} },
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{0xBB31, {SXGMII1, QXGMII2, PCIE2, PCIE1} },
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{0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
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{0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
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{0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },
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@ -14,6 +14,10 @@
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};
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};
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&esdhc1 {
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mmc-hs200-1_8v;
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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@ -33,12 +33,65 @@
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&esdhc1 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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fpga@66 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "simple-mfd";
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reg = <0x66>;
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mux-mdio@54 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mdio-mux-i2creg";
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reg = <0x54>;
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#mux-control-cells = <1>;
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mux-reg-masks = <0x54 0xf0>;
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mdio-parent-bus = <&mdio0>;
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/* on-board MDIO with a single RGMII PHY */
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mdio@00 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00>;
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qds_phy0: phy@5 {
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reg = <5>;
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};
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};
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/* slot 1 */
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slot1: mdio@40 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40>;
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};
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/* slot 2 */
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slot2: mdio@50 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x50>;
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};
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/* slot 3 */
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slot3: mdio@60 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x60>;
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};
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/* slot 4 */
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slot4: mdio@70 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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};
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};
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};
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i2c-mux@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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@ -108,7 +161,4 @@
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&mdio0 {
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status = "okay";
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qds_phy0: phy@5 {
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reg = <5>;
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};
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};
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@ -33,6 +33,7 @@
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&esdhc1 {
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status = "okay";
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mmc-hs200-1_8v;
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};
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&i2c0 {
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@ -25,6 +25,7 @@
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&esdhc1 {
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status = "okay";
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mmc-hs200-1_8v;
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};
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&i2c0 {
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@ -180,7 +180,7 @@ struct sys_info {
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unsigned long freq_systembus;
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unsigned long freq_ddrbus;
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unsigned long freq_localbus;
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unsigned long freq_sdhc;
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unsigned long freq_cga_m2;
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#ifdef CONFIG_SYS_DPAA_FMAN
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unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
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#endif
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@ -278,6 +278,7 @@ struct sys_info {
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/* frequency of platform PLL */
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unsigned long freq_systembus;
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unsigned long freq_ddrbus;
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unsigned long freq_cga_m2;
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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unsigned long freq_ddrbus2;
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#endif
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@ -105,6 +105,8 @@ static const struct serdes_phy_config serdes1_phy_config[] = {
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EMI1, IO_SLOT_1},
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{WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
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EMI1, IO_SLOT_2} } },
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{14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
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EMI1, IO_SLOT_1} } },
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{15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
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EMI1, IO_SLOT_1},
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{WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
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@ -686,7 +688,7 @@ int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
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struct phy_device *phy_dev, int phandle)
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{
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char phy_node_name[] = "ethernet-phy@00";
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char phy_id_compatible_str[] = "ethernet-phy-id0000.0000";
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char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
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int ret;
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sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
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@ -700,7 +702,7 @@ int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
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return *subnodeoffset;
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}
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sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x",
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sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
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phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
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debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
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@ -20,6 +20,8 @@
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#include <efi_loader.h>
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#include <asm/arch/mmu.h>
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#include <hwconfig.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/config.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include "../common/qixis.h"
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@ -116,6 +118,72 @@ int board_early_init_f(void)
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return 0;
|
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}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_FIXUP
|
||||
int board_fix_fdt(void *fdt)
|
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{
|
||||
char *reg_names, *reg_name;
|
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int names_len, old_name_len, new_name_len, remaining_names_len;
|
||||
struct str_map {
|
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char *old_str;
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char *new_str;
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||||
} reg_names_map[] = {
|
||||
{ "ccsr", "dip" },
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{ "pf_ctrl", "ctrl" }
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};
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int off = -1, i;
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if (IS_SVR_REV(get_svr(), 1, 0))
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return 0;
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||||
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||||
off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
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while (off != -FDT_ERR_NOTFOUND) {
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fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
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strlen("fsl,ls-pcie") + 1);
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||||
reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
|
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&names_len);
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if (!reg_names)
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continue;
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reg_name = reg_names;
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remaining_names_len = names_len - (reg_name - reg_names);
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for (i = 0; (i < ARRAY_SIZE(reg_names_map)) && names_len; i++) {
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old_name_len = strlen(reg_names_map[i].old_str);
|
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new_name_len = strlen(reg_names_map[i].new_str);
|
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if (memcmp(reg_name, reg_names_map[i].old_str,
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old_name_len) == 0) {
|
||||
/* first only leave required bytes for new_str
|
||||
* and copy rest of the string after it
|
||||
*/
|
||||
memcpy(reg_name + new_name_len,
|
||||
reg_name + old_name_len,
|
||||
remaining_names_len - old_name_len);
|
||||
/* Now copy new_str */
|
||||
memcpy(reg_name, reg_names_map[i].new_str,
|
||||
new_name_len);
|
||||
names_len -= old_name_len;
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||||
names_len += new_name_len;
|
||||
}
|
||||
|
||||
reg_name = memchr(reg_name, '\0', remaining_names_len);
|
||||
if (!reg_name)
|
||||
break;
|
||||
|
||||
reg_name += 1;
|
||||
|
||||
remaining_names_len = names_len -
|
||||
(reg_name - reg_names);
|
||||
}
|
||||
|
||||
fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
|
||||
off = fdt_node_offset_by_compatible(fdt, off,
|
||||
"fsl,lx2160a-pcie");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TARGET_LX2160AQDS)
|
||||
void esdhc_dspi_status_fixup(void *blob)
|
||||
{
|
||||
|
@ -283,7 +351,7 @@ int checkboard(void)
|
|||
|
||||
puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
|
||||
puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
|
||||
puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
|
||||
puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -55,4 +55,6 @@ CONFIG_FSL_QSPI=y
|
|||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
|
|
|
@ -74,4 +74,6 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_WDT=y
|
||||
CONFIG_WDT_SP805=y
|
||||
CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
|
@ -9,6 +9,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
|||
CONFIG_AHCI=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_BOARD_FIXUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
|
|
|
@ -10,6 +10,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
|||
CONFIG_AHCI=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_BOARD_FIXUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
|
@ -62,4 +63,6 @@ CONFIG_USB=y
|
|||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
|
@ -167,7 +167,6 @@ config MMC_HS200_SUPPORT
|
|||
The HS200 mode is support by some eMMC. The bus frequency is up to
|
||||
200MHz. This mode requires tuning the IO.
|
||||
|
||||
|
||||
config SPL_MMC_HS200_SUPPORT
|
||||
bool "enable HS200 support in SPL"
|
||||
help
|
||||
|
@ -695,10 +694,19 @@ endif
|
|||
|
||||
config FSL_ESDHC
|
||||
bool "Freescale/NXP eSDHC controller support"
|
||||
select FSL_ESDHC_USE_PERIPHERAL_CLK if MMC_HS200_SUPPORT || MMC_UHS_SUPPORT
|
||||
help
|
||||
This selects support for the eSDHC (Enhanced Secure Digital Host
|
||||
Controller) found on numerous Freescale/NXP SoCs.
|
||||
|
||||
config FSL_ESDHC_USE_PERIPHERAL_CLK
|
||||
bool "enable ESDHC peripheral clock support"
|
||||
depends on FSL_ESDHC
|
||||
help
|
||||
eSDHC supports two reference clocks (platform clock and peripheral clock).
|
||||
Peripheral clock which could provide higher clock frequency is required to
|
||||
be used for tuning of SD UHS mode and eMMC HS200/HS400 modes.
|
||||
|
||||
config FSL_ESDHC_IMX
|
||||
bool "Freescale/NXP i.MX eSDHC controller support"
|
||||
help
|
||||
|
|
|
@ -395,10 +395,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|||
esdhc_write32(®s->cmdarg, cmd->cmdarg);
|
||||
esdhc_write32(®s->xfertyp, xfertyp);
|
||||
|
||||
if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
|
||||
(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
|
||||
flags = IRQSTAT_BRR;
|
||||
|
||||
/* Wait for the command to complete */
|
||||
start = get_timer(0);
|
||||
while (!(esdhc_read32(®s->irqstat) & flags)) {
|
||||
|
@ -458,12 +454,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|||
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
|
||||
esdhc_pio_read_write(priv, data);
|
||||
#else
|
||||
flags = DATA_COMPLETE;
|
||||
if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
|
||||
(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
|
||||
flags = IRQSTAT_BRR;
|
||||
}
|
||||
|
||||
do {
|
||||
irqstat = esdhc_read32(®s->irqstat);
|
||||
|
||||
|
@ -476,7 +466,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|||
err = -ECOMM;
|
||||
goto out;
|
||||
}
|
||||
} while ((irqstat & flags) != flags);
|
||||
} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
|
||||
|
||||
/*
|
||||
* Need invalidate the dcache here again to avoid any
|
||||
|
@ -517,7 +507,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
|
|||
int div = 1;
|
||||
int pre_div = 2;
|
||||
int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
|
||||
int sdhc_clk = priv->sdhc_clk;
|
||||
unsigned int sdhc_clk = priv->sdhc_clk;
|
||||
u32 time_out;
|
||||
u32 value;
|
||||
uint clk;
|
||||
|
||||
if (clock < mmc->cfg->f_min)
|
||||
|
@ -538,11 +530,18 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
|
|||
|
||||
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
|
||||
|
||||
udelay(10000);
|
||||
time_out = 20;
|
||||
value = PRSSTAT_SDSTB;
|
||||
while (!(esdhc_read32(®s->prsstat) & value)) {
|
||||
if (time_out == 0) {
|
||||
printf("fsl_esdhc: Internal clock never stabilised.\n");
|
||||
break;
|
||||
}
|
||||
time_out--;
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
|
||||
|
||||
priv->clock = clock;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
||||
|
@ -1024,6 +1023,8 @@ static int fsl_esdhc_probe(struct udevice *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
mmc_of_parse(dev, &plat->cfg);
|
||||
|
||||
mmc = &plat->mmc;
|
||||
mmc->cfg = &plat->cfg;
|
||||
mmc->dev = dev;
|
||||
|
@ -1081,6 +1082,9 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
|
|||
.get_cd = fsl_esdhc_get_cd,
|
||||
.send_cmd = fsl_esdhc_send_cmd,
|
||||
.set_ios = fsl_esdhc_set_ios,
|
||||
#ifdef MMC_SUPPORTS_TUNING
|
||||
.execute_tuning = fsl_esdhc_execute_tuning,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
@ -87,9 +87,16 @@ static int sp805_wdt_stop(struct udevice *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int sp805_wdt_expire_now(struct udevice *dev, ulong flags)
|
||||
{
|
||||
sp805_wdt_start(dev, 0, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sp805_wdt_probe(struct udevice *dev)
|
||||
{
|
||||
debug("%s: Probing wdt%u\n", __func__, dev->seq);
|
||||
debug("%s: Probing wdt%u (sp805-wdt)\n", __func__, dev->seq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -109,6 +116,7 @@ static const struct wdt_ops sp805_wdt_ops = {
|
|||
.start = sp805_wdt_start,
|
||||
.reset = sp805_wdt_reset,
|
||||
.stop = sp805_wdt_stop,
|
||||
.expire_now = sp805_wdt_expire_now,
|
||||
};
|
||||
|
||||
static const struct udevice_id sp805_wdt_ids[] = {
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* Copyright 2018-2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __LX2_COMMON_H
|
||||
|
@ -199,14 +199,14 @@ unsigned long get_board_ddr_clk(void);
|
|||
"fsl_mc start mc 0x20a00000 0x20e00000\0"
|
||||
|
||||
#define SD_MC_INIT_CMD \
|
||||
"mmc read 0x80000000 0x5000 0x800;" \
|
||||
"mmc read 0x80100000 0x7000 0x800;" \
|
||||
"mmc read 0x80a00000 0x5000 0x1200;" \
|
||||
"mmc read 0x80e00000 0x7000 0x800;" \
|
||||
"env exists secureboot && " \
|
||||
"mmc read 0x80700000 0x3800 0x10 && " \
|
||||
"mmc read 0x80740000 0x3A00 0x10 && " \
|
||||
"esbc_validate 0x80700000 && " \
|
||||
"esbc_validate 0x80740000 ;" \
|
||||
"fsl_mc start mc 0x80000000 0x80100000\0"
|
||||
"fsl_mc start mc 0x80a00000 0x80e00000\0"
|
||||
|
||||
#define EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||
|
@ -265,11 +265,11 @@ unsigned long get_board_ddr_clk(void);
|
|||
|
||||
#define SD_BOOTCOMMAND \
|
||||
"env exists mcinitcmd && mmcinfo; " \
|
||||
"mmc read 0x80001000 0x6800 0x800; " \
|
||||
"mmc read 0x80d00000 0x6800 0x800; " \
|
||||
"env exists mcinitcmd && env exists secureboot " \
|
||||
" && mmc read 0x80780000 0x3C00 0x10 " \
|
||||
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
|
||||
"&& fsl_mc lazyapply dpl 0x80001000;" \
|
||||
"&& fsl_mc lazyapply dpl 0x80d00000;" \
|
||||
"run distro_bootcmd;run sd_bootcmd;" \
|
||||
"env exists secureboot && esbc_halt;"
|
||||
|
||||
|
|
|
@ -205,6 +205,10 @@ struct fsl_esdhc_cfg {
|
|||
int fsl_esdhc_mmc_init(bd_t *bis);
|
||||
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
|
||||
void fdt_fixup_esdhc(void *blob, bd_t *bd);
|
||||
#ifdef MMC_SUPPORTS_TUNING
|
||||
static inline int fsl_esdhc_execute_tuning(struct udevice *dev,
|
||||
uint32_t opcode) {return 0; }
|
||||
#endif
|
||||
#else
|
||||
static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
|
||||
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
|
||||
|
|
Loading…
Add table
Reference in a new issue