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clk: clk_stm32f: Fix stm32_clk_get_rate()

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Wrong parameter was passed to stm32_clk_pll48clk_rate().
sysclk (PLL_p output value) was passed instead of VCO value.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard 2018-02-08 17:20:45 +01:00 • committed by Tom Rini
parent 167f2c90f6
commit aa230be4bf
1 changed files with 7 additions and 5 deletions
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12
drivers/clk/clk_stm32f.c
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@ -230,7 +230,7 @@ static int configure_clocks(struct udevice *dev)
} }
static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
u32 sysclk) u32 vco)
{ {
struct stm32_rcc_regs *regs = priv->base; struct stm32_rcc_regs *regs = priv->base;
u16 pllq, pllm, pllsain, pllsaip; u16 pllq, pllm, pllsain, pllsaip;
@ -254,7 +254,7 @@ static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
return ((priv->hse_rate / pllm) * pllsain) / pllsaip; return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
} }
/* PLL48CLK is selected from PLLQ */ /* PLL48CLK is selected from PLLQ */
return sysclk / pllq; return vco / pllq;
} }
static bool stm32_get_timpre(struct stm32_clk *priv) static bool stm32_get_timpre(struct stm32_clk *priv)
@ -337,6 +337,7 @@ static ulong stm32_clk_get_rate(struct clk *clk)
struct stm32_clk *priv = dev_get_priv(clk->dev); struct stm32_clk *priv = dev_get_priv(clk->dev);
struct stm32_rcc_regs *regs = priv->base; struct stm32_rcc_regs *regs = priv->base;
u32 sysclk = 0; u32 sysclk = 0;
u32 vco;
u16 pllm, plln, pllp; u16 pllm, plln, pllp;
if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) == if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
@ -346,7 +347,8 @@ static ulong stm32_clk_get_rate(struct clk *clk)
>> RCC_PLLCFGR_PLLN_SHIFT); >> RCC_PLLCFGR_PLLN_SHIFT);
pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
sysclk = ((priv->hse_rate / pllm) * plln) / pllp; vco = (priv->hse_rate / pllm) * plln;
sysclk = vco / pllp;
} else { } else {
return -EINVAL; return -EINVAL;
} }
@ -388,14 +390,14 @@ static ulong stm32_clk_get_rate(struct clk *clk)
/* System clock is selected as SDMMC1 clock */ /* System clock is selected as SDMMC1 clock */
return sysclk; return sysclk;
else else
return stm32_clk_pll48clk_rate(priv, sysclk); return stm32_clk_pll48clk_rate(priv, vco);
break; break;
case STM32F7_APB2_CLOCK(SDMMC2): case STM32F7_APB2_CLOCK(SDMMC2):
if (readl(&regs->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL) if (readl(&regs->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
/* System clock is selected as SDMMC2 clock */ /* System clock is selected as SDMMC2 clock */
return sysclk; return sysclk;
else else
return stm32_clk_pll48clk_rate(priv, sysclk); return stm32_clk_pll48clk_rate(priv, vco);
break; break;
/* For timer clock, an additionnal prescaler is used*/ /* For timer clock, an additionnal prescaler is used*/