ColdFire: Add M5373EVB platform support - 2

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> Signed-off by: John Rigby <jrigby@freescale.com>
2025-03-21 06:31:31 +00:00 · 2008-01-14 17:23:08 -06:00 · 2008-01-14 17:23:08 -06:00 · aa5f1f9dc8
commit aa5f1f9dc8
parent 1ac559d4aa
9 changed files with 708 additions and 24 deletions
--- a/1
+++ b/1
@ -649,6 +649,7 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>

 	M5235EVB		mcf52x2
 	M5329EVB		mcf532x
+	M5373EVB		mcf532x
 	M54455EVB		mcf5445x

 Hayden Fraser <Hayden.Fraser@freescale.com>
--- a/3
+++ b/3
@ -649,7 +649,8 @@ LIST_coldfire="			\
 	M5271EVB		\
 	M5272C3			\
 	M5282EVB		\
-	M5329EVB		\
+	M5329AFEE		\
+	M5373EVB		\
 	M54455EVB		\
 	r5200			\
 	TASREG			\
--- a/10
+++ b/10
@ -1811,6 +1811,16 @@ M5329BFEE_config :	unconfig
 	fi
 	@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale

+M5373EVB_config :	unconfig
+	@case "$@" in \
+	M5373EVB_config)	NAND=16;; \
+	esac; \
+	>include/config.h ; \
+	if [ "$${NAND}" != "0" ] ; then \
+		echo "#define NANDFLASH_SIZE	$${NAND}" > $(obj)include/config.h ; \
+	fi
+	@$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale
+
 M54455EVB_config \
 M54455EVB_atmel_config \
 M54455EVB_intel_config \
--- a/cpu/mcf532x/cpu.c
+++ b/cpu/mcf532x/cpu.c
@ -64,6 +64,18 @@ int checkcpu(void)
 	case 0x61:
 		id = 5327;
 		break;
+	case 0x65:
+		id = 5373;
+		break;
+	case 0x68:
+		id = 53721;
+		break;
+	case 0x69:
+		id = 5372;
+		break;
+	case 0x6B:
+		id = 5372;
+		break;
 	}

 	if (id) {
@ -84,6 +96,7 @@ void watchdog_reset(void)
 	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);

 	wdp->sr = 0x5555;	/* Count register */
+	wdp->sr = 0xAAAA;	/* Count register */
 }

 int watchdog_disable(void)
@ -104,8 +117,11 @@ int watchdog_init(void)

 	/* set timeout and enable watchdog */
 	wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
-	wdog_module |= (wdog_module / 8192);
-	wdp->mr = wdog_module;
+#ifdef CONFIG_M5329
+	wdp->mr = (wdog_module / 8192);
+#else
+	wdp->mr = (wdog_module / 4096);
+#endif

 	wdp->cr = WTM_WCR_EN;
 	puts("WATCHDOG:enabled\n");
--- a/doc/README.m5373evb
+++ b/doc/README.m5373evb
@ -0,0 +1,333 @@
+Freescale MCF5373EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 11/08/07
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m5373evb/m5373evb.c	Dram setup
+- board/freescale/m5373evb/mii.c	Mii access
+- board/freescale/m5373evb/Makefile	Makefile
+- board/freescale/m5373evb/config.mk	config make
+- board/freescale/m5373evb/u-boot.lds	Linker description
+
+- cpu/mcf532x/cpu.c		cpu specific code
+- cpu/mcf532x/cpu_init.c	FBCS, Mux pins, icache and RTC extra regs
+- cpu/mcf532x/interrupts.c	cpu specific interrupt support
+- cpu/mcf532x/speed.c		system, pci, flexbus, and cpu clock
+- cpu/mcf532x/Makefile		Makefile
+- cpu/mcf532x/config.mk		config make
+- cpu/mcf532x/start.S		start up assembly code
+
+- doc/README.m5373evb		This readme file
+
+- drivers/net/mcffec.c		ColdFire common FEC driver
+- drivers/serial/mcfuart.c	ColdFire common UART driver
+- drivers/rtc/mcfrtc.c		Realtime clock Driver
+
+- include/asm-m68k/bitops.h		Bit operation function export
+- include/asm-m68k/byteorder.h		Byte order functions
+- include/asm-m68k/fec.h		FEC structure and definition
+- include/asm-m68k/fsl_i2c.h		I2C structure and definition
+- include/asm-m68k/global_data.h	Global data structure
+- include/asm-m68k/immap.h		ColdFire specific header file and driver macros
+- include/asm-m68k/immap_532x.h		mcf532x specific header file
+- include/asm-m68k/io.h			io functions
+- include/asm-m68k/m532x.h		mcf532x specific header file
+- include/asm-m68k/posix_types.h	Posix
+- include/asm-m68k/processor.h		header file
+- include/asm-m68k/ptrace.h		Exception structure
+- include/asm-m68k/rtc.h		Realtime clock header file
+- include/asm-m68k/string.h		String function export
+- include/asm-m68k/timer.h		Timer structure and definition
+- include/asm-m68k/types.h		Data types definition
+- include/asm-m68k/uart.h		Uart structure and definition
+- include/asm-m68k/u-boot.h		u-boot structure
+
+- include/configs/M5373EVB.h		Board specific configuration file
+
+- lib_m68k/board.c			board init function
+- lib_m68k/cache.c
+- lib_m68k/interrupts			Coldfire common interrupt functions
+- lib_m68k/m68k_linux.c
+- lib_m68k/time.c			Timer functions (Dma timer and PIT)
+- lib_m68k/traps.c			Exception init code
+
+1 MCF5373 specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M5373EVB Development Board
+CONFIG_MCF532x		-- define for all MCF532x CPUs
+CONFIG_M5373		-- define for all Freescale MCF5373 CPUs
+CONFIG_M5373EVB		-- define for M5373EVB board
+
+CONFIG_MCFUART		-- define to use common CF Uart driver
+CFG_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE		-- define UART baudrate
+
+CONFIG_MCFRTC		-- define to use common CF RTC driver
+CFG_MCFRTC_BASE		-- provide base address for RTC in immap.h
+CFG_RTC_OSCILLATOR	-- define RTC clock frequency
+RTC_DEBUG		-- define to show RTC debug message
+CONFIG_CMD_DATE		-- enable to use date feature in u-boot
+
+CONFIG_MCFFEC		-- define to use common CF FEC driver
+CONFIG_NET_MULTI	-- define to use multi FEC in u-boot
+CONFIG_MII		-- enable to use MII driver
+CONFIG_CF_DOMII		-- enable to use MII feature in cmd_mii.c
+CFG_DISCOVER_PHY	-- enable PHY discovery
+CFG_RX_ETH_BUFFER	-- Set FEC Receive buffer
+CFG_FAULT_ECHO_LINK_DOWN--
+CFG_FEC0_PINMUX		-- Set FEC0 Pin configuration
+CFG_FEC0_MIIBASE	-- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP	-- set FEC timeout loop
+
+CONFIG_MCFTMR		-- define to use DMA timer
+CONFIG_MCFPIT		-- define to use PIT timer
+
+CONFIG_FSL_I2C		-- define to use FSL common I2C driver
+CONFIG_HARD_I2C		-- define for I2C hardware support
+CONFIG_SOFT_I2C		-- define for I2C bit-banged
+CFG_I2C_SPEED		-- define for I2C speed
+CFG_I2C_SLAVE		-- define for I2C slave address
+CFG_I2C_OFFSET		-- define for I2C base address offset
+CFG_IMMR		-- define for MBAR offset
+
+CFG_MBAR		-- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CFG_INIT_RAM_ADDR	-- defines the base address of the MCF5373 internal SRAM
+
+CFG_CSn_BASE	-- defines the Chip Select Base register
+CFG_CSn_MASK	-- defines the Chip Select Mask register
+CFG_CSn_CTRL	-- defines the Chip Select Control register
+
+CFG_SDRAM_BASE	-- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+	Flash:		0x00000000-0x3FFFFFFF (1024MB)
+	DDR:		0x40000000-0x7FFFFFFF (1024MB)
+	SRAM:		0x80000000-0x8FFFFFFF (256MB)
+	IP:		0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+	linux kernel, you can customize it based on your system requirements:
+	Flash0:		0x00000000-0x00FFFFFF (16MB)
+
+	DDR:		0x40000000-0x4FFFFFFF (256MB)
+	SRAM:		0x80000000-0x80007FFF (32KB)
+	IP:		0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1	To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+   export CROSS_COMPILE=cross-compile-prefix
+   cd u-boot-1.x.x
+   make distclean
+   make M5373EVB_config
+   make
+
+4. SCREEN DUMP
+==============
+4.1 M5373EVB Development board
+    (NOTE: May not show exactly the same)
+
+U-Boot 1.3.0 (Nov 8 2007 - 12:44:08)
+
+CPU:   Freescale MCF5373 (Mask:65 Version:1)
+       CPU CLK 240 Mhz BUS CLK 80 Mhz
+Board: Freescale FireEngine 5373 EVB
+I2C:   ready
+DRAM:  32 MB
+FLASH: 2 MB
+In:    serial
+Out:   serial
+Err:   serial
+NAND:  16 MiB
+Net:   FEC0
+-> print
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+hostname=M5373EVB
+netdev=eth0
+loadaddr=40010000
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
+ethact=FEC0
+u-boot=u-boot.bin
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=261632k
+
+Environment size: 401/8188 bytes
+-> bdinfo
+memstart    = 0x40000000
+memsize     = 0x02000000
+flashstart  = 0x00000000
+flashsize   = 0x00200000
+flashoffset = 0x00000000
+sramstart   = 0x80000000
+sramsize    = 0x00008000
+mbar        = 0xFC000000
+busfreq     =     80 MHz
+ethaddr     = 00:E0:0C:BC:E5:60
+ip_addr     = 192.168.1.3
+baudrate    = 115200 bps
+->
+-> help
+?       - alias for 'help'
+autoscr - run script from memory
+base    - print or set address offset
+bdinfo  - print Board Info structure
+boot    - boot default, i.e., run 'bootcmd'
+bootd   - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm   - boot application image from memory
+bootp	- boot image via network using BootP/TFTP protocol
+bootvx  - Boot vxWorks from an ELF image
+cmp     - memory compare
+coninfo - print console devices and information
+cp      - memory copy
+crc32   - checksum calculation
+date    - get/set/reset date & time
+dcache  - enable or disable data cache
+echo    - echo args to console
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+go      - start application at address 'addr'
+help    - print online help
+icache  - enable or disable instruction cache
+icrc32  - checksum calculation
+iloop   - infinite loop on address range
+imd     - i2c memory display
+iminfo  - print header information for application image
+imls    - list all images found in flash
+imm     - i2c memory modify (auto-incrementing)
+imw     - memory write (fill)
+inm     - memory modify (constant address)
+iprobe  - probe to discover valid I2C chip addresses
+itest	- return true/false on integer compare
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loady   - load binary file over serial line (ymodem mode)
+loop    - infinite loop on address range
+ls	- list files in a directory (default /)
+md      - memory display
+mii     - MII utility commands
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nand	- NAND sub-system
+nboot	- boot from NAND device
+nfs	- boot image via network using NFS protocol
+nm      - memory modify (constant address)
+ping	- send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sleep   - delay execution for some time
+tftpboot- boot image via network using TFTP protocol
+version - print monitor version
+-> tftp 0x40800000 uImage
+Using FEC0 device
+TFTP from server 192.168.1.3; our IP address is 192.168.1.3 Filename 'uImage'.
+Load address: 0x40800000
+Loading: #################################################################
+          #################################################################
+          ##########
+done
+Bytes transferred = 2053270 (1f5496 hex)
+-> bootm 0x40800000
+## Booting image at 40800000 ...
+    Image Name:   Linux Kernel Image
+    Created:      2007-11-07  20:33:08 UTC
+    Image Type:   M68K Linux Kernel Image (gzip compressed)
+    Data Size:    2053206 Bytes =  2 MB
+    Load Address: 40020000
+    Entry Point:  40020000
+    Verifying Checksum ... OK
+    Uncompressing Kernel Image ... OK
+Linux version 2.6.22-uc1 (mattw@loa) (gcc version 4.2.1 (Sourcery G++ Lite 4.2-7
+
+
+uClinux/COLDFIRE(m537x)
+COLDFIRE port done by Greg Ungerer, gerg@snapgear.com Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne Built 1 zonelists.  Total pages: 8128 Kernel command line: rootfstype=romfs PID hash table entries: 128 (order: 7, 512 bytes) Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory available: 28092k/32768k RAM, (1788k kernel code, 244k data) Mount-cache hash table entries: 512
+NET: Registered protocol family 16
+USB-MCF537x: (HOST module) EHCI device is registered
+USB-MCF537x: (OTG module) EHCI device is registered
+USB-MCF537x: (OTG module) UDC device is registered
+usbcore: registered new interface driver usbfs
+usbcore: registered new interface driver hub
+usbcore: registered new device driver usb
+NET: Registered protocol family 2
+IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
+TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered
+JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
+io scheduler noop registered
+io scheduler cfq registered (default)
+ColdFire internal UART serial driver version 1.00 ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
+ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
+ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: module loaded
+nbd: registered device at major 43
+usbcore: registered new interface driver ub FEC ENET Version 0.2
+fec: PHY @ 0x1, ID 0x20005c90 -- DP83848
+eth0: ethernet 00:e0:0c:bc:e5:60
+uclinux[mtd]: RAM probe address=0x4021c22c size=0x22b000 Creating 1 MTD partitions on "RAM":
+0x00000000-0x0022b000 : "ROMfs"
+uclinux[mtd]: set ROMfs to be root filesystem NAND device: Manufacturer ID: 0x20, Chip ID: 0x73 (ST Micro NAND 16MiB 3,3V 8-b) Scanning device for bad blocks Creating 1 MTD partitions on "NAND 16MiB 3,3V 8-bit":
+0x00000000-0x01000000 : "M53xx flash partition 1"
+QSPI: spi->max_speed_hz 300000
+QSPI: Baud set to 255
+SPI: Coldfire master initialized
+M537x - Disable UART1 when using Audio
+udc: Freescale MCF53xx UDC driver version 27 October 2006 init
+udc: MCF53xx USB Device is found. ID=0x5 Rev=0x41 i2c /dev entries driver
+usbcore: registered new interface driver usbhid
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 17
+VFS: Mounted root (romfs filesystem) readonly.
+Freeing unused kernel memory: 64k freed (0x401f5000 - 0x40204000) init started:  BusyBox v1.00 (2007.11.07-19:57+0000) multi-call binary?Setting e Mounting filesystems
+mount: Mounting devpts on /dev/pts failed: No such device
+mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory Starting syslogd and klogd Setting up networking on loopback device:
+Setting up networking on eth0:
+info, udhcpc (v0.9.9-pre) started
+eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
+debug, Sending discover...
+debug, Sending discover...
+debug, Sending select for 172.27.0.130...
+info, Lease of 172.27.0.130 obtained, lease time 43200 deleting routers
+route: SIOC[ADD|DEL]RT: No such process
+adding dns 172.27.0.1
+Starting the boa webserver:
+Setting time from ntp server: ntp.cs.strath.ac.uk
+ntp.cs.strath.ac.uk: Unknown host
+
+
+BusyBox v1.00 (2007.11.07-19:57+0000) Built-in shell (msh) Enter 'help' for a list of built-in commands.
+
+#
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@ -169,7 +169,7 @@
 #endif
 #endif				/* CONFIG_M5282 */

-#ifdef CONFIG_M5329
+#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
 #include <asm/immap_5329.h>
 #include <asm/m5329.h>

@ -197,7 +197,7 @@

 #define CFG_INTR_BASE		(MMAP_INTC0)
 #define CFG_NUM_IRQS		(128)
-#endif				/* CONFIG_M5329 */
+#endif				/* CONFIG_M5329 && CONFIG_M5373 */

 #ifdef CONFIG_M54455
 #include <asm/immap_5445x.h>
--- a/include/asm-m68k/immap_5329.h
+++ b/include/asm-m68k/immap_5329.h
@ -378,91 +378,133 @@ typedef struct rcm {
 /* GPIO port registers */
 typedef struct gpio_ctrl {
 	/* Port Output Data Registers */
+#ifdef CONFIG_M5329
 	u8 podr_fech;		/* 0x00 */
 	u8 podr_fecl;		/* 0x01 */
+#else
+	u16 res00;		/* 0x00 - 0x01 */
+#endif
 	u8 podr_ssi;		/* 0x02 */
 	u8 podr_busctl;		/* 0x03 */
 	u8 podr_be;		/* 0x04 */
 	u8 podr_cs;		/* 0x05 */
 	u8 podr_pwm;		/* 0x06 */
 	u8 podr_feci2c;		/* 0x07 */
-	u8 res1;		/* 0x08 */
+	u8 res08;		/* 0x08 */
 	u8 podr_uart;		/* 0x09 */
 	u8 podr_qspi;		/* 0x0A */
 	u8 podr_timer;		/* 0x0B */
-	u8 res2;		/* 0x0C */
+#ifdef CONFIG_M5329
+	u8 res0C;		/* 0x0C */
 	u8 podr_lcddatah;	/* 0x0D */
 	u8 podr_lcddatam;	/* 0x0E */
 	u8 podr_lcddatal;	/* 0x0F */
 	u8 podr_lcdctlh;	/* 0x10 */
 	u8 podr_lcdctll;	/* 0x11 */
+#else
+	u16 res0C;		/* 0x0C - 0x0D */
+	u8 podr_fech;		/* 0x0E */
+	u8 podr_fecl;		/* 0x0F */
+	u16 res10[3];		/* 0x10 - 0x15 */
+#endif

 	/* Port Data Direction Registers */
-	u16 res3;		/* 0x12 - 0x13 */
+#ifdef CONFIG_M5329
+	u16 res12;		/* 0x12 - 0x13 */
 	u8 pddr_fech;		/* 0x14 */
 	u8 pddr_fecl;		/* 0x15 */
+#endif
 	u8 pddr_ssi;		/* 0x16 */
 	u8 pddr_busctl;		/* 0x17 */
 	u8 pddr_be;		/* 0x18 */
 	u8 pddr_cs;		/* 0x19 */
 	u8 pddr_pwm;		/* 0x1A */
 	u8 pddr_feci2c;		/* 0x1B */
-	u8 res4;		/* 0x1C */
+	u8 res1C;		/* 0x1C */
 	u8 pddr_uart;		/* 0x1D */
 	u8 pddr_qspi;		/* 0x1E */
 	u8 pddr_timer;		/* 0x1F */
-	u8 res5;		/* 0x20 */
+#ifdef CONFIG_M5329
+	u8 res20;		/* 0x20 */
 	u8 pddr_lcddatah;	/* 0x21 */
 	u8 pddr_lcddatam;	/* 0x22 */
 	u8 pddr_lcddatal;	/* 0x23 */
 	u8 pddr_lcdctlh;	/* 0x24 */
 	u8 pddr_lcdctll;	/* 0x25 */
-	u16 res6;		/* 0x26 - 0x27 */
+	u16 res26;		/* 0x26 - 0x27 */
+#else
+	u16 res20;		/* 0x20 - 0x21 */
+	u8 pddr_fech;		/* 0x22 */
+	u8 pddr_fecl;		/* 0x23 */
+	u16 res24[3];		/* 0x24 - 0x29 */
+#endif

 	/* Port Data Direction Registers */
+#ifdef CONFIG_M5329
 	u8 ppd_fech;		/* 0x28 */
 	u8 ppd_fecl;		/* 0x29 */
+#endif
 	u8 ppd_ssi;		/* 0x2A */
 	u8 ppd_busctl;		/* 0x2B */
 	u8 ppd_be;		/* 0x2C */
 	u8 ppd_cs;		/* 0x2D */
 	u8 ppd_pwm;		/* 0x2E */
 	u8 ppd_feci2c;		/* 0x2F */
-	u8 res7;		/* 0x30 */
+	u8 res30;		/* 0x30 */
 	u8 ppd_uart;		/* 0x31 */
 	u8 ppd_qspi;		/* 0x32 */
 	u8 ppd_timer;		/* 0x33 */
-	u8 res8;		/* 0x34 */
+#ifdef CONFIG_M5329
+	u8 res34;		/* 0x34 */
 	u8 ppd_lcddatah;	/* 0x35 */
 	u8 ppd_lcddatam;	/* 0x36 */
 	u8 ppd_lcddatal;	/* 0x37 */
 	u8 ppd_lcdctlh;		/* 0x38 */
 	u8 ppd_lcdctll;		/* 0x39 */
-	u16 res9;		/* 0x3A - 0x3B */
+	u16 res3A;		/* 0x3A - 0x3B */
+#else
+	u16 res34;		/* 0x34 - 0x35 */
+	u8 ppd_fech;		/* 0x36 */
+	u8 ppd_fecl;		/* 0x37 */
+	u16 res38[3];		/* 0x38 - 0x3D */
+#endif

 	/* Port Clear Output Data Registers */
-	u8 pclrr_fech;		/* 0x3C */
-	u8 pclrr_fecl;		/* 0x3D */
+#ifdef CONFIG_M5329
+	u8 res3C;		/* 0x3C */
+	u8 pclrr_fech;		/* 0x3D */
+	u8 pclrr_fecl;		/* 0x3E */
+#else
 	u8 pclrr_ssi;		/* 0x3E */
+#endif
 	u8 pclrr_busctl;	/* 0x3F */
 	u8 pclrr_be;		/* 0x40 */
 	u8 pclrr_cs;		/* 0x41 */
 	u8 pclrr_pwm;		/* 0x42 */
 	u8 pclrr_feci2c;	/* 0x43 */
-	u8 res10;		/* 0x44 */
+	u8 res44;		/* 0x44 */
 	u8 pclrr_uart;		/* 0x45 */
 	u8 pclrr_qspi;		/* 0x46 */
 	u8 pclrr_timer;		/* 0x47 */
-	u8 res11;		/* 0x48 */
-	u8 pclrr_lcddatah;	/* 0x49 */
-	u8 pclrr_lcddatam;	/* 0x4A */
-	u8 pclrr_lcddatal;	/* 0x4B */
+#ifdef CONFIG_M5329
+	u8 pclrr_lcddatah;	/* 0x48 */
+	u8 pclrr_lcddatam;	/* 0x49 */
+	u8 pclrr_lcddatal;	/* 0x4A */
+	u8 pclrr_ssi;		/* 0x4B */
 	u8 pclrr_lcdctlh;	/* 0x4C */
 	u8 pclrr_lcdctll;	/* 0x4D */
-	u16 res12;		/* 0x4E - 0x4F */
+	u16 res4E;		/* 0x4E - 0x4F */
+#else
+	u16 res48;		/* 0x48 - 0x49 */
+	u8 pclrr_fech;		/* 0x4A */
+	u8 pclrr_fecl;		/* 0x4B */
+	u8 res4C[5];		/* 0x4C - 0x50 */
+#endif

 	/* Pin Assignment Registers */
+#ifdef CONFIG_M5329
 	u8 par_fec;		/* 0x50 */
+#endif
 	u8 par_pwm;		/* 0x51 */
 	u8 par_busctl;		/* 0x52 */
 	u8 par_feci2c;		/* 0x53 */
@ -472,15 +514,20 @@ typedef struct gpio_ctrl {
 	u16 par_uart;		/* 0x58 */
 	u16 par_qspi;		/* 0x5A */
 	u8 par_timer;		/* 0x5C */
+#ifdef CONFIG_M5329
 	u8 par_lcddata;		/* 0x5D */
 	u16 par_lcdctl;		/* 0x5E */
+#else
+	u8 par_fec;		/* 0x5D */
+	u16 res5E;		/* 0x5E - 0x5F */
+#endif
 	u16 par_irq;		/* 0x60 */
-	u16 res16;		/* 0x62 - 0x63 */
+	u16 res62;		/* 0x62 - 0x63 */

 	/* Mode Select Control Registers */
 	u8 mscr_flexbus;	/* 0x64 */
 	u8 mscr_sdram;		/* 0x65 */
-	u16 res17;		/* 0x66 - 0x67 */
+	u16 res66;		/* 0x66 - 0x67 */

 	/* Drive Strength Control Registers */
 	u8 dscr_i2c;		/* 0x68 */
@ -490,7 +537,11 @@ typedef struct gpio_ctrl {
 	u8 dscr_qspi;		/* 0x6C */
 	u8 dscr_timer;		/* 0x6D */
 	u8 dscr_ssi;		/* 0x6E */
+#ifdef CONFIG_M5329
 	u8 dscr_lcd;		/* 0x6F */
+#else
+	u8 res6F;		/* 0x6F */
+#endif
 	u8 dscr_debug;		/* 0x70 */
 	u8 dscr_clkrst;		/* 0x71 */
 	u8 dscr_irq;		/* 0x72 */
--- a/include/asm-m68k/m5329.h
+++ b/include/asm-m68k/m5329.h
@ -1118,6 +1118,7 @@
 #define GPIO_PCLRR_LCDCTLL7		(0x80)

 /* Bit definitions and macros for GPIO_PAR_FEC */
+#ifdef CONFIG_M5329
 #define GPIO_PAR_FEC_MII(x)		(((x)&0x03)<<0)
 #define GPIO_PAR_FEC_7W(x)		(((x)&0x03)<<2)
 #define GPIO_PAR_FEC_7W_GPIO		(0x00)
@ -1126,6 +1127,10 @@
 #define GPIO_PAR_FEC_MII_GPIO		(0x00)
 #define GPIO_PAR_FEC_MII_UART		(0x01)
 #define GPIO_PAR_FEC_MII_FEC		(0x03)
+#else
+#define GPIO_PAR_FEC_7W_FEC		(0x08)
+#define GPIO_PAR_FEC_MII_FEC		(0x02)
+#endif

 /* Bit definitions and macros for GPIO_PAR_PWM */
 #define GPIO_PAR_PWM1(x)		(((x)&0x03)<<0)
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@ -0,0 +1,267 @@
+/*
+ * Configuation settings for the Freescale MCF5373 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5373EVB_H
+#define _M5373EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF532x		/* define processor family */
+#define CONFIG_M5373		/* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	3360	/* timeout in ms, max is 3.36 sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#ifdef NANDFLASH_SIZE
+#      define CONFIG_CMD_NAND
+#endif
+
+#define CFG_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_NET_MULTI		1
+#	define CONFIG_MII		1
+#	define CFG_DISCOVER_PHY
+#	define CFG_RX_ETH_BUFFER	8
+#	define CFG_FAULT_ECHO_LINK_DOWN
+
+#	define CFG_FEC0_PINMUX		0
+#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP 	50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CFG_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CFG_FAULT_ECHO_LINK_DOWN
+#			define CFG_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CFG_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C		/* I2C with hw support */
+#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CFG_I2C_SPEED		80000
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_OFFSET		0x58000
+#define CFG_IMMR		CFG_MBAR
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		M5373EVB
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"			\
+	"loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0"	\
+	"u-boot=u-boot.bin\0"	\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"	\
+	"prog=prot off 0 2ffff;"	\
+	"era 0 2ffff;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"	\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CFG_PROMPT		"-> "
+#define CFG_LONGHELP		/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CFG_LOAD_ADDR		0x40010000
+
+#define CFG_HZ			1000
+#define CFG_CLK			80000000
+#define CFG_CPU_CLK		CFG_CLK * 3
+
+#define CFG_MBAR		0xFC000000
+
+#define CFG_LATCH_ADDR		(CFG_CS1_BASE + 0x80000)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x80000000
+#define CFG_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL	0x221
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x40000000
+#define CFG_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CFG_SDRAM_CFG1		0x53722730
+#define CFG_SDRAM_CFG2		0x56670000
+#define CFG_SDRAM_CTRL		0xE1092000
+#define CFG_SDRAM_EMOD		0x40010000
+#define CFG_SDRAM_MODE		0x018D0000
+
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN	64*1024
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+#	define CFG_FLASH_CFI_DRIVER	1
+#	define CFG_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
+
+#ifdef NANDFLASH_SIZE
+#	define CFG_MAX_NAND_DEVICE	1
+#	define CFG_NAND_BASE		CFG_CS2_BASE
+#	define CFG_NAND_SIZE		1
+#	define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#	define NAND_MAX_CHIPS		1
+#	define NAND_ALLOW_ERASE_ALL	1
+#	define CONFIG_JFFS2_NAND	1
+#	define CONFIG_JFFS2_DEV		"nand0"
+#	define CONFIG_JFFS2_PART_SIZE	(CFG_CS2_MASK & ~1)
+#	define CONFIG_JFFS2_PART_OFFSET	0x00000000
+#endif
+
+#define CFG_FLASH_BASE		CFG_CS0_BASE
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_IS_EMBEDDED	1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - NAND Flash 16, 32, or 64MB
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CFG_CS0_BASE		0
+#define CFG_CS0_MASK		0x007f0001
+#define CFG_CS0_CTRL		0x00001fa0
+
+#define CFG_CS1_BASE		0x10000000
+#define CFG_CS1_MASK		0x001f0001
+#define CFG_CS1_CTRL		0x002A3780
+
+#ifdef NANDFLASH_SIZE
+#define CFG_CS2_BASE		0x20000000
+#define CFG_CS2_MASK		((NANDFLASH_SIZE << 20) | 1)
+#define CFG_CS2_CTRL		0x00001f60
+#endif
+
+#endif				/* _M5373EVB_H */