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mtd: nand: pxa3xx: enable NAND controller if the SoC needs it
Based on Linux kernel commit fc256f5789cb ("mtd: nand: pxa3xx: enable NAND controller if the SoC needs it"). This commit adds support for the Armada 8040 nand controller. The kernel commit says this: Marvell recent SoCs like A7k/A8k do not boot with NAND flash controller activated by default. Enabling the controller is a matter of writing in a system controller register that may also be used for other NAND related choices. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
This commit is contained in:
parent
6d1edab44c
commit
aaedaaae63
2 changed files with 44 additions and 10 deletions
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@ -196,6 +196,8 @@ config NAND_PXA3XX
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bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
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select SYS_NAND_SELF_INIT
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select DM_MTD
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select REGMAP
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select SYSCON
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imply CMD_NAND
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help
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This enables the driver for the NAND flash device found on
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@ -22,6 +22,8 @@
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/types.h>
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#include <syscon.h>
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#include <regmap.h>
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#include <dm/uclass.h>
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#include <dm/read.h>
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@ -119,6 +121,10 @@ DECLARE_GLOBAL_DATA_PTR;
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#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
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#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
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/* System control register and bit to enable NAND on some SoCs */
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#define GENCONF_SOC_DEVICE_MUX 0x208
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#define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
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/*
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* This should be large enough to read 'ONFI' and 'JEDEC'.
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* Let's use 7 bytes, which is the maximum ID count supported
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@ -159,6 +165,7 @@ enum {
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enum pxa3xx_nand_variant {
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PXA3XX_NAND_VARIANT_PXA,
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PXA3XX_NAND_VARIANT_ARMADA370,
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PXA3XX_NAND_VARIANT_ARMADA_8K,
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};
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struct pxa3xx_nand_host {
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@ -424,13 +431,16 @@ static const struct udevice_id pxa3xx_nand_dt_ids[] = {
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.compatible = "marvell,mvebu-pxa3xx-nand",
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.data = PXA3XX_NAND_VARIANT_ARMADA370,
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},
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{
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.compatible = "marvell,armada-8k-nand-controller",
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.data = PXA3XX_NAND_VARIANT_ARMADA_8K,
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},
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{}
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};
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static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void)
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static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(struct udevice *dev)
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{
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/* We only support the Armada 370/XP/38x for now */
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return PXA3XX_NAND_VARIANT_ARMADA370;
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return dev_get_driver_data(dev);
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}
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static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
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@ -707,7 +717,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
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info->retcode = ERR_UNCORERR;
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if (status & NDSR_CORERR) {
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info->retcode = ERR_CORERR;
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
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if ((info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
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info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) &&
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info->ecc_bch)
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info->ecc_err_cnt = NDSR_ERR_CNT(status);
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else
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@ -762,7 +773,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
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nand_writel(info, NDCB0, info->ndcb2);
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/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
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info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
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nand_writel(info, NDCB0, info->ndcb3);
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}
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@ -1676,7 +1688,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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}
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/* Device detection must be done with ECC disabled */
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
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info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
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nand_writel(info, NDECCCTRL, 0x0);
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if (nand_scan_ident(mtd, 1, NULL))
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@ -1726,7 +1739,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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* (aka split) command handling,
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*/
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if (mtd->writesize > info->chunk_size) {
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
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info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) {
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chip->cmdfunc = nand_cmdfunc_extended;
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} else {
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dev_err(mtd->dev,
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@ -1762,7 +1776,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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return nand_scan_tail(mtd);
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}
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static int alloc_nand_resource(struct pxa3xx_nand_info *info)
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static int alloc_nand_resource(struct udevice *dev, struct pxa3xx_nand_info *info)
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{
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struct pxa3xx_nand_platform_data *pdata;
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struct pxa3xx_nand_host *host;
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@ -1774,7 +1788,7 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info)
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if (pdata->num_cs <= 0)
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return -ENODEV;
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info->variant = pxa3xx_nand_get_variant();
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info->variant = pxa3xx_nand_get_variant(dev);
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for (cs = 0; cs < pdata->num_cs; cs++) {
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chip = (struct nand_chip *)
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((u8 *)&info[1] + sizeof(*host) * cs);
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@ -1810,6 +1824,24 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info)
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/* initialize all interrupts to be disabled */
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disable_int(info, NDSR_MASK);
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/*
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* Some SoCs like A7k/A8k need to enable manually the NAND
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* controller to avoid being bootloader dependent. This is done
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* through the use of a single bit in the System Functions registers.
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*/
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if (pxa3xx_nand_get_variant(dev) == PXA3XX_NAND_VARIANT_ARMADA_8K) {
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struct regmap *sysctrl_base = syscon_regmap_lookup_by_phandle(
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dev, "marvell,system-controller");
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u32 reg;
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if (IS_ERR(sysctrl_base))
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return PTR_ERR(sysctrl_base);
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regmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, ®);
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reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN;
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regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
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}
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return 0;
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}
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@ -1864,7 +1896,7 @@ static int pxa3xx_nand_probe(struct udevice *dev)
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pdata = info->pdata;
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ret = alloc_nand_resource(info);
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ret = alloc_nand_resource(dev, info);
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if (ret) {
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dev_err(dev, "alloc nand resource failed\n");
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return ret;
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