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pci: pcie_imx: Fix hang on mx6qp

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PCI driver currently hangs on mx6qp.

Toggle the reset bit with the appropriate timings to fix the issue.

Based on the FSL kernel driver implementation.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Fabio Estevam 2015-10-13 11:01:27 -03:00 • committed by Tom Rini
parent cb4c833b74
commit aaf87f03ad
2 changed files with 10 additions and 0 deletions
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2
arch/arm/include/asm/arch-mx6/iomux.h
View file

@ -18,6 +18,8 @@
#define IOMUXC_GPR1_REF_SSP_EN (1 << 16)
#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18)
#define IOMUXC_GPR1_PCIE_SW_RST (1 << 29)
/*
* IOMUXC_GPR5 bit fields
*/

8
drivers/pci/pcie_imx.c
View file

@ -19,6 +19,7 @@
#include <asm/io.h>
#include <linux/sizes.h>
#include <errno.h>
#include <asm/arch/sys_proto.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
@ -430,6 +431,10 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
static int imx6_pcie_assert_core_reset(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
if (is_mx6dqp())
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
#if defined(CONFIG_MX6SX)
struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
@ -536,6 +541,9 @@ static int imx6_pcie_deassert_core_reset(void)
enable_pcie_clock();
if (is_mx6dqp())
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
/*
* Wait for the clock to settle a bit, when the clock are sourced
* from the CPU, we need about 30 ms to settle.