mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 05:31:32 +00:00
Merge git://git.denx.de/u-boot-imx
This commit is contained in:
commit
ab1af91093
86 changed files with 8264 additions and 971 deletions
|
@ -660,6 +660,12 @@ config ARCH_MESON
|
|||
targeted at media players and tablet computers. We currently
|
||||
support the S905 (GXBaby) 64-bit SoC.
|
||||
|
||||
config ARCH_MX8M
|
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bool "NXP i.MX8M platform"
|
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select ARM64
|
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select DM
|
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select SUPPORT_SPL
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|
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config ARCH_MX25
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bool "NXP MX25"
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select CPU_ARM926EJS
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||||
|
@ -1254,13 +1260,15 @@ source "arch/arm/cpu/armv7/ls102xa/Kconfig"
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|||
|
||||
source "arch/arm/mach-imx/mx2/Kconfig"
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|
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source "arch/arm/mach-imx/mx7ulp/Kconfig"
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||||
|
||||
source "arch/arm/mach-imx/mx7/Kconfig"
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source "arch/arm/mach-imx/mx5/Kconfig"
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||||
|
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source "arch/arm/mach-imx/mx6/Kconfig"
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|
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source "arch/arm/mach-imx/mx5/Kconfig"
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source "arch/arm/mach-imx/mx7/Kconfig"
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|
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source "arch/arm/mach-imx/mx7ulp/Kconfig"
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|
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source "arch/arm/mach-imx/mx8m/Kconfig"
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source "arch/arm/mach-omap2/Kconfig"
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|
|
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@ -95,11 +95,11 @@ libs-y += arch/arm/cpu/
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libs-y += arch/arm/lib/
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ifeq ($(CONFIG_SPL_BUILD),y)
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ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35))
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ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m))
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libs-y += arch/arm/mach-imx/
|
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endif
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else
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ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
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ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610))
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libs-y += arch/arm/mach-imx/
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endif
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endif
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||||
|
|
|
@ -385,9 +385,11 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
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imx6sl-evk.dtb \
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imx6sll-evk.dtb \
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imx6dl-icore.dtb \
|
||||
imx6dl-icore-mipi.dtb \
|
||||
imx6dl-icore-rqs.dtb \
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||||
imx6q-cm-fx6.dtb \
|
||||
imx6q-icore.dtb \
|
||||
imx6q-icore-mipi.dtb \
|
||||
imx6q-icore-rqs.dtb \
|
||||
imx6q-logicpd.dtb \
|
||||
imx6sx-sabreauto.dtb \
|
||||
|
|
92
arch/arm/dts/fsl-imx8-ca53.dtsi
Normal file
92
arch/arm/dts/fsl-imx8-ca53.dtsi
Normal file
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/{
|
||||
cpus {
|
||||
#address-cells = <2>;
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||||
#size-cells = <0>;
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||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_SLEEP: cpu-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0000000>;
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||||
entry-latency-us = <700>;
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exit-latency-us = <250>;
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min-residency-us = <1000>;
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};
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||||
|
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CLUSTER_SLEEP: cluster-sleep {
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||||
compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1000000>;
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||||
entry-latency-us = <1000>;
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||||
exit-latency-us = <700>;
|
||||
min-residency-us = <2700>;
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||||
wakeup-latency-us = <1500>;
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||||
};
|
||||
};
|
||||
|
||||
/* We have 1 clusters having 4 Cortex-A53 cores */
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A53_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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cpu-idle-states = <&CPU_SLEEP>;
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};
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A53_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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cpu-idle-states = <&CPU_SLEEP>;
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||||
};
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|
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A53_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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||||
enable-method = "psci";
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||||
next-level-cache = <&A53_L2>;
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||||
cpu-idle-states = <&CPU_SLEEP>;
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||||
};
|
||||
|
||||
A53_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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cpu-idle-states = <&CPU_SLEEP>;
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};
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A53_L2: l2-cache0 {
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||||
compatible = "cache";
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||||
};
|
||||
};
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||||
|
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psci {
|
||||
compatible = "arm,psci-1.0";
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||||
method = "smc";
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||||
cpu_suspend = <0xc4000001>;
|
||||
cpu_off = <0xc4000002>;
|
||||
cpu_on = <0xc4000003>;
|
||||
};
|
||||
};
|
429
arch/arm/dts/fsl-imx8mq.dtsi
Normal file
429
arch/arm/dts/fsl-imx8mq.dtsi
Normal file
|
@ -0,0 +1,429 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "fsl-imx8-ca53.dtsi"
|
||||
#include <dt-bindings/clock/imx8mq-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/pins-imx8mq.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,imx8mq";
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||||
interrupt-parent = <&gpc>;
|
||||
#address-cells = <2>;
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||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &fec1;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@38800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
|
||||
<0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
|
||||
IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
|
||||
IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
|
||||
IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
|
||||
IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
|
||||
clock-frequency = <8333333>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
power: power-controller {
|
||||
compatible = "fsl,imx8mq-pm-domain";
|
||||
num-domains = <11>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
pwm2: pwm@30670000 {
|
||||
compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x0 0x30670000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
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<&clk IMX8MQ_CLK_PWM2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@30200000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0 0x30200000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@30210000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0 0x30210000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@30220000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0 0x30220000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@30230000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0 0x30230000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@30240000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0 0x30240000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
tmu: tmu@30260000 {
|
||||
compatible = "fsl,imx8mq-tmu";
|
||||
reg = <0x0 0x30260000 0x0 0x10000>;
|
||||
interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
little-endian;
|
||||
u-boot,dm-pre-reloc;
|
||||
fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
|
||||
fsl,tmu-calibration = <0x00000000 0x00000020
|
||||
0x00000001 0x00000028
|
||||
0x00000002 0x00000030
|
||||
0x00000003 0x00000038
|
||||
0x00000004 0x00000040
|
||||
0x00000005 0x00000048
|
||||
0x00000006 0x00000050
|
||||
0x00000007 0x00000058
|
||||
0x00000008 0x00000060
|
||||
0x00000009 0x00000068
|
||||
0x0000000a 0x00000070
|
||||
0x0000000b 0x00000077
|
||||
|
||||
0x00010000 0x00000057
|
||||
0x00010001 0x0000005b
|
||||
0x00010002 0x0000005f
|
||||
0x00010003 0x00000063
|
||||
0x00010004 0x00000067
|
||||
0x00010005 0x0000006b
|
||||
0x00010006 0x0000006f
|
||||
0x00010007 0x00000073
|
||||
0x00010008 0x00000077
|
||||
0x00010009 0x0000007b
|
||||
0x0001000a 0x0000007f
|
||||
|
||||
0x00020000 0x00000002
|
||||
0x00020001 0x0000000e
|
||||
0x00020002 0x0000001a
|
||||
0x00020003 0x00000026
|
||||
0x00020004 0x00000032
|
||||
0x00020005 0x0000003e
|
||||
0x00020006 0x0000004a
|
||||
0x00020007 0x00000056
|
||||
0x00020008 0x00000062
|
||||
|
||||
0x00030000 0x00000000
|
||||
0x00030001 0x00000008
|
||||
0x00030002 0x00000010
|
||||
0x00030003 0x00000018
|
||||
0x00030004 0x00000020
|
||||
0x00030005 0x00000028
|
||||
0x00030006 0x00000030
|
||||
0x00030007 0x00000038>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
/* cpu thermal */
|
||||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <2000>;
|
||||
thermal-sensors = <&tmu>;
|
||||
trips {
|
||||
cpu_alert0: trip0 {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
cpu_crit0: trip1 {
|
||||
temperature = <125000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lcdif: lcdif@30320000 {
|
||||
compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
|
||||
reg = <0x0 0x30320000 0x0 0x10000>;
|
||||
clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
|
||||
<&clk IMX8MQ_CLK_DUMMY>,
|
||||
<&clk IMX8MQ_CLK_DUMMY>;
|
||||
clock-names = "pix", "axi", "disp_axi";
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
|
||||
assigned-clock-rate = <594000000>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@30330000 {
|
||||
compatible = "fsl,imx8mq-iomuxc";
|
||||
reg = <0x0 0x30330000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@30340000 {
|
||||
compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
|
||||
reg = <0x0 0x30340000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
|
||||
reg = <0x0 0x30350000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
anatop: anatop@30360000 {
|
||||
compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
|
||||
"syscon", "simple-bus";
|
||||
reg = <0x0 0x30360000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
clk: ccm@30380000 {
|
||||
compatible = "fsl,imx8mq-ccm";
|
||||
reg = <0x0 0x30380000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gpc: gpc@303a0000 {
|
||||
compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
|
||||
reg = <0x0 0x303a0000 0x0 0x10000>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
usdhc1: usdhc@30b40000 {
|
||||
compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x0 0x30b40000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
|
||||
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: usdhc@30b50000 {
|
||||
compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x0 0x30b50000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
|
||||
<&clk IMX8MQ_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec1: ethernet@30be0000 {
|
||||
compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x0 0x30be0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
|
||||
<&clk IMX8MQ_CLK_ENET_REF_DIV>,
|
||||
<&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
|
||||
<&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
|
||||
<&clk IMX8MQ_CLK_ENET_REF_SRC>,
|
||||
<&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
|
||||
<&clk IMX8MQ_SYS2_PLL_100M>,
|
||||
<&clk IMX8MQ_SYS2_PLL_125M>;
|
||||
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
|
||||
stop-mode = <&gpr 0x10 3>;
|
||||
fsl,num-tx-queues=<3>;
|
||||
fsl,num-rx-queues=<3>;
|
||||
fsl,wakeup_irq = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
imx_ion {
|
||||
compatible = "fsl,mxc-ion";
|
||||
fsl,heap-id = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a20000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@30a30000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a30000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@30a40000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a40000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@30a50000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a50000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog1: wdog@30280000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0 0x30280000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog2: wdog@30290000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0 0x30290000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog3: wdog@302a0000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0 0x302a0000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma_cap: dma_cap {
|
||||
compatible = "dma-capability";
|
||||
only-dma-mask32 = <1>;
|
||||
};
|
||||
|
||||
qspi: qspi@30bb0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-qspi";
|
||||
reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
|
||||
<&clk IMX8MQ_CLK_QSPI_ROOT>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
#cooling-cells = <2>;
|
||||
};
|
21
arch/arm/dts/imx6dl-icore-mipi.dts
Normal file
21
arch/arm/dts/imx6dl-icore-mipi.dts
Normal file
|
@ -0,0 +1,21 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2017 Engicam S.r.l.
|
||||
* Copyright (C) 2017 Amarula Solutions B.V.
|
||||
* Author: Jagan Teki <jagan@amarulasolutions.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-icore.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit";
|
||||
compatible = "engicam,imx6-icore", "fsl,imx6dl";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
u-boot,dm-spl;
|
||||
status = "okay";
|
||||
};
|
21
arch/arm/dts/imx6q-icore-mipi.dts
Normal file
21
arch/arm/dts/imx6q-icore-mipi.dts
Normal file
|
@ -0,0 +1,21 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2017 Engicam S.r.l.
|
||||
* Copyright (C) 2017 Amarula Solutions B.V.
|
||||
* Author: Jagan Teki <jagan@amarulasolutions.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-icore.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Engicam i.CoreM6 Quad/Dual MIPI Starter Kit";
|
||||
compatible = "engicam,imx6-icore", "fsl,imx6q";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
u-boot,dm-spl;
|
||||
status = "okay";
|
||||
};
|
|
@ -44,6 +44,10 @@
|
|||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc1 = &usdhc3;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
|
@ -126,6 +130,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
no-1-8-v;
|
||||
non-removable;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
|
@ -219,4 +231,20 @@
|
|||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
u-boot,dm-spl;
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "imx6ull.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
#include <dt-bindings/clock/imx6ul-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "imx6ull-pinfunc.h"
|
||||
#include "imx6ull-pinfunc-snvs.h"
|
||||
|
|
|
@ -134,6 +134,28 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
|
||||
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
|
||||
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
|
||||
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
|
||||
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
|
||||
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
|
||||
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
|
||||
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
|
||||
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
|
||||
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
|
||||
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
|
||||
|
@ -147,6 +169,28 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
|
||||
MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
|
||||
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
|
||||
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
|
||||
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
|
||||
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
|
||||
MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
|
||||
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
|
||||
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
|
||||
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
|
||||
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
|
||||
|
@ -162,6 +206,38 @@
|
|||
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
|
||||
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
|
||||
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -287,23 +363,35 @@
|
|||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
|
||||
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
|
||||
vmmc-supply = <®_sd1_vmmc>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
||||
non-removable;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -25,12 +25,14 @@
|
|||
#define MXC_CPU_MX6QP 0x69
|
||||
#define MXC_CPU_MX7S 0x71 /* dummy ID */
|
||||
#define MXC_CPU_MX7D 0x72
|
||||
#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */
|
||||
#define MXC_CPU_MX8MQ 0x82
|
||||
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
|
||||
#define MXC_CPU_VF610 0xF6 /* dummy ID */
|
||||
|
||||
#define MXC_SOC_MX6 0x60
|
||||
#define MXC_SOC_MX7 0x70
|
||||
#define MXC_SOC_MX7ULP 0x80 /* dummy */
|
||||
#define MXC_SOC_MX8M 0x80
|
||||
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
|
||||
|
||||
#define CHIP_REV_1_0 0x10
|
||||
#define CHIP_REV_1_1 0x11
|
||||
|
|
|
@ -36,59 +36,59 @@ enum {
|
|||
MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
@ -97,51 +97,51 @@ enum {
|
|||
MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE),
|
||||
MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE),
|
||||
MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
|
||||
|
@ -197,309 +197,318 @@ enum {
|
|||
MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP),
|
||||
|
||||
MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x11, 0x528, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE),
|
||||
MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE),
|
||||
MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
/*
|
||||
* Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
|
||||
* card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
|
||||
* Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
|
||||
* bug that configuring the SD1_CMD function doesn't enable the input path for
|
||||
* this pin.
|
||||
* This might have side effects for other hardware units that are connected to
|
||||
* that pin and use the respective function as input.
|
||||
*/
|
||||
MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
|
||||
MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
|
||||
MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE),
|
||||
MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE),
|
||||
|
||||
MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP),
|
||||
MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP),
|
||||
|
||||
MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
|
||||
|
||||
MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP),
|
||||
MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP),
|
||||
|
||||
MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
|
||||
MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x11, 0x524, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL),
|
||||
MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
||||
MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
|
||||
MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
|
||||
|
|
|
@ -482,10 +482,11 @@ struct src {
|
|||
|
||||
#define src_base ((struct src *)SRC_BASE_ADDR)
|
||||
|
||||
#define SRC_SCR_M4_ENABLE_OFFSET 22
|
||||
#define SRC_SCR_M4_ENABLE_MASK (1 << 22)
|
||||
#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
|
||||
#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4)
|
||||
#define SRC_M4_REG_OFFSET 0
|
||||
#define SRC_M4_ENABLE_OFFSET 22
|
||||
#define SRC_M4_ENABLE_MASK BIT(22)
|
||||
#define SRC_M4C_NON_SCLR_RST_OFFSET 4
|
||||
#define SRC_M4C_NON_SCLR_RST_MASK BIT(4)
|
||||
|
||||
/* GPR1 bitfields */
|
||||
#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
|
||||
|
|
|
@ -264,10 +264,12 @@ struct src {
|
|||
u32 ddrc_rcr;
|
||||
};
|
||||
|
||||
#define SRC_M4RCR_M4C_NON_SCLR_RST_OFFSET 0
|
||||
#define SRC_M4RCR_M4C_NON_SCLR_RST_MASK (1 << 0)
|
||||
#define SRC_M4RCR_ENABLE_M4_OFFSET 3
|
||||
#define SRC_M4RCR_ENABLE_M4_MASK (1 << 3)
|
||||
#define SRC_M4_REG_OFFSET 0xC
|
||||
#define SRC_M4C_NON_SCLR_RST_OFFSET 0
|
||||
#define SRC_M4C_NON_SCLR_RST_MASK BIT(0)
|
||||
#define SRC_M4_ENABLE_OFFSET 3
|
||||
#define SRC_M4_ENABLE_MASK BIT(3)
|
||||
|
||||
#define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1
|
||||
#define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1)
|
||||
|
||||
|
@ -1208,14 +1210,6 @@ extern void pcie_power_off(void);
|
|||
readl(USBOTG2_IPS_BASE_ADDR + 0x158))
|
||||
#define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)
|
||||
|
||||
/* Boot device type */
|
||||
#define BOOT_TYPE_SD 0x1
|
||||
#define BOOT_TYPE_MMC 0x2
|
||||
#define BOOT_TYPE_NAND 0x3
|
||||
#define BOOT_TYPE_QSPI 0x4
|
||||
#define BOOT_TYPE_WEIM 0x5
|
||||
#define BOOT_TYPE_SPINOR 0x6
|
||||
|
||||
struct bootrom_sw_info {
|
||||
u8 reserved_1;
|
||||
u8 boot_dev_instance;
|
||||
|
|
657
arch/arm/include/asm/arch-mx8m/clock.h
Normal file
657
arch/arm/include/asm/arch-mx8m/clock.h
Normal file
|
@ -0,0 +1,657 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Peng Fan <peng.fan@nxp.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_IMX8M_CLOCK_H
|
||||
#define _ASM_ARCH_IMX8M_CLOCK_H
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
enum pll_clocks {
|
||||
ANATOP_ARM_PLL,
|
||||
ANATOP_GPU_PLL,
|
||||
ANATOP_SYSTEM_PLL1,
|
||||
ANATOP_SYSTEM_PLL2,
|
||||
ANATOP_SYSTEM_PLL3,
|
||||
ANATOP_AUDIO_PLL1,
|
||||
ANATOP_AUDIO_PLL2,
|
||||
ANATOP_VIDEO_PLL1,
|
||||
ANATOP_VIDEO_PLL2,
|
||||
ANATOP_DRAM_PLL,
|
||||
};
|
||||
|
||||
enum clk_slice_type {
|
||||
CORE_CLOCK_SLICE,
|
||||
BUS_CLOCK_SLICE,
|
||||
IP_CLOCK_SLICE,
|
||||
AHB_CLOCK_SLICE,
|
||||
IPG_CLOCK_SLICE,
|
||||
CORE_SEL_CLOCK_SLICE,
|
||||
DRAM_SEL_CLOCK_SLICE,
|
||||
};
|
||||
|
||||
enum clk_root_index {
|
||||
MXC_ARM_CLK = 0,
|
||||
ARM_A53_CLK_ROOT = 0,
|
||||
ARM_M4_CLK_ROOT = 1,
|
||||
VPU_A53_CLK_ROOT = 2,
|
||||
GPU_CORE_CLK_ROOT = 3,
|
||||
GPU_SHADER_CLK_ROOT = 4,
|
||||
MAIN_AXI_CLK_ROOT = 16,
|
||||
ENET_AXI_CLK_ROOT = 17,
|
||||
NAND_USDHC_BUS_CLK_ROOT = 18,
|
||||
VPU_BUS_CLK_ROOT = 19,
|
||||
DISPLAY_AXI_CLK_ROOT = 20,
|
||||
DISPLAY_APB_CLK_ROOT = 21,
|
||||
DISPLAY_RTRM_CLK_ROOT = 22,
|
||||
USB_BUS_CLK_ROOT = 23,
|
||||
GPU_AXI_CLK_ROOT = 24,
|
||||
GPU_AHB_CLK_ROOT = 25,
|
||||
NOC_CLK_ROOT = 26,
|
||||
NOC_APB_CLK_ROOT = 27,
|
||||
AHB_CLK_ROOT = 32,
|
||||
IPG_CLK_ROOT = 33,
|
||||
MXC_IPG_CLK = 33,
|
||||
AUDIO_AHB_CLK_ROOT = 34,
|
||||
MIPI_DSI_ESC_RX_CLK_ROOT = 36,
|
||||
DRAM_SEL_CFG = 48,
|
||||
CORE_SEL_CFG = 49,
|
||||
DRAM_ALT_CLK_ROOT = 64,
|
||||
DRAM_APB_CLK_ROOT = 65,
|
||||
VPU_G1_CLK_ROOT = 66,
|
||||
VPU_G2_CLK_ROOT = 67,
|
||||
DISPLAY_DTRC_CLK_ROOT = 68,
|
||||
DISPLAY_DC8000_CLK_ROOT = 69,
|
||||
PCIE1_CTRL_CLK_ROOT = 70,
|
||||
PCIE1_PHY_CLK_ROOT = 71,
|
||||
PCIE1_AUX_CLK_ROOT = 72,
|
||||
DC_PIXEL_CLK_ROOT = 73,
|
||||
LCDIF_PIXEL_CLK_ROOT = 74,
|
||||
SAI1_CLK_ROOT = 75,
|
||||
SAI2_CLK_ROOT = 76,
|
||||
SAI3_CLK_ROOT = 77,
|
||||
SAI4_CLK_ROOT = 78,
|
||||
SAI5_CLK_ROOT = 79,
|
||||
SAI6_CLK_ROOT = 80,
|
||||
SPDIF1_CLK_ROOT = 81,
|
||||
SPDIF2_CLK_ROOT = 82,
|
||||
ENET_REF_CLK_ROOT = 83,
|
||||
ENET_TIMER_CLK_ROOT = 84,
|
||||
ENET_PHY_REF_CLK_ROOT = 85,
|
||||
NAND_CLK_ROOT = 86,
|
||||
QSPI_CLK_ROOT = 87,
|
||||
MXC_ESDHC_CLK = 88,
|
||||
USDHC1_CLK_ROOT = 88,
|
||||
MXC_ESDHC2_CLK = 89,
|
||||
USDHC2_CLK_ROOT = 89,
|
||||
I2C1_CLK_ROOT = 90,
|
||||
MXC_I2C_CLK = 90,
|
||||
I2C2_CLK_ROOT = 91,
|
||||
I2C3_CLK_ROOT = 92,
|
||||
I2C4_CLK_ROOT = 93,
|
||||
UART1_CLK_ROOT = 94,
|
||||
UART2_CLK_ROOT = 95,
|
||||
UART3_CLK_ROOT = 96,
|
||||
UART4_CLK_ROOT = 97,
|
||||
USB_CORE_REF_CLK_ROOT = 98,
|
||||
USB_PHY_REF_CLK_ROOT = 99,
|
||||
GIC_CLK_ROOT = 100,
|
||||
ECSPI1_CLK_ROOT = 101,
|
||||
ECSPI2_CLK_ROOT = 102,
|
||||
PWM1_CLK_ROOT = 103,
|
||||
PWM2_CLK_ROOT = 104,
|
||||
PWM3_CLK_ROOT = 105,
|
||||
PWM4_CLK_ROOT = 106,
|
||||
GPT1_CLK_ROOT = 107,
|
||||
GPT2_CLK_ROOT = 108,
|
||||
GPT3_CLK_ROOT = 109,
|
||||
GPT4_CLK_ROOT = 110,
|
||||
GPT5_CLK_ROOT = 111,
|
||||
GPT6_CLK_ROOT = 112,
|
||||
TRACE_CLK_ROOT = 113,
|
||||
WDOG_CLK_ROOT = 114,
|
||||
WRCLK_CLK_ROOT = 115,
|
||||
IPP_DO_CLKO1 = 116,
|
||||
IPP_DO_CLKO2 = 117,
|
||||
MIPI_DSI_CORE_CLK_ROOT = 118,
|
||||
MIPI_DSI_PHY_REF_CLK_ROOT = 119,
|
||||
MIPI_DSI_DBI_CLK_ROOT = 120,
|
||||
OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
|
||||
MIPI_CSI1_CORE_CLK_ROOT = 122,
|
||||
MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
|
||||
MIPI_CSI1_ESC_CLK_ROOT = 124,
|
||||
MIPI_CSI2_CORE_CLK_ROOT = 125,
|
||||
MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
|
||||
MIPI_CSI2_ESC_CLK_ROOT = 127,
|
||||
PCIE2_CTRL_CLK_ROOT = 128,
|
||||
PCIE2_PHY_CLK_ROOT = 129,
|
||||
PCIE2_AUX_CLK_ROOT = 130,
|
||||
ECSPI3_CLK_ROOT = 131,
|
||||
OLD_MIPI_DSI_ESC_RX_ROOT = 132,
|
||||
DISPLAY_HDMI_CLK_ROOT = 133,
|
||||
CLK_ROOT_MAX,
|
||||
};
|
||||
|
||||
enum clk_root_src {
|
||||
OSC_25M_CLK,
|
||||
ARM_PLL_CLK,
|
||||
DRAM_PLL1_CLK,
|
||||
VIDEO_PLL2_CLK,
|
||||
VPU_PLL_CLK,
|
||||
GPU_PLL_CLK,
|
||||
SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_266M_CLK,
|
||||
SYSTEM_PLL1_200M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL1_133M_CLK,
|
||||
SYSTEM_PLL1_100M_CLK,
|
||||
SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK,
|
||||
SYSTEM_PLL2_333M_CLK,
|
||||
SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_166M_CLK,
|
||||
SYSTEM_PLL2_125M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK,
|
||||
AUDIO_PLL1_CLK,
|
||||
AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK,
|
||||
OSC_32K_CLK,
|
||||
EXT_CLK_1,
|
||||
EXT_CLK_2,
|
||||
EXT_CLK_3,
|
||||
EXT_CLK_4,
|
||||
OSC_27M_CLK,
|
||||
};
|
||||
|
||||
/* CCGR index */
|
||||
enum clk_ccgr_index {
|
||||
CCGR_DVFS = 0,
|
||||
CCGR_ANAMIX = 1,
|
||||
CCGR_CPU = 2,
|
||||
CCGR_CSU = 4,
|
||||
CCGR_DRAM1 = 5,
|
||||
CCGR_DRAM2_OBSOLETE = 6,
|
||||
CCGR_ECSPI1 = 7,
|
||||
CCGR_ECSPI2 = 8,
|
||||
CCGR_ECSPI3 = 9,
|
||||
CCGR_ENET1 = 10,
|
||||
CCGR_GPIO1 = 11,
|
||||
CCGR_GPIO2 = 12,
|
||||
CCGR_GPIO3 = 13,
|
||||
CCGR_GPIO4 = 14,
|
||||
CCGR_GPIO5 = 15,
|
||||
CCGR_GPT1 = 16,
|
||||
CCGR_GPT2 = 17,
|
||||
CCGR_GPT3 = 18,
|
||||
CCGR_GPT4 = 19,
|
||||
CCGR_GPT5 = 20,
|
||||
CCGR_GPT6 = 21,
|
||||
CCGR_HS = 22,
|
||||
CCGR_I2C1 = 23,
|
||||
CCGR_I2C2 = 24,
|
||||
CCGR_I2C3 = 25,
|
||||
CCGR_I2C4 = 26,
|
||||
CCGR_IOMUX = 27,
|
||||
CCGR_IOMUX1 = 28,
|
||||
CCGR_IOMUX2 = 29,
|
||||
CCGR_IOMUX3 = 30,
|
||||
CCGR_IOMUX4 = 31,
|
||||
CCGR_M4 = 32,
|
||||
CCGR_MU = 33,
|
||||
CCGR_OCOTP = 34,
|
||||
CCGR_OCRAM = 35,
|
||||
CCGR_OCRAM_S = 36,
|
||||
CCGR_PCIE = 37,
|
||||
CCGR_PERFMON1 = 38,
|
||||
CCGR_PERFMON2 = 39,
|
||||
CCGR_PWM1 = 40,
|
||||
CCGR_PWM2 = 41,
|
||||
CCGR_PWM3 = 42,
|
||||
CCGR_PWM4 = 43,
|
||||
CCGR_QOS = 44,
|
||||
CCGR_DISMIX = 45,
|
||||
CCGR_MEGAMIX = 46,
|
||||
CCGR_QSPI = 47,
|
||||
CCGR_RAWNAND = 48,
|
||||
CCGR_RDC = 49,
|
||||
CCGR_ROM = 50,
|
||||
CCGR_SAI1 = 51,
|
||||
CCGR_SAI2 = 52,
|
||||
CCGR_SAI3 = 53,
|
||||
CCGR_SAI4 = 54,
|
||||
CCGR_SAI5 = 55,
|
||||
CCGR_SAI6 = 56,
|
||||
CCGR_SCTR = 57,
|
||||
CCGR_SDMA1 = 58,
|
||||
CCGR_SDMA2 = 59,
|
||||
CCGR_SEC_DEBUG = 60,
|
||||
CCGR_SEMA1 = 61,
|
||||
CCGR_SEMA2 = 62,
|
||||
CCGR_SIM_DISPLAY = 63,
|
||||
CCGR_SIM_ENET = 64,
|
||||
CCGR_SIM_M = 65,
|
||||
CCGR_SIM_MAIN = 66,
|
||||
CCGR_SIM_S = 67,
|
||||
CCGR_SIM_WAKEUP = 68,
|
||||
CCGR_SIM_USB = 69,
|
||||
CCGR_SIM_VPU = 70,
|
||||
CCGR_SNVS = 71,
|
||||
CCGR_TRACE = 72,
|
||||
CCGR_UART1 = 73,
|
||||
CCGR_UART2 = 74,
|
||||
CCGR_UART3 = 75,
|
||||
CCGR_UART4 = 76,
|
||||
CCGR_USB_CTRL1 = 77,
|
||||
CCGR_USB_CTRL2 = 78,
|
||||
CCGR_USB_PHY1 = 79,
|
||||
CCGR_USB_PHY2 = 80,
|
||||
CCGR_USDHC1 = 81,
|
||||
CCGR_USDHC2 = 82,
|
||||
CCGR_WDOG1 = 83,
|
||||
CCGR_WDOG2 = 84,
|
||||
CCGR_WDOG3 = 85,
|
||||
CCGR_VA53 = 86,
|
||||
CCGR_GPU = 87,
|
||||
CCGR_HEVC = 88,
|
||||
CCGR_AVC = 89,
|
||||
CCGR_VP9 = 90,
|
||||
CCGR_HEVC_INTER = 91,
|
||||
CCGR_GIC = 92,
|
||||
CCGR_DISPLAY = 93,
|
||||
CCGR_HDMI = 94,
|
||||
CCGR_HDMI_PHY = 95,
|
||||
CCGR_XTAL = 96,
|
||||
CCGR_PLL = 97,
|
||||
CCGR_TSENSOR = 98,
|
||||
CCGR_VPU_DEC = 99,
|
||||
CCGR_PCIE2 = 100,
|
||||
CCGR_MIPI_CSI1 = 101,
|
||||
CCGR_MIPI_CSI2 = 102,
|
||||
CCGR_MAX,
|
||||
};
|
||||
|
||||
/* src index */
|
||||
enum clk_src_index {
|
||||
CLK_SRC_CKIL_SYNC_REQ = 0,
|
||||
CLK_SRC_ARM_PLL_EN = 1,
|
||||
CLK_SRC_GPU_PLL_EN = 2,
|
||||
CLK_SRC_VPU_PLL_EN = 3,
|
||||
CLK_SRC_DRAM_PLL_EN = 4,
|
||||
CLK_SRC_SYSTEM_PLL1_EN = 5,
|
||||
CLK_SRC_SYSTEM_PLL2_EN = 6,
|
||||
CLK_SRC_SYSTEM_PLL3_EN = 7,
|
||||
CLK_SRC_AUDIO_PLL1_EN = 8,
|
||||
CLK_SRC_AUDIO_PLL2_EN = 9,
|
||||
CLK_SRC_VIDEO_PLL1_EN = 10,
|
||||
CLK_SRC_VIDEO_PLL2_EN = 11,
|
||||
CLK_SRC_ARM_PLL = 12,
|
||||
CLK_SRC_GPU_PLL = 13,
|
||||
CLK_SRC_VPU_PLL = 14,
|
||||
CLK_SRC_DRAM_PLL = 15,
|
||||
CLK_SRC_SYSTEM_PLL1_800M = 16,
|
||||
CLK_SRC_SYSTEM_PLL1_400M = 17,
|
||||
CLK_SRC_SYSTEM_PLL1_266M = 18,
|
||||
CLK_SRC_SYSTEM_PLL1_200M = 19,
|
||||
CLK_SRC_SYSTEM_PLL1_160M = 20,
|
||||
CLK_SRC_SYSTEM_PLL1_133M = 21,
|
||||
CLK_SRC_SYSTEM_PLL1_100M = 22,
|
||||
CLK_SRC_SYSTEM_PLL1_80M = 23,
|
||||
CLK_SRC_SYSTEM_PLL1_40M = 24,
|
||||
CLK_SRC_SYSTEM_PLL2_1000M = 25,
|
||||
CLK_SRC_SYSTEM_PLL2_500M = 26,
|
||||
CLK_SRC_SYSTEM_PLL2_333M = 27,
|
||||
CLK_SRC_SYSTEM_PLL2_250M = 28,
|
||||
CLK_SRC_SYSTEM_PLL2_200M = 29,
|
||||
CLK_SRC_SYSTEM_PLL2_166M = 30,
|
||||
CLK_SRC_SYSTEM_PLL2_125M = 31,
|
||||
CLK_SRC_SYSTEM_PLL2_100M = 32,
|
||||
CLK_SRC_SYSTEM_PLL2_50M = 33,
|
||||
CLK_SRC_SYSTEM_PLL3 = 34,
|
||||
CLK_SRC_AUDIO_PLL1 = 35,
|
||||
CLK_SRC_AUDIO_PLL2 = 36,
|
||||
CLK_SRC_VIDEO_PLL1 = 37,
|
||||
CLK_SRC_VIDEO_PLL2 = 38,
|
||||
CLK_SRC_OSC_25M = 39,
|
||||
CLK_SRC_OSC_27M = 40,
|
||||
};
|
||||
|
||||
enum root_pre_div {
|
||||
CLK_ROOT_PRE_DIV1 = 0,
|
||||
CLK_ROOT_PRE_DIV2,
|
||||
CLK_ROOT_PRE_DIV3,
|
||||
CLK_ROOT_PRE_DIV4,
|
||||
CLK_ROOT_PRE_DIV5,
|
||||
CLK_ROOT_PRE_DIV6,
|
||||
CLK_ROOT_PRE_DIV7,
|
||||
CLK_ROOT_PRE_DIV8,
|
||||
};
|
||||
|
||||
enum root_post_div {
|
||||
CLK_ROOT_POST_DIV1 = 0,
|
||||
CLK_ROOT_POST_DIV2,
|
||||
CLK_ROOT_POST_DIV3,
|
||||
CLK_ROOT_POST_DIV4,
|
||||
CLK_ROOT_POST_DIV5,
|
||||
CLK_ROOT_POST_DIV6,
|
||||
CLK_ROOT_POST_DIV7,
|
||||
CLK_ROOT_POST_DIV8,
|
||||
CLK_ROOT_POST_DIV9,
|
||||
CLK_ROOT_POST_DIV10,
|
||||
CLK_ROOT_POST_DIV11,
|
||||
CLK_ROOT_POST_DIV12,
|
||||
CLK_ROOT_POST_DIV13,
|
||||
CLK_ROOT_POST_DIV14,
|
||||
CLK_ROOT_POST_DIV15,
|
||||
CLK_ROOT_POST_DIV16,
|
||||
CLK_ROOT_POST_DIV17,
|
||||
CLK_ROOT_POST_DIV18,
|
||||
CLK_ROOT_POST_DIV19,
|
||||
CLK_ROOT_POST_DIV20,
|
||||
CLK_ROOT_POST_DIV21,
|
||||
CLK_ROOT_POST_DIV22,
|
||||
CLK_ROOT_POST_DIV23,
|
||||
CLK_ROOT_POST_DIV24,
|
||||
CLK_ROOT_POST_DIV25,
|
||||
CLK_ROOT_POST_DIV26,
|
||||
CLK_ROOT_POST_DIV27,
|
||||
CLK_ROOT_POST_DIV28,
|
||||
CLK_ROOT_POST_DIV29,
|
||||
CLK_ROOT_POST_DIV30,
|
||||
CLK_ROOT_POST_DIV31,
|
||||
CLK_ROOT_POST_DIV32,
|
||||
CLK_ROOT_POST_DIV33,
|
||||
CLK_ROOT_POST_DIV34,
|
||||
CLK_ROOT_POST_DIV35,
|
||||
CLK_ROOT_POST_DIV36,
|
||||
CLK_ROOT_POST_DIV37,
|
||||
CLK_ROOT_POST_DIV38,
|
||||
CLK_ROOT_POST_DIV39,
|
||||
CLK_ROOT_POST_DIV40,
|
||||
CLK_ROOT_POST_DIV41,
|
||||
CLK_ROOT_POST_DIV42,
|
||||
CLK_ROOT_POST_DIV43,
|
||||
CLK_ROOT_POST_DIV44,
|
||||
CLK_ROOT_POST_DIV45,
|
||||
CLK_ROOT_POST_DIV46,
|
||||
CLK_ROOT_POST_DIV47,
|
||||
CLK_ROOT_POST_DIV48,
|
||||
CLK_ROOT_POST_DIV49,
|
||||
CLK_ROOT_POST_DIV50,
|
||||
CLK_ROOT_POST_DIV51,
|
||||
CLK_ROOT_POST_DIV52,
|
||||
CLK_ROOT_POST_DIV53,
|
||||
CLK_ROOT_POST_DIV54,
|
||||
CLK_ROOT_POST_DIV55,
|
||||
CLK_ROOT_POST_DIV56,
|
||||
CLK_ROOT_POST_DIV57,
|
||||
CLK_ROOT_POST_DIV58,
|
||||
CLK_ROOT_POST_DIV59,
|
||||
CLK_ROOT_POST_DIV60,
|
||||
CLK_ROOT_POST_DIV61,
|
||||
CLK_ROOT_POST_DIV62,
|
||||
CLK_ROOT_POST_DIV63,
|
||||
CLK_ROOT_POST_DIV64,
|
||||
};
|
||||
|
||||
struct clk_root_map {
|
||||
enum clk_root_index entry;
|
||||
enum clk_slice_type slice_type;
|
||||
u32 slice_index;
|
||||
u8 src_mux[8];
|
||||
};
|
||||
|
||||
struct ccm_ccgr {
|
||||
u32 ccgr;
|
||||
u32 ccgr_set;
|
||||
u32 ccgr_clr;
|
||||
u32 ccgr_tog;
|
||||
};
|
||||
|
||||
struct ccm_root {
|
||||
u32 target_root;
|
||||
u32 target_root_set;
|
||||
u32 target_root_clr;
|
||||
u32 target_root_tog;
|
||||
u32 misc;
|
||||
u32 misc_set;
|
||||
u32 misc_clr;
|
||||
u32 misc_tog;
|
||||
u32 nm_post;
|
||||
u32 nm_post_root_set;
|
||||
u32 nm_post_root_clr;
|
||||
u32 nm_post_root_tog;
|
||||
u32 nm_pre;
|
||||
u32 nm_pre_root_set;
|
||||
u32 nm_pre_root_clr;
|
||||
u32 nm_pre_root_tog;
|
||||
u32 db_post;
|
||||
u32 db_post_root_set;
|
||||
u32 db_post_root_clr;
|
||||
u32 db_post_root_tog;
|
||||
u32 db_pre;
|
||||
u32 db_pre_root_set;
|
||||
u32 db_pre_root_clr;
|
||||
u32 db_pre_root_tog;
|
||||
u32 reserved[4];
|
||||
u32 access_ctrl;
|
||||
u32 access_ctrl_root_set;
|
||||
u32 access_ctrl_root_clr;
|
||||
u32 access_ctrl_root_tog;
|
||||
};
|
||||
|
||||
struct ccm_reg {
|
||||
u32 reserved_0[4096];
|
||||
struct ccm_ccgr ccgr_array[192];
|
||||
u32 reserved_1[3328];
|
||||
struct ccm_root core_root[5];
|
||||
u32 reserved_2[352];
|
||||
struct ccm_root bus_root[12];
|
||||
u32 reserved_3[128];
|
||||
struct ccm_root ahb_ipg_root[4];
|
||||
u32 reserved_4[384];
|
||||
struct ccm_root dram_sel;
|
||||
struct ccm_root core_sel;
|
||||
u32 reserved_5[448];
|
||||
struct ccm_root ip_root[78];
|
||||
};
|
||||
|
||||
#define CCGR_CLK_ON_MASK 0x03
|
||||
#define CLK_SRC_ON_MASK 0x03
|
||||
|
||||
#define CLK_ROOT_ON BIT(28)
|
||||
#define CLK_ROOT_OFF (0 << 28)
|
||||
#define CLK_ROOT_ENABLE_MASK BIT(28)
|
||||
#define CLK_ROOT_ENABLE_SHIFT 28
|
||||
#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
|
||||
|
||||
/* For SEL, only use 1 bit */
|
||||
#define CLK_ROOT_SRC_MUX_MASK 0x07000000
|
||||
#define CLK_ROOT_SRC_MUX_SHIFT 24
|
||||
#define CLK_ROOT_SRC_0 0x00000000
|
||||
#define CLK_ROOT_SRC_1 0x01000000
|
||||
#define CLK_ROOT_SRC_2 0x02000000
|
||||
#define CLK_ROOT_SRC_3 0x03000000
|
||||
#define CLK_ROOT_SRC_4 0x04000000
|
||||
#define CLK_ROOT_SRC_5 0x05000000
|
||||
#define CLK_ROOT_SRC_6 0x06000000
|
||||
#define CLK_ROOT_SRC_7 0x07000000
|
||||
|
||||
#define CLK_ROOT_PRE_DIV_MASK (0x00070000)
|
||||
#define CLK_ROOT_PRE_DIV_SHIFT 16
|
||||
#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)
|
||||
|
||||
#define CLK_ROOT_AUDO_SLOW_EN 0x1000
|
||||
|
||||
#define CLK_ROOT_AUDO_DIV_MASK 0x700
|
||||
#define CLK_ROOT_AUDO_DIV_SHIFT 0x8
|
||||
#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)
|
||||
|
||||
/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
|
||||
#define CLK_ROOT_POST_DIV_MASK 0x3f
|
||||
#define CLK_ROOT_CORE_POST_DIV_MASK 0x7
|
||||
#define CLK_ROOT_IPG_POST_DIV_MASK 0x3
|
||||
#define CLK_ROOT_POST_DIV_SHIFT 0
|
||||
#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
|
||||
|
||||
/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
|
||||
#define FRAC_PLL_LOCK_MASK BIT(31)
|
||||
#define FRAC_PLL_CLKE_MASK BIT(21)
|
||||
#define FRAC_PLL_PD_MASK BIT(19)
|
||||
#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
|
||||
#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
|
||||
#define FRAC_PLL_BYPASS_MASK BIT(14)
|
||||
#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
|
||||
#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
|
||||
#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
|
||||
#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
|
||||
#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
|
||||
#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
|
||||
#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
|
||||
#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
|
||||
|
||||
#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
|
||||
#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
|
||||
#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
|
||||
#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
|
||||
|
||||
#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
|
||||
#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
|
||||
#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
|
||||
#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
|
||||
|
||||
/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
|
||||
#define SSCG_PLL_LOCK_MASK BIT(31)
|
||||
#define SSCG_PLL_CLKE_MASK BIT(25)
|
||||
#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
|
||||
#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
|
||||
#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
|
||||
#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
|
||||
#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
|
||||
#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
|
||||
#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
|
||||
#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
|
||||
#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
|
||||
#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
|
||||
#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
|
||||
#define SSCG_PLL_PD_MASK BIT(7)
|
||||
#define SSCG_PLL_BYPASS1_MASK BIT(5)
|
||||
#define SSCG_PLL_BYPASS2_MASK BIT(4)
|
||||
#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
|
||||
#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
|
||||
#define SSCG_PLL_REFCLK_SEL_MASK 0x3
|
||||
#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
|
||||
#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
|
||||
#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
|
||||
#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
|
||||
|
||||
#define SSCG_PLL_SSDS_MASK BIT(8)
|
||||
#define SSCG_PLL_SSMD_MASK (0x7 << 5)
|
||||
#define SSCG_PLL_SSMF_MASK (0xf << 1)
|
||||
#define SSCG_PLL_SSE_MASK 0x1
|
||||
|
||||
#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
|
||||
#define SSCG_PLL_REF_DIVR1_SHIFT 25
|
||||
#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
|
||||
#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
|
||||
#define SSCG_PLL_REF_DIVR2_SHIFT 19
|
||||
#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
|
||||
SSCG_PLL_FEEDBACK_DIV_F1_MASK)
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
|
||||
SSCG_PLL_FEEDBACK_DIV_F2_MASK)
|
||||
#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
|
||||
#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
|
||||
#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
|
||||
SSCG_PLL_OUTPUT_DIV_VAL_MASK)
|
||||
#define SSCG_PLL_FILTER_RANGE_MASK 0x1
|
||||
|
||||
#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
|
||||
#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
|
||||
#define HW_DIGPROG_MINOR_MASK 0xff
|
||||
|
||||
#define HW_OSC_27M_CLKE_MASK BIT(4)
|
||||
#define HW_OSC_25M_CLKE_MASK BIT(2)
|
||||
#define HW_OSC_32K_SEL_MASK 0x1
|
||||
#define HW_OSC_32K_SEL_RTC 0x1
|
||||
#define HW_OSC_32K_SEL_25M_DIV800 0x0
|
||||
|
||||
#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
|
||||
#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
|
||||
#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
|
||||
#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
|
||||
#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
|
||||
#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
|
||||
#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
|
||||
#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
|
||||
#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
|
||||
#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
|
||||
#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
|
||||
#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
|
||||
|
||||
#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
|
||||
#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
|
||||
#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
|
||||
#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
|
||||
#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
|
||||
#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
|
||||
#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
|
||||
#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
|
||||
#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
|
||||
#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
|
||||
|
||||
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
|
||||
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
|
||||
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
|
||||
#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
|
||||
#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000
|
||||
#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
|
||||
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
|
||||
|
||||
enum enet_freq {
|
||||
ENET_25MHZ = 0,
|
||||
ENET_50MHZ,
|
||||
ENET_125MHZ,
|
||||
};
|
||||
|
||||
enum frac_pll_out_val {
|
||||
FRAC_PLL_OUT_1000M,
|
||||
FRAC_PLL_OUT_1600M,
|
||||
};
|
||||
|
||||
u32 imx_get_fecclk(void);
|
||||
u32 imx_get_uartclk(void);
|
||||
int clock_init(void);
|
||||
void init_clk_usdhc(u32 index);
|
||||
void init_uart_clk(u32 index);
|
||||
void init_wdog_clk(void);
|
||||
unsigned int mxc_get_clock(enum clk_root_index clk);
|
||||
int clock_enable(enum clk_ccgr_index index, bool enable);
|
||||
int clock_root_enabled(enum clk_root_index clock_id);
|
||||
int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
|
||||
enum root_post_div post_div, enum clk_root_src clock_src);
|
||||
int clock_set_target_val(enum clk_root_index clock_id, u32 val);
|
||||
int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
|
||||
int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
|
||||
int clock_get_postdiv(enum clk_root_index clock_id,
|
||||
enum root_post_div *post_div);
|
||||
int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
|
||||
void mxs_set_lcdclk(u32 base_addr, u32 freq);
|
||||
int set_clk_qspi(void);
|
||||
void enable_ocotp_clk(unsigned char enable);
|
||||
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
|
||||
int set_clk_enet(enum enet_freq type);
|
||||
#endif
|
10
arch/arm/include/asm/arch-mx8m/crm_regs.h
Normal file
10
arch/arm/include/asm/arch-mx8m/crm_regs.h
Normal file
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
|
||||
#define _ASM_ARCH_MX8M_CRM_REGS_H
|
||||
/* Dummy header, some imx-common code needs this file */
|
||||
#endif
|
356
arch/arm/include/asm/arch-mx8m/ddr.h
Normal file
356
arch/arm/include/asm/arch-mx8m/ddr.h
Normal file
|
@ -0,0 +1,356 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MX8M_DDR_H
|
||||
#define __ASM_ARCH_MX8M_DDR_H
|
||||
|
||||
#define DDRC_DDR_SS_GPR0 0x3d000000
|
||||
#define DDRC_IPS_BASE_ADDR_0 0x3f400000
|
||||
#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
|
||||
#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
|
||||
|
||||
struct ddrc_freq {
|
||||
u32 res0[8];
|
||||
u32 derateen;
|
||||
u32 derateint;
|
||||
u32 res1[10];
|
||||
u32 rfshctl0;
|
||||
u32 res2[4];
|
||||
u32 rfshtmg;
|
||||
u32 rfshtmg1;
|
||||
u32 res3[28];
|
||||
u32 init3;
|
||||
u32 init4;
|
||||
u32 res;
|
||||
u32 init6;
|
||||
u32 init7;
|
||||
u32 res4[4];
|
||||
u32 dramtmg0;
|
||||
u32 dramtmg1;
|
||||
u32 dramtmg2;
|
||||
u32 dramtmg3;
|
||||
u32 dramtmg4;
|
||||
u32 dramtmg5;
|
||||
u32 dramtmg6;
|
||||
u32 dramtmg7;
|
||||
u32 dramtmg8;
|
||||
u32 dramtmg9;
|
||||
u32 dramtmg10;
|
||||
u32 dramtmg11;
|
||||
u32 dramtmg12;
|
||||
u32 dramtmg13;
|
||||
u32 dramtmg14;
|
||||
u32 dramtmg15;
|
||||
u32 dramtmg16;
|
||||
u32 dramtmg17;
|
||||
u32 res5[10];
|
||||
u32 mramtmg0;
|
||||
u32 mramtmg1;
|
||||
u32 mramtmg4;
|
||||
u32 mramtmg9;
|
||||
u32 zqctl0;
|
||||
u32 res6[3];
|
||||
u32 dfitmg0;
|
||||
u32 dfitmg1;
|
||||
u32 res7[7];
|
||||
u32 dfitmg2;
|
||||
u32 dfitmg3;
|
||||
u32 res8[33];
|
||||
u32 odtcfg;
|
||||
};
|
||||
|
||||
struct imx8m_ddrc_regs {
|
||||
u32 mstr;
|
||||
u32 stat;
|
||||
u32 mstr1;
|
||||
u32 res1;
|
||||
u32 mrctrl0;
|
||||
u32 mrctrl1;
|
||||
u32 mrstat;
|
||||
u32 mrctrl2;
|
||||
u32 derateen;
|
||||
u32 derateint;
|
||||
u32 mstr2;
|
||||
u32 res2;
|
||||
u32 pwrctl;
|
||||
u32 pwrtmg;
|
||||
u32 hwlpctl;
|
||||
u32 hwffcctl;
|
||||
u32 hwffcstat;
|
||||
u32 res3[3];
|
||||
u32 rfshctl0;
|
||||
u32 rfshctl1;
|
||||
u32 rfshctl2;
|
||||
u32 rfshctl4;
|
||||
u32 rfshctl3;
|
||||
u32 rfshtmg;
|
||||
u32 rfshtmg1;
|
||||
u32 res4;
|
||||
u32 ecccfg0;
|
||||
u32 ecccfg1;
|
||||
u32 eccstat;
|
||||
u32 eccclr;
|
||||
u32 eccerrcnt;
|
||||
u32 ecccaddr0;
|
||||
u32 ecccaddr1;
|
||||
u32 ecccsyn0;
|
||||
u32 ecccsyn1;
|
||||
u32 ecccsyn2;
|
||||
u32 eccbitmask0;
|
||||
u32 eccbitmask1;
|
||||
u32 eccbitmask2;
|
||||
u32 eccuaddr0;
|
||||
u32 eccuaddr1;
|
||||
u32 eccusyn0;
|
||||
u32 eccusyn1;
|
||||
u32 eccusyn2;
|
||||
u32 eccpoisonaddr0;
|
||||
u32 eccpoisonaddr1;
|
||||
u32 crcparctl0;
|
||||
u32 crcparctl1;
|
||||
u32 crcparctl2;
|
||||
u32 crcparstat;
|
||||
u32 init0;
|
||||
u32 init1;
|
||||
u32 init2;
|
||||
u32 init3;
|
||||
u32 init4;
|
||||
u32 init5;
|
||||
u32 init6;
|
||||
u32 init7;
|
||||
u32 dimmctl;
|
||||
u32 rankctl;
|
||||
u32 res5;
|
||||
u32 chctl;
|
||||
u32 dramtmg0;
|
||||
u32 dramtmg1;
|
||||
u32 dramtmg2;
|
||||
u32 dramtmg3;
|
||||
u32 dramtmg4;
|
||||
u32 dramtmg5;
|
||||
u32 dramtmg6;
|
||||
u32 dramtmg7;
|
||||
u32 dramtmg8;
|
||||
u32 dramtmg9;
|
||||
u32 dramtmg10;
|
||||
u32 dramtmg11;
|
||||
u32 dramtmg12;
|
||||
u32 dramtmg13;
|
||||
u32 dramtmg14;
|
||||
u32 dramtmg15;
|
||||
u32 dramtmg16;
|
||||
u32 dramtmg17;
|
||||
u32 res6[10];
|
||||
u32 mramtmg0;
|
||||
u32 mramtmg1;
|
||||
u32 mramtmg4;
|
||||
u32 mramtmg9;
|
||||
u32 zqctl0;
|
||||
u32 zqctl1;
|
||||
u32 zqctl2;
|
||||
u32 zqstat;
|
||||
u32 dfitmg0;
|
||||
u32 dfitmg1;
|
||||
u32 dfilpcfg0;
|
||||
u32 dfilpcfg1;
|
||||
u32 dfiupd0;
|
||||
u32 dfiupd1;
|
||||
u32 dfiupd2;
|
||||
u32 res7;
|
||||
u32 dfimisc;
|
||||
u32 dfitmg2;
|
||||
u32 dfitmg3;
|
||||
u32 dfistat;
|
||||
u32 dbictl;
|
||||
u32 dfiphymstr;
|
||||
u32 res8[14];
|
||||
u32 addrmap0;
|
||||
u32 addrmap1;
|
||||
u32 addrmap2;
|
||||
u32 addrmap3;
|
||||
u32 addrmap4;
|
||||
u32 addrmap5;
|
||||
u32 addrmap6;
|
||||
u32 addrmap7;
|
||||
u32 addrmap8;
|
||||
u32 addrmap9;
|
||||
u32 addrmap10;
|
||||
u32 addrmap11;
|
||||
u32 res9[4];
|
||||
u32 odtcfg;
|
||||
u32 odtmap;
|
||||
u32 res10[2];
|
||||
u32 sched;
|
||||
u32 sched1;
|
||||
u32 sched2;
|
||||
u32 perfhpr1;
|
||||
u32 res11;
|
||||
u32 perflpr1;
|
||||
u32 res12;
|
||||
u32 perfwr1;
|
||||
u32 res13[4];
|
||||
u32 dqmap0;
|
||||
u32 dqmap1;
|
||||
u32 dqmap2;
|
||||
u32 dqmap3;
|
||||
u32 dqmap4;
|
||||
u32 dqmap5;
|
||||
u32 res14[26];
|
||||
u32 dbg0;
|
||||
u32 dbg1;
|
||||
u32 dbgcam;
|
||||
u32 dbgcmd;
|
||||
u32 dbgstat;
|
||||
u32 res15[3];
|
||||
u32 swctl;
|
||||
u32 swstat;
|
||||
u32 res16[2];
|
||||
u32 ocparcfg0;
|
||||
u32 ocparcfg1;
|
||||
u32 ocparcfg2;
|
||||
u32 ocparcfg3;
|
||||
u32 ocparstat0;
|
||||
u32 ocparstat1;
|
||||
u32 ocparwlog0;
|
||||
u32 ocparwlog1;
|
||||
u32 ocparwlog2;
|
||||
u32 ocparawlog0;
|
||||
u32 ocparawlog1;
|
||||
u32 ocparrlog0;
|
||||
u32 ocparrlog1;
|
||||
u32 ocpararlog0;
|
||||
u32 ocpararlog1;
|
||||
u32 poisoncfg;
|
||||
u32 poisonstat;
|
||||
u32 adveccindex;
|
||||
union {
|
||||
u32 adveccstat;
|
||||
u32 eccapstat;
|
||||
};
|
||||
u32 eccpoisonpat0;
|
||||
u32 eccpoisonpat1;
|
||||
u32 eccpoisonpat2;
|
||||
u32 res17[6];
|
||||
u32 caparpoisonctl;
|
||||
u32 caparpoisonstat;
|
||||
u32 res18[2];
|
||||
u32 dynbsmstat;
|
||||
u32 res19[18];
|
||||
u32 pstat;
|
||||
u32 pccfg;
|
||||
struct {
|
||||
u32 pcfgr;
|
||||
u32 pcfgw;
|
||||
u32 pcfgc;
|
||||
struct {
|
||||
u32 pcfgidmaskch0;
|
||||
u32 pcfidvaluech0;
|
||||
} pcfgid[16];
|
||||
u32 pctrl;
|
||||
u32 pcfgqos0;
|
||||
u32 pcfgqos1;
|
||||
u32 pcfgwqos0;
|
||||
u32 pcfgwqos1;
|
||||
u32 res[4];
|
||||
} pcfg[16];
|
||||
struct {
|
||||
u32 sarbase;
|
||||
u32 sarsize;
|
||||
} sar[4];
|
||||
u32 sbrctl;
|
||||
u32 sbrstat;
|
||||
u32 sbrwdata0;
|
||||
u32 sbrwdata1;
|
||||
u32 pdch;
|
||||
u32 res20[755];
|
||||
/* umctl2_regs_dch1 */
|
||||
u32 ch1_stat;
|
||||
u32 res21[2];
|
||||
u32 ch1_mrctrl0;
|
||||
u32 ch1_mrctrl1;
|
||||
u32 ch1_mrstat;
|
||||
u32 ch1_mrctrl2;
|
||||
u32 res22[4];
|
||||
u32 ch1_pwrctl;
|
||||
u32 ch1_pwrtmg;
|
||||
u32 ch1_hwlpctl;
|
||||
u32 res23[15];
|
||||
u32 ch1_eccstat;
|
||||
u32 ch1_eccclr;
|
||||
u32 ch1_eccerrcnt;
|
||||
u32 ch1_ecccaddr0;
|
||||
u32 ch1_ecccaddr1;
|
||||
u32 ch1_ecccsyn0;
|
||||
u32 ch1_ecccsyn1;
|
||||
u32 ch1_ecccsyn2;
|
||||
u32 ch1_eccbitmask0;
|
||||
u32 ch1_eccbitmask1;
|
||||
u32 ch1_eccbitmask2;
|
||||
u32 ch1_eccuaddr0;
|
||||
u32 ch1_eccuaddr1;
|
||||
u32 ch1_eccusyn0;
|
||||
u32 ch1_eccusyn1;
|
||||
u32 ch1_eccusyn2;
|
||||
u32 res24[2];
|
||||
u32 ch1_crcparctl0;
|
||||
u32 res25[2];
|
||||
u32 ch1_crcparstat;
|
||||
u32 res26[46];
|
||||
u32 ch1_zqctl2;
|
||||
u32 ch1_zqstat;
|
||||
u32 res27[11];
|
||||
u32 ch1_dfistat;
|
||||
u32 res28[33];
|
||||
u32 ch1_odtmap;
|
||||
u32 res29[47];
|
||||
u32 ch1_dbg1;
|
||||
u32 ch1_dbgcam;
|
||||
u32 ch1_dbgcmd;
|
||||
u32 ch1_dbgstat;
|
||||
u32 res30[123];
|
||||
/* umctl2_regs_freq1 */
|
||||
struct ddrc_freq freq1;
|
||||
u32 res31[109];
|
||||
/* umctl2_regs_addrmap_alt */
|
||||
u32 addrmap0_alt;
|
||||
u32 addrmap1_alt;
|
||||
u32 addrmap2_alt;
|
||||
u32 addrmap3_alt;
|
||||
u32 addrmap4_alt;
|
||||
u32 addrmap5_alt;
|
||||
u32 addrmap6_alt;
|
||||
u32 addrmap7_alt;
|
||||
u32 addrmap8_alt;
|
||||
u32 addrmap9_alt;
|
||||
u32 addrmap10_alt;
|
||||
u32 addrmap11_alt;
|
||||
u32 res32[758];
|
||||
/* umctl2_regs_freq2 */
|
||||
struct ddrc_freq freq2;
|
||||
u32 res33[879];
|
||||
/* umctl2_regs_freq3 */
|
||||
struct ddrc_freq freq3;
|
||||
};
|
||||
|
||||
struct imx8m_ddrphy_regs {
|
||||
u32 reg[0xf0000];
|
||||
};
|
||||
|
||||
/* PHY State */
|
||||
enum pstate {
|
||||
PS0,
|
||||
PS1,
|
||||
PS2,
|
||||
PS3,
|
||||
};
|
||||
|
||||
enum msg_response {
|
||||
TRAIN_SUCCESS = 0x7,
|
||||
TRAIN_STREAM_START = 0x8,
|
||||
TRAIN_FAIL = 0xff,
|
||||
};
|
||||
|
||||
#endif
|
12
arch/arm/include/asm/arch-mx8m/gpio.h
Normal file
12
arch/arm/include/asm/arch-mx8m/gpio.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MX8M_GPIO_H
|
||||
#define __ASM_ARCH_MX8M_GPIO_H
|
||||
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
|
||||
#endif
|
468
arch/arm/include/asm/arch-mx8m/imx-regs.h
Normal file
468
arch/arm/include/asm/arch-mx8m/imx-regs.h
Normal file
|
@ -0,0 +1,468 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MX8M_REGS_H__
|
||||
#define __ASM_ARCH_MX8M_REGS_H__
|
||||
|
||||
#include <asm/mach-imx/regs-lcdif.h>
|
||||
|
||||
#define ROM_VERSION_A0 0x800
|
||||
#define ROM_VERSION_B0 0x83C
|
||||
|
||||
#define M4_BOOTROM_BASE_ADDR 0x007E0000
|
||||
|
||||
#define SAI1_BASE_ADDR 0x30010000
|
||||
#define SAI6_BASE_ADDR 0x30030000
|
||||
#define SAI5_BASE_ADDR 0x30040000
|
||||
#define SAI4_BASE_ADDR 0x30050000
|
||||
#define SPBA2_BASE_ADDR 0x300F0000
|
||||
#define AIPS1_BASE_ADDR 0x301F0000
|
||||
#define GPIO1_BASE_ADDR 0X30200000
|
||||
#define GPIO2_BASE_ADDR 0x30210000
|
||||
#define GPIO3_BASE_ADDR 0x30220000
|
||||
#define GPIO4_BASE_ADDR 0x30230000
|
||||
#define GPIO5_BASE_ADDR 0x30240000
|
||||
#define ANA_TSENSOR_BASE_ADDR 0x30260000
|
||||
#define ANA_OSC_BASE_ADDR 0x30270000
|
||||
#define WDOG1_BASE_ADDR 0x30280000
|
||||
#define WDOG2_BASE_ADDR 0x30290000
|
||||
#define WDOG3_BASE_ADDR 0x302A0000
|
||||
#define SDMA2_BASE_ADDR 0x302C0000
|
||||
#define GPT1_BASE_ADDR 0x302D0000
|
||||
#define GPT2_BASE_ADDR 0x302E0000
|
||||
#define GPT3_BASE_ADDR 0x302F0000
|
||||
#define ROMCP_BASE_ADDR 0x30310000
|
||||
#define LCDIF_BASE_ADDR 0x30320000
|
||||
#define IOMUXC_BASE_ADDR 0x30330000
|
||||
#define IOMUXC_GPR_BASE_ADDR 0x30340000
|
||||
#define OCOTP_BASE_ADDR 0x30350000
|
||||
#define ANATOP_BASE_ADDR 0x30360000
|
||||
#define SNVS_HP_BASE_ADDR 0x30370000
|
||||
#define CCM_BASE_ADDR 0x30380000
|
||||
#define SRC_BASE_ADDR 0x30390000
|
||||
#define GPC_BASE_ADDR 0x303A0000
|
||||
#define SEMAPHORE1_BASE_ADDR 0x303B0000
|
||||
#define SEMAPHORE2_BASE_ADDR 0x303C0000
|
||||
#define RDC_BASE_ADDR 0x303D0000
|
||||
#define CSU_BASE_ADDR 0x303E0000
|
||||
|
||||
#define AIPS2_BASE_ADDR 0x305F0000
|
||||
#define PWM1_BASE_ADDR 0x30660000
|
||||
#define PWM2_BASE_ADDR 0x30670000
|
||||
#define PWM3_BASE_ADDR 0x30680000
|
||||
#define PWM4_BASE_ADDR 0x30690000
|
||||
#define SYSCNT_RD_BASE_ADDR 0x306A0000
|
||||
#define SYSCNT_CMP_BASE_ADDR 0x306B0000
|
||||
#define SYSCNT_CTRL_BASE_ADDR 0x306C0000
|
||||
#define GPT6_BASE_ADDR 0x306E0000
|
||||
#define GPT5_BASE_ADDR 0x306F0000
|
||||
#define GPT4_BASE_ADDR 0x30700000
|
||||
#define PERFMON1_BASE_ADDR 0x307C0000
|
||||
#define PERFMON2_BASE_ADDR 0x307D0000
|
||||
#define QOSC_BASE_ADDR 0x307F0000
|
||||
|
||||
#define SPDIF1_BASE_ADDR 0x30810000
|
||||
#define ECSPI1_BASE_ADDR 0x30820000
|
||||
#define ECSPI2_BASE_ADDR 0x30830000
|
||||
#define ECSPI3_BASE_ADDR 0x30840000
|
||||
#define UART1_BASE_ADDR 0x30860000
|
||||
#define UART3_BASE_ADDR 0x30880000
|
||||
#define UART2_BASE_ADDR 0x30890000
|
||||
#define SPDIF2_BASE_ADDR 0x308A0000
|
||||
#define SAI2_BASE_ADDR 0x308B0000
|
||||
#define SAI3_BASE_ADDR 0x308C0000
|
||||
#define SPBA1_BASE_ADDR 0x308F0000
|
||||
#define CAAM_BASE_ADDR 0x30900000
|
||||
#define AIPS3_BASE_ADDR 0x309F0000
|
||||
#define MIPI_PHY_BASE_ADDR 0x30A00000
|
||||
#define MIPI_DSI_BASE_ADDR 0x30A10000
|
||||
#define I2C1_BASE_ADDR 0x30A20000
|
||||
#define I2C2_BASE_ADDR 0x30A30000
|
||||
#define I2C3_BASE_ADDR 0x30A40000
|
||||
#define I2C4_BASE_ADDR 0x30A50000
|
||||
#define UART4_BASE_ADDR 0x30A60000
|
||||
#define MIPI_CSI_BASE_ADDR 0x30A70000
|
||||
#define MIPI_CSI_PHY1_BASE_ADDR 0x30A80000
|
||||
#define CSI1_BASE_ADDR 0x30A90000
|
||||
#define MU_A_BASE_ADDR 0x30AA0000
|
||||
#define MU_B_BASE_ADDR 0x30AB0000
|
||||
#define SEMAPHOR_HS_BASE_ADDR 0x30AC0000
|
||||
#define USDHC1_BASE_ADDR 0x30B40000
|
||||
#define USDHC2_BASE_ADDR 0x30B50000
|
||||
#define MIPI_CS2_BASE_ADDR 0x30B60000
|
||||
#define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000
|
||||
#define CSI2_BASE_ADDR 0x30B80000
|
||||
#define QSPI0_BASE_ADDR 0x30BB0000
|
||||
#define QSPI0_AMBA_BASE 0x08000000
|
||||
#define SDMA1_BASE_ADDR 0x30BD0000
|
||||
#define ENET1_BASE_ADDR 0x30BE0000
|
||||
|
||||
#define HDMI_CTRL_BASE_ADDR 0x32C00000
|
||||
#define AIPS4_BASE_ADDR 0x32DF0000
|
||||
#define DC1_BASE_ADDR 0x32E00000
|
||||
#define DC2_BASE_ADDR 0x32E10000
|
||||
#define DC3_BASE_ADDR 0x32E20000
|
||||
#define HDMI_SEC_BASE_ADDR 0x32E40000
|
||||
#define TZASC_BASE_ADDR 0x32F80000
|
||||
#define MTR_BASE_ADDR 0x32FB0000
|
||||
#define PLATFORM_CTRL_BASE_ADDR 0x32FE0000
|
||||
|
||||
#define MXS_APBH_BASE 0x33000000
|
||||
#define MXS_GPMI_BASE 0x33002000
|
||||
#define MXS_BCH_BASE 0x33004000
|
||||
|
||||
#define USB1_BASE_ADDR 0x38100000
|
||||
#define USB2_BASE_ADDR 0x38200000
|
||||
#define USB1_PHY_BASE_ADDR 0x381F0000
|
||||
#define USB2_PHY_BASE_ADDR 0x382F0000
|
||||
|
||||
#define MXS_LCDIF_BASE LCDIF_BASE_ADDR
|
||||
|
||||
#define SRC_IPS_BASE_ADDR 0x30390000
|
||||
#define SRC_DDRC_RCR_ADDR 0x30391000
|
||||
#define SRC_DDRC2_RCR_ADDR 0x30391004
|
||||
|
||||
#define DDRC_DDR_SS_GPR0 0x3d000000
|
||||
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
|
||||
#define DDR_CSD1_BASE_ADDR 0x40000000
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <asm/types.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#define GPR_TZASC_EN BIT(0)
|
||||
#define GPR_TZASC_EN_LOCK BIT(16)
|
||||
|
||||
#define SRC_SCR_M4_ENABLE_OFFSET 3
|
||||
#define SRC_SCR_M4_ENABLE_MASK BIT(3)
|
||||
#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
|
||||
#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
|
||||
#define SRC_DDR1_ENABLE_MASK 0x8F000000UL
|
||||
#define SRC_DDR2_ENABLE_MASK 0x8F000000UL
|
||||
#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
|
||||
#define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2)
|
||||
#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
|
||||
#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
|
||||
|
||||
struct iomuxc_gpr_base_regs {
|
||||
u32 gpr[47];
|
||||
};
|
||||
|
||||
struct ocotp_regs {
|
||||
u32 ctrl;
|
||||
u32 ctrl_set;
|
||||
u32 ctrl_clr;
|
||||
u32 ctrl_tog;
|
||||
u32 timing;
|
||||
u32 rsvd0[3];
|
||||
u32 data;
|
||||
u32 rsvd1[3];
|
||||
u32 read_ctrl;
|
||||
u32 rsvd2[3];
|
||||
u32 read_fuse_data;
|
||||
u32 rsvd3[3];
|
||||
u32 sw_sticky;
|
||||
u32 rsvd4[3];
|
||||
u32 scs;
|
||||
u32 scs_set;
|
||||
u32 scs_clr;
|
||||
u32 scs_tog;
|
||||
u32 crc_addr;
|
||||
u32 rsvd5[3];
|
||||
u32 crc_value;
|
||||
u32 rsvd6[3];
|
||||
u32 version;
|
||||
u32 rsvd7[0xdb];
|
||||
|
||||
/* fuse banks */
|
||||
struct fuse_bank {
|
||||
u32 fuse_regs[0x10];
|
||||
} bank[0];
|
||||
};
|
||||
|
||||
struct fuse_bank0_regs {
|
||||
u32 lock;
|
||||
u32 rsvd0[3];
|
||||
u32 uid_low;
|
||||
u32 rsvd1[3];
|
||||
u32 uid_high;
|
||||
u32 rsvd2[7];
|
||||
};
|
||||
|
||||
struct fuse_bank1_regs {
|
||||
u32 tester3;
|
||||
u32 rsvd0[3];
|
||||
u32 tester4;
|
||||
u32 rsvd1[3];
|
||||
u32 tester5;
|
||||
u32 rsvd2[3];
|
||||
u32 cfg0;
|
||||
u32 rsvd3[3];
|
||||
};
|
||||
|
||||
struct anamix_pll {
|
||||
u32 audio_pll1_cfg0;
|
||||
u32 audio_pll1_cfg1;
|
||||
u32 audio_pll2_cfg0;
|
||||
u32 audio_pll2_cfg1;
|
||||
u32 video_pll_cfg0;
|
||||
u32 video_pll_cfg1;
|
||||
u32 gpu_pll_cfg0;
|
||||
u32 gpu_pll_cfg1;
|
||||
u32 vpu_pll_cfg0;
|
||||
u32 vpu_pll_cfg1;
|
||||
u32 arm_pll_cfg0;
|
||||
u32 arm_pll_cfg1;
|
||||
u32 sys_pll1_cfg0;
|
||||
u32 sys_pll1_cfg1;
|
||||
u32 sys_pll1_cfg2;
|
||||
u32 sys_pll2_cfg0;
|
||||
u32 sys_pll2_cfg1;
|
||||
u32 sys_pll2_cfg2;
|
||||
u32 sys_pll3_cfg0;
|
||||
u32 sys_pll3_cfg1;
|
||||
u32 sys_pll3_cfg2;
|
||||
u32 video_pll2_cfg0;
|
||||
u32 video_pll2_cfg1;
|
||||
u32 video_pll2_cfg2;
|
||||
u32 dram_pll_cfg0;
|
||||
u32 dram_pll_cfg1;
|
||||
u32 dram_pll_cfg2;
|
||||
u32 digprog;
|
||||
u32 osc_misc_cfg;
|
||||
u32 pllout_monitor_cfg;
|
||||
u32 frac_pllout_div_cfg;
|
||||
u32 sscg_pllout_div_cfg;
|
||||
};
|
||||
|
||||
struct fuse_bank9_regs {
|
||||
u32 mac_addr0;
|
||||
u32 rsvd0[3];
|
||||
u32 mac_addr1;
|
||||
u32 rsvd1[11];
|
||||
};
|
||||
|
||||
/* System Reset Controller (SRC) */
|
||||
struct src {
|
||||
u32 scr;
|
||||
u32 a53rcr;
|
||||
u32 a53rcr1;
|
||||
u32 m4rcr;
|
||||
u32 reserved1[4];
|
||||
u32 usbophy1_rcr;
|
||||
u32 usbophy2_rcr;
|
||||
u32 mipiphy_rcr;
|
||||
u32 pciephy_rcr;
|
||||
u32 hdmi_rcr;
|
||||
u32 disp_rcr;
|
||||
u32 reserved2[2];
|
||||
u32 gpu_rcr;
|
||||
u32 vpu_rcr;
|
||||
u32 pcie2_rcr;
|
||||
u32 mipiphy1_rcr;
|
||||
u32 mipiphy2_rcr;
|
||||
u32 reserved3;
|
||||
u32 sbmr1;
|
||||
u32 srsr;
|
||||
u32 reserved4[2];
|
||||
u32 sisr;
|
||||
u32 simr;
|
||||
u32 sbmr2;
|
||||
u32 gpr1;
|
||||
u32 gpr2;
|
||||
u32 gpr3;
|
||||
u32 gpr4;
|
||||
u32 gpr5;
|
||||
u32 gpr6;
|
||||
u32 gpr7;
|
||||
u32 gpr8;
|
||||
u32 gpr9;
|
||||
u32 gpr10;
|
||||
u32 reserved5[985];
|
||||
u32 ddr1_rcr;
|
||||
u32 ddr2_rcr;
|
||||
};
|
||||
|
||||
struct gpc_reg {
|
||||
u32 lpcr_bsc;
|
||||
u32 lpcr_ad;
|
||||
u32 lpcr_cpu1;
|
||||
u32 lpcr_cpu2;
|
||||
u32 lpcr_cpu3;
|
||||
u32 slpcr;
|
||||
u32 mst_cpu_mapping;
|
||||
u32 mmdc_cpu_mapping;
|
||||
u32 mlpcr;
|
||||
u32 pgc_ack_sel;
|
||||
u32 pgc_ack_sel_m4;
|
||||
u32 gpc_misc;
|
||||
u32 imr1_core0;
|
||||
u32 imr2_core0;
|
||||
u32 imr3_core0;
|
||||
u32 imr4_core0;
|
||||
u32 imr1_core1;
|
||||
u32 imr2_core1;
|
||||
u32 imr3_core1;
|
||||
u32 imr4_core1;
|
||||
u32 imr1_cpu1;
|
||||
u32 imr2_cpu1;
|
||||
u32 imr3_cpu1;
|
||||
u32 imr4_cpu1;
|
||||
u32 imr1_cpu3;
|
||||
u32 imr2_cpu3;
|
||||
u32 imr3_cpu3;
|
||||
u32 imr4_cpu3;
|
||||
u32 isr1_cpu0;
|
||||
u32 isr2_cpu0;
|
||||
u32 isr3_cpu0;
|
||||
u32 isr4_cpu0;
|
||||
u32 isr1_cpu1;
|
||||
u32 isr2_cpu1;
|
||||
u32 isr3_cpu1;
|
||||
u32 isr4_cpu1;
|
||||
u32 isr1_cpu2;
|
||||
u32 isr2_cpu2;
|
||||
u32 isr3_cpu2;
|
||||
u32 isr4_cpu2;
|
||||
u32 isr1_cpu3;
|
||||
u32 isr2_cpu3;
|
||||
u32 isr3_cpu3;
|
||||
u32 isr4_cpu3;
|
||||
u32 slt0_cfg;
|
||||
u32 slt1_cfg;
|
||||
u32 slt2_cfg;
|
||||
u32 slt3_cfg;
|
||||
u32 slt4_cfg;
|
||||
u32 slt5_cfg;
|
||||
u32 slt6_cfg;
|
||||
u32 slt7_cfg;
|
||||
u32 slt8_cfg;
|
||||
u32 slt9_cfg;
|
||||
u32 slt10_cfg;
|
||||
u32 slt11_cfg;
|
||||
u32 slt12_cfg;
|
||||
u32 slt13_cfg;
|
||||
u32 slt14_cfg;
|
||||
u32 pgc_cpu_0_1_mapping;
|
||||
u32 cpu_pgc_up_trg;
|
||||
u32 mix_pgc_up_trg;
|
||||
u32 pu_pgc_up_trg;
|
||||
u32 cpu_pgc_dn_trg;
|
||||
u32 mix_pgc_dn_trg;
|
||||
u32 pu_pgc_dn_trg;
|
||||
u32 lpcr_bsc2;
|
||||
u32 pgc_cpu_2_3_mapping;
|
||||
u32 lps_cpu0;
|
||||
u32 lps_cpu1;
|
||||
u32 lps_cpu2;
|
||||
u32 lps_cpu3;
|
||||
u32 gpc_gpr;
|
||||
u32 gtor;
|
||||
u32 debug_addr1;
|
||||
u32 debug_addr2;
|
||||
u32 cpu_pgc_up_status1;
|
||||
u32 mix_pgc_up_status0;
|
||||
u32 mix_pgc_up_status1;
|
||||
u32 mix_pgc_up_status2;
|
||||
u32 m4_mix_pgc_up_status0;
|
||||
u32 m4_mix_pgc_up_status1;
|
||||
u32 m4_mix_pgc_up_status2;
|
||||
u32 pu_pgc_up_status0;
|
||||
u32 pu_pgc_up_status1;
|
||||
u32 pu_pgc_up_status2;
|
||||
u32 m4_pu_pgc_up_status0;
|
||||
u32 m4_pu_pgc_up_status1;
|
||||
u32 m4_pu_pgc_up_status2;
|
||||
u32 a53_lp_io_0;
|
||||
u32 a53_lp_io_1;
|
||||
u32 a53_lp_io_2;
|
||||
u32 cpu_pgc_dn_status1;
|
||||
u32 mix_pgc_dn_status0;
|
||||
u32 mix_pgc_dn_status1;
|
||||
u32 mix_pgc_dn_status2;
|
||||
u32 m4_mix_pgc_dn_status0;
|
||||
u32 m4_mix_pgc_dn_status1;
|
||||
u32 m4_mix_pgc_dn_status2;
|
||||
u32 pu_pgc_dn_status0;
|
||||
u32 pu_pgc_dn_status1;
|
||||
u32 pu_pgc_dn_status2;
|
||||
u32 m4_pu_pgc_dn_status0;
|
||||
u32 m4_pu_pgc_dn_status1;
|
||||
u32 m4_pu_pgc_dn_status2;
|
||||
u32 res[3];
|
||||
u32 mix_pdn_flg;
|
||||
u32 pu_pdn_flg;
|
||||
u32 m4_mix_pdn_flg;
|
||||
u32 m4_pu_pdn_flg;
|
||||
u32 imr1_core2;
|
||||
u32 imr2_core2;
|
||||
u32 imr3_core2;
|
||||
u32 imr4_core2;
|
||||
u32 imr1_core3;
|
||||
u32 imr2_core3;
|
||||
u32 imr3_core3;
|
||||
u32 imr4_core3;
|
||||
u32 pgc_ack_sel_pu;
|
||||
u32 pgc_ack_sel_m4_pu;
|
||||
u32 slt15_cfg;
|
||||
u32 slt16_cfg;
|
||||
u32 slt17_cfg;
|
||||
u32 slt18_cfg;
|
||||
u32 slt19_cfg;
|
||||
u32 gpc_pu_pwrhsk;
|
||||
u32 slt0_cfg_pu;
|
||||
u32 slt1_cfg_pu;
|
||||
u32 slt2_cfg_pu;
|
||||
u32 slt3_cfg_pu;
|
||||
u32 slt4_cfg_pu;
|
||||
u32 slt5_cfg_pu;
|
||||
u32 slt6_cfg_pu;
|
||||
u32 slt7_cfg_pu;
|
||||
u32 slt8_cfg_pu;
|
||||
u32 slt9_cfg_pu;
|
||||
u32 slt10_cfg_pu;
|
||||
u32 slt11_cfg_pu;
|
||||
u32 slt12_cfg_pu;
|
||||
u32 slt13_cfg_pu;
|
||||
u32 slt14_cfg_pu;
|
||||
u32 slt15_cfg_pu;
|
||||
u32 slt16_cfg_pu;
|
||||
u32 slt17_cfg_pu;
|
||||
u32 slt18_cfg_pu;
|
||||
u32 slt19_cfg_pu;
|
||||
};
|
||||
|
||||
#define WDOG_WDT_MASK BIT(3)
|
||||
#define WDOG_WDZST_MASK BIT(0)
|
||||
struct wdog_regs {
|
||||
u16 wcr; /* Control */
|
||||
u16 wsr; /* Service */
|
||||
u16 wrsr; /* Reset Status */
|
||||
u16 wicr; /* Interrupt Control */
|
||||
u16 wmcr; /* Miscellaneous Control */
|
||||
};
|
||||
|
||||
struct bootrom_sw_info {
|
||||
u8 reserved_1;
|
||||
u8 boot_dev_instance;
|
||||
u8 boot_dev_type;
|
||||
u8 reserved_2;
|
||||
u32 core_freq;
|
||||
u32 axi_freq;
|
||||
u32 ddr_freq;
|
||||
u32 tick_freq;
|
||||
u32 reserved_3[3];
|
||||
};
|
||||
|
||||
#define ROM_SW_INFO_ADDR_B0 0x00000968
|
||||
#define ROM_SW_INFO_ADDR_A0 0x000009e8
|
||||
|
||||
#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
|
||||
(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
|
||||
(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
|
||||
#endif
|
||||
#endif
|
623
arch/arm/include/asm/arch-mx8m/mx8mq_pins.h
Normal file
623
arch/arm/include/asm/arch-mx8m/mx8mq_pins.h
Normal file
|
@ -0,0 +1,623 @@
|
|||
/*
|
||||
* Copyright (C) 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MX8MQ_PINS_H__
|
||||
#define __ASM_ARCH_MX8MQ_PINS_H__
|
||||
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
|
||||
enum {
|
||||
IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO09__CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0 = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1 = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2 = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
|
||||
IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_TXC__ENET_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_RXC__ENET_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_DATA1__CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_DATA2__CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
|
||||
IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
|
||||
IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
|
||||
IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
|
||||
IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
|
||||
IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
|
||||
IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
|
||||
IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2 = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
|
||||
IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
|
||||
IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
|
||||
IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
|
||||
IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
|
||||
IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
|
||||
IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
|
||||
IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
|
||||
IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
|
||||
IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
|
||||
IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0x10 | 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C1_SCL__ENET_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0x10 | 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C1_SDA__ENET_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
|
||||
IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0x10 | 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0x10 | 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0x10 | 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0x10 | 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0x10 | 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
|
||||
IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0x10 | 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0),
|
||||
IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_UART1_RXD__UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
|
||||
IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_UART1_TXD__UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_UART2_RXD__UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
|
||||
IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_UART2_TXD__UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_UART3_RXD__UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
|
||||
IMX8MQ_PAD_UART3_RXD__UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
|
||||
IMX8MQ_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_UART3_TXD__UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_UART3_TXD__UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
|
||||
IMX8MQ_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_UART4_RXD__UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
|
||||
IMX8MQ_PAD_UART4_RXD__UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
|
||||
IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
|
||||
IMX8MQ_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
|
||||
|
||||
IMX8MQ_PAD_UART4_TXD__UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
|
||||
IMX8MQ_PAD_UART4_TXD__UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
|
||||
IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0),
|
||||
IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
|
||||
};
|
||||
#endif
|
18
arch/arm/include/asm/arch-mx8m/sys_proto.h
Normal file
18
arch/arm/include/asm/arch-mx8m/sys_proto.h
Normal file
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Copyright (C) 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_MX8M_SYS_PROTO_H
|
||||
#define __ARCH_MX8M_SYS_PROTO_H
|
||||
|
||||
#include <asm/mach-imx/sys_proto.h>
|
||||
|
||||
void set_wdog_reset(struct wdog_regs *wdog);
|
||||
void enable_tzc380(void);
|
||||
void restore_boot_params(void);
|
||||
extern unsigned long rom_pointer[];
|
||||
enum boot_device get_boot_device(void);
|
||||
bool is_usb_boot(void);
|
||||
#endif
|
|
@ -26,10 +26,20 @@ enum boot_device {
|
|||
MMC4_BOOT,
|
||||
NAND_BOOT,
|
||||
QSPI_BOOT,
|
||||
USB_BOOT,
|
||||
UNKNOWN_BOOT,
|
||||
BOOT_DEV_NUM = UNKNOWN_BOOT,
|
||||
};
|
||||
|
||||
/* Boot device type */
|
||||
#define BOOT_TYPE_SD 0x1
|
||||
#define BOOT_TYPE_MMC 0x2
|
||||
#define BOOT_TYPE_NAND 0x3
|
||||
#define BOOT_TYPE_QSPI 0x4
|
||||
#define BOOT_TYPE_WEIM 0x5
|
||||
#define BOOT_TYPE_SPINOR 0x6
|
||||
#define BOOT_TYPE_USB 0xF
|
||||
|
||||
struct boot_mode {
|
||||
const char *name;
|
||||
unsigned cfg_val;
|
||||
|
|
|
@ -87,7 +87,27 @@ typedef u64 iomux_v3_cfg_t;
|
|||
#define IOMUX_CONFIG_LPSR 0x20
|
||||
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
|
||||
MUX_MODE_SHIFT)
|
||||
#ifdef CONFIG_MX7
|
||||
#ifdef CONFIG_MX8M
|
||||
#define PAD_CTL_DSE0 (0x0 << 0)
|
||||
#define PAD_CTL_DSE1 (0x1 << 0)
|
||||
#define PAD_CTL_DSE2 (0x2 << 0)
|
||||
#define PAD_CTL_DSE3 (0x3 << 0)
|
||||
#define PAD_CTL_DSE4 (0x4 << 0)
|
||||
#define PAD_CTL_DSE5 (0x5 << 0)
|
||||
#define PAD_CTL_DSE6 (0x6 << 0)
|
||||
#define PAD_CTL_DSE7 (0x7 << 0)
|
||||
|
||||
#define PAD_CTL_FSEL0 (0x0 << 3)
|
||||
#define PAD_CTL_FSEL1 (0x1 << 3)
|
||||
#define PAD_CTL_FSEL2 (0x2 << 3)
|
||||
#define PAD_CTL_FSEL3 (0x3 << 3)
|
||||
|
||||
#define PAD_CTL_ODE (0x1 << 5)
|
||||
#define PAD_CTL_PUE (0x1 << 6)
|
||||
#define PAD_CTL_HYS (0x1 << 7)
|
||||
#define PAD_CTL_LVTTL (0x1 << 8)
|
||||
|
||||
#elif defined CONFIG_MX7
|
||||
|
||||
#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
|
||||
|
||||
|
@ -240,7 +260,7 @@ void imx_iomux_gpio_get_function(unsigned int gpio,
|
|||
#if defined(CONFIG_MX6QDL)
|
||||
#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
|
||||
#define SETUP_IOMUX_PAD(def) \
|
||||
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \
|
||||
if (is_mx6dq() || is_mx6dqp()) { \
|
||||
imx_iomux_v3_setup_pad(MX6Q_##def); \
|
||||
} else { \
|
||||
imx_iomux_v3_setup_pad(MX6DL_##def); \
|
||||
|
|
|
@ -88,8 +88,7 @@ struct mxc_i2c_bus {
|
|||
|
||||
|
||||
#define I2C_PADS_INFO(name) \
|
||||
(is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \
|
||||
&mx6q_##name : &mx6s_##name
|
||||
(is_mx6dq() || is_mx6dqp()) ? &mx6q_##name : &mx6s_##name
|
||||
#endif
|
||||
|
||||
int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
|
||||
|
|
|
@ -19,11 +19,11 @@
|
|||
struct mxs_lcdif_regs {
|
||||
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
|
||||
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
|
||||
|
||||
#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
|
||||
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
|
||||
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
|
||||
defined(CONFIG_MX7)
|
||||
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
|
||||
defined(CONFIG_MX8M)
|
||||
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
|
||||
#endif
|
||||
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
|
||||
|
@ -61,7 +61,8 @@ struct mxs_lcdif_regs {
|
|||
#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
|
||||
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
|
||||
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
|
||||
defined(CONFIG_MX7)
|
||||
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
|
||||
defined(CONFIG_MX8M)
|
||||
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
|
||||
#endif
|
||||
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
|
||||
|
@ -72,7 +73,8 @@ struct mxs_lcdif_regs {
|
|||
#if defined(CONFIG_MX6SX) || \
|
||||
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
|
||||
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
|
||||
defined(CONFIG_MX7)
|
||||
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
|
||||
defined(CONFIG_MX8M)
|
||||
mxs_reg_32(hw_lcdif_thres)
|
||||
mxs_reg_32(hw_lcdif_as_ctrl)
|
||||
mxs_reg_32(hw_lcdif_as_buf)
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
|
||||
#define is_mx6() (is_soc_type(MXC_SOC_MX6))
|
||||
#define is_mx7() (is_soc_type(MXC_SOC_MX7))
|
||||
#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
|
||||
|
||||
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
|
||||
#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
|
||||
|
@ -126,4 +127,7 @@ void lcdif_power_down(void);
|
|||
int mxs_reset_block(struct mxs_register_32 *reg);
|
||||
int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
|
||||
int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
|
||||
|
||||
unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
|
||||
unsigned long reg1, unsigned long reg2);
|
||||
#endif
|
||||
|
|
|
@ -7,30 +7,41 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
|
||||
ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610))
|
||||
obj-y = iomux-v3.o
|
||||
endif
|
||||
|
||||
ifeq ($(SOC),$(filter $(SOC),mx8m))
|
||||
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
|
||||
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
|
||||
obj-$(CONFIG_FEC_MXC) += mac.o
|
||||
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
|
||||
obj-y += cpu.o
|
||||
endif
|
||||
|
||||
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
|
||||
obj-y += cpu.o speed.o
|
||||
obj-$(CONFIG_GPT_TIMER) += timer.o
|
||||
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
|
||||
endif
|
||||
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
|
||||
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m))
|
||||
obj-y += misc.o
|
||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
||||
endif
|
||||
ifeq ($(SOC),$(filter $(SOC),mx7))
|
||||
obj-y += cpu.o
|
||||
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
|
||||
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
|
||||
endif
|
||||
ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
|
||||
obj-y += cache.o init.o
|
||||
obj-$(CONFIG_SATA) += sata.o
|
||||
obj-$(CONFIG_FEC_MXC) += mac.o
|
||||
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
|
||||
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
|
||||
endif
|
||||
obj-$(CONFIG_SATA) += sata.o
|
||||
obj-$(CONFIG_SECURE_BOOT) += hab.o
|
||||
obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
|
||||
endif
|
||||
|
@ -124,8 +135,10 @@ spl/u-boot-nand-spl.imx: SPL FORCE
|
|||
|
||||
targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx)
|
||||
|
||||
obj-$(CONFIG_ARM64) += sip.o
|
||||
|
||||
obj-$(CONFIG_MX5) += mx5/
|
||||
obj-$(CONFIG_MX6) += mx6/
|
||||
obj-$(CONFIG_MX7) += mx7/
|
||||
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
|
||||
|
||||
obj-$(CONFIG_MX8M) += mx8m/
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <imx_thermal.h>
|
||||
#include <ipu_pixfmt.h>
|
||||
#include <thermal.h>
|
||||
|
@ -62,6 +63,11 @@ static char *get_reset_cause(void)
|
|||
return "WDOG4";
|
||||
case 0x00200:
|
||||
return "TEMPSENSE";
|
||||
#elif defined(CONFIG_MX8M)
|
||||
case 0x00100:
|
||||
return "WDOG2";
|
||||
case 0x00200:
|
||||
return "TEMPSENSE";
|
||||
#else
|
||||
case 0x00100:
|
||||
return "TEMPSENSE";
|
||||
|
@ -137,6 +143,8 @@ unsigned imx_ddr_size(void)
|
|||
const char *get_imx_type(u32 imxtype)
|
||||
{
|
||||
switch (imxtype) {
|
||||
case MXC_CPU_MX8MQ:
|
||||
return "8MQ"; /* Quad-core version of the mx8m */
|
||||
case MXC_CPU_MX7S:
|
||||
return "7S"; /* Single-core version of the mx7 */
|
||||
case MXC_CPU_MX7D:
|
||||
|
@ -259,7 +267,7 @@ int cpu_mmc_init(bd_t *bis)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_MX7
|
||||
#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
|
||||
u32 get_ahb_clk(void)
|
||||
{
|
||||
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
@ -293,6 +301,7 @@ void arch_preboot_os(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
#ifndef CONFIG_MX8M
|
||||
void set_chipselect_size(int const cs_size)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
@ -323,6 +332,125 @@ void set_chipselect_size(int const cs_size)
|
|||
|
||||
writel(reg, &iomuxc_regs->gpr[1]);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
|
||||
/*
|
||||
* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
|
||||
* defines a 2-bit SPEED_GRADING
|
||||
*/
|
||||
#define OCOTP_TESTER3_SPEED_SHIFT 8
|
||||
enum cpu_speed {
|
||||
OCOTP_TESTER3_SPEED_GRADE0,
|
||||
OCOTP_TESTER3_SPEED_GRADE1,
|
||||
OCOTP_TESTER3_SPEED_GRADE2,
|
||||
OCOTP_TESTER3_SPEED_GRADE3,
|
||||
};
|
||||
|
||||
u32 get_cpu_speed_grade_hz(void)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[1];
|
||||
struct fuse_bank1_regs *fuse =
|
||||
(struct fuse_bank1_regs *)bank->fuse_regs;
|
||||
uint32_t val;
|
||||
|
||||
val = readl(&fuse->tester3);
|
||||
val >>= OCOTP_TESTER3_SPEED_SHIFT;
|
||||
val &= 0x3;
|
||||
|
||||
switch(val) {
|
||||
case OCOTP_TESTER3_SPEED_GRADE0:
|
||||
return 800000000;
|
||||
case OCOTP_TESTER3_SPEED_GRADE1:
|
||||
return is_mx7() ? 500000000 : 1000000000;
|
||||
case OCOTP_TESTER3_SPEED_GRADE2:
|
||||
return is_mx7() ? 1000000000 : 1300000000;
|
||||
case OCOTP_TESTER3_SPEED_GRADE3:
|
||||
return is_mx7() ? 1200000000 : 1500000000;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
|
||||
* defines a 2-bit SPEED_GRADING
|
||||
*/
|
||||
#define OCOTP_TESTER3_TEMP_SHIFT 6
|
||||
|
||||
u32 get_cpu_temp_grade(int *minc, int *maxc)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[1];
|
||||
struct fuse_bank1_regs *fuse =
|
||||
(struct fuse_bank1_regs *)bank->fuse_regs;
|
||||
uint32_t val;
|
||||
|
||||
val = readl(&fuse->tester3);
|
||||
val >>= OCOTP_TESTER3_TEMP_SHIFT;
|
||||
val &= 0x3;
|
||||
|
||||
if (minc && maxc) {
|
||||
if (val == TEMP_AUTOMOTIVE) {
|
||||
*minc = -40;
|
||||
*maxc = 125;
|
||||
} else if (val == TEMP_INDUSTRIAL) {
|
||||
*minc = -40;
|
||||
*maxc = 105;
|
||||
} else if (val == TEMP_EXTCOMMERCIAL) {
|
||||
*minc = -20;
|
||||
*maxc = 105;
|
||||
} else {
|
||||
*minc = 0;
|
||||
*maxc = 95;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
|
||||
enum boot_device get_boot_device(void)
|
||||
{
|
||||
struct bootrom_sw_info **p =
|
||||
(struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
|
||||
|
||||
enum boot_device boot_dev = SD1_BOOT;
|
||||
u8 boot_type = (*p)->boot_dev_type;
|
||||
u8 boot_instance = (*p)->boot_dev_instance;
|
||||
|
||||
switch (boot_type) {
|
||||
case BOOT_TYPE_SD:
|
||||
boot_dev = boot_instance + SD1_BOOT;
|
||||
break;
|
||||
case BOOT_TYPE_MMC:
|
||||
boot_dev = boot_instance + MMC1_BOOT;
|
||||
break;
|
||||
case BOOT_TYPE_NAND:
|
||||
boot_dev = NAND_BOOT;
|
||||
break;
|
||||
case BOOT_TYPE_QSPI:
|
||||
boot_dev = QSPI_BOOT;
|
||||
break;
|
||||
case BOOT_TYPE_WEIM:
|
||||
boot_dev = WEIM_NOR_BOOT;
|
||||
break;
|
||||
case BOOT_TYPE_SPINOR:
|
||||
boot_dev = SPI_NOR_BOOT;
|
||||
break;
|
||||
#ifdef CONFIG_MX8M
|
||||
case BOOT_TYPE_USB:
|
||||
boot_dev = USB_BOOT;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return boot_dev;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NXP_BOARD_REVISION
|
||||
int nxp_board_rev(void)
|
||||
|
|
|
@ -5,21 +5,51 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-imx/sys_proto.h>
|
||||
#include <command.h>
|
||||
#include <imx_sip.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
/* Allow for arch specific config before we boot */
|
||||
int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
|
||||
int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
|
||||
{
|
||||
/* please define platform specific arch_auxiliary_core_up() */
|
||||
return CMD_RET_FAILURE;
|
||||
ulong stack, pc;
|
||||
|
||||
if (!boot_private_data)
|
||||
return -EINVAL;
|
||||
|
||||
stack = *(ulong *)boot_private_data;
|
||||
pc = *(ulong *)(boot_private_data + 4);
|
||||
|
||||
/* Set the stack and pc to M4 bootROM */
|
||||
writel(stack, M4_BOOTROM_BASE_ADDR);
|
||||
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
|
||||
|
||||
/* Enable M4 */
|
||||
#ifdef CONFIG_MX8M
|
||||
call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
|
||||
#else
|
||||
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
|
||||
SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Allow for arch specific config before we boot */
|
||||
int __weak arch_auxiliary_core_check_up(u32 core_id)
|
||||
int arch_auxiliary_core_check_up(u32 core_id)
|
||||
{
|
||||
/* please define platform specific arch_auxiliary_core_check_up() */
|
||||
return 0;
|
||||
#ifdef CONFIG_MX8M
|
||||
return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
|
||||
#else
|
||||
unsigned int val;
|
||||
|
||||
val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
|
||||
|
||||
if (val & SRC_M4C_NON_SCLR_RST_MASK)
|
||||
return 0; /* assert in reset */
|
||||
|
||||
return 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
61
arch/arm/mach-imx/mac.c
Normal file
61
arch/arm/mach-imx/mac.c
Normal file
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Peng Fan <peng.fan@nxp.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <errno.h>
|
||||
|
||||
struct imx_mac_fuse {
|
||||
u32 mac_addr0;
|
||||
u32 rsvd0[3];
|
||||
u32 mac_addr1;
|
||||
u32 rsvd1[3];
|
||||
u32 mac_addr2;
|
||||
u32 rsvd2[7];
|
||||
};
|
||||
|
||||
#define MAC_FUSE_MX6_OFFSET 0x620
|
||||
#define MAC_FUSE_MX7_OFFSET 0x640
|
||||
|
||||
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
|
||||
{
|
||||
struct imx_mac_fuse *fuse;
|
||||
u32 offset;
|
||||
bool has_second_mac;
|
||||
|
||||
offset = is_mx6() ? MAC_FUSE_MX6_OFFSET : MAC_FUSE_MX7_OFFSET;
|
||||
fuse = (struct imx_mac_fuse *)(ulong)(OCOTP_BASE_ADDR + offset);
|
||||
has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull();
|
||||
|
||||
if (has_second_mac && dev_id == 1) {
|
||||
u32 value = readl(&fuse->mac_addr2);
|
||||
|
||||
mac[0] = value >> 24;
|
||||
mac[1] = value >> 16;
|
||||
mac[2] = value >> 8;
|
||||
mac[3] = value;
|
||||
|
||||
value = readl(&fuse->mac_addr1);
|
||||
mac[4] = value >> 24;
|
||||
mac[5] = value >> 16;
|
||||
|
||||
} else {
|
||||
u32 value = readl(&fuse->mac_addr1);
|
||||
|
||||
mac[0] = value >> 8;
|
||||
mac[1] = value;
|
||||
|
||||
value = readl(&fuse->mac_addr0);
|
||||
mac[2] = value >> 24;
|
||||
mac[3] = value >> 16;
|
||||
mac[4] = value >> 8;
|
||||
mac[5] = value;
|
||||
}
|
||||
}
|
30
arch/arm/mach-imx/mmc_env.c
Normal file
30
arch/arm/mach-imx/mmc_env.c
Normal file
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (C) 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
|
||||
__weak int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return CONFIG_SYS_MMC_ENV_DEV;
|
||||
}
|
||||
|
||||
int mmc_get_env_dev(void)
|
||||
{
|
||||
struct bootrom_sw_info **p =
|
||||
(struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
|
||||
int devno = (*p)->boot_dev_instance;
|
||||
u8 boot_type = (*p)->boot_dev_type;
|
||||
|
||||
/* If not boot from sd/mmc, use default value */
|
||||
if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
|
||||
return CONFIG_SYS_MMC_ENV_DEV;
|
||||
|
||||
return board_mmc_get_env_dev(devno);
|
||||
}
|
|
@ -9,3 +9,8 @@
|
|||
|
||||
obj-y := soc.o clock.o
|
||||
obj-y += lowlevel_init.o
|
||||
|
||||
# common files for mx53 dram initialization
|
||||
obj-$(CONFIG_TARGET_M53EVK) += mx53_dram.o
|
||||
obj-$(CONFIG_TARGET_MX53CX9020) += mx53_dram.o
|
||||
obj-$(CONFIG_TARGET_MX53LOCO) += mx53_dram.o
|
||||
|
|
45
arch/arm/mach-imx/mx5/mx53_dram.c
Normal file
45
arch/arm/mach-imx/mx5/mx53_dram.c
Normal file
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (C) 2017 Beckhoff Automation GmbH & Co. KG
|
||||
* Patrick Bruenn <p.bruenn@beckhoff.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
phys_size_t get_effective_memsize(void)
|
||||
{
|
||||
/*
|
||||
* WARNING: We must override get_effective_memsize() function here
|
||||
* to report only the size of the first DRAM bank. This is to make
|
||||
* U-Boot relocator place U-Boot into valid memory, that is, at the
|
||||
* end of the first DRAM bank. If we did not override this function
|
||||
* like so, U-Boot would be placed at the address of the first DRAM
|
||||
* bank + total DRAM size - sizeof(uboot), which in the setup where
|
||||
* each DRAM bank contains 512MiB of DRAM would result in placing
|
||||
* U-Boot into invalid memory area close to the end of the first
|
||||
* DRAM bank.
|
||||
*/
|
||||
return get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
|
||||
gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
|
||||
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -518,40 +518,6 @@ int board_postclk_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[4];
|
||||
struct fuse_bank4_regs *fuse =
|
||||
(struct fuse_bank4_regs *)bank->fuse_regs;
|
||||
|
||||
if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
|
||||
u32 value = readl(&fuse->mac_addr2);
|
||||
mac[0] = value >> 24 ;
|
||||
mac[1] = value >> 16 ;
|
||||
mac[2] = value >> 8 ;
|
||||
mac[3] = value ;
|
||||
|
||||
value = readl(&fuse->mac_addr1);
|
||||
mac[4] = value >> 24 ;
|
||||
mac[5] = value >> 16 ;
|
||||
|
||||
} else {
|
||||
u32 value = readl(&fuse->mac_addr1);
|
||||
mac[0] = (value >> 8);
|
||||
mac[1] = value ;
|
||||
|
||||
value = readl(&fuse->mac_addr0);
|
||||
mac[2] = value >> 24 ;
|
||||
mac[3] = value >> 16 ;
|
||||
mac[4] = value >> 8 ;
|
||||
mac[5] = value ;
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
/*
|
||||
* cfg_val will be used for
|
||||
|
@ -700,41 +666,3 @@ void gpr_init(void)
|
|||
writel(0x007F007F, &iomux->gpr[7]);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IMX_BOOTAUX
|
||||
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
|
||||
{
|
||||
struct src *src_reg;
|
||||
u32 stack, pc;
|
||||
|
||||
if (!boot_private_data)
|
||||
return -EINVAL;
|
||||
|
||||
stack = *(u32 *)boot_private_data;
|
||||
pc = *(u32 *)(boot_private_data + 4);
|
||||
|
||||
/* Set the stack and pc to M4 bootROM */
|
||||
writel(stack, M4_BOOTROM_BASE_ADDR);
|
||||
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
|
||||
|
||||
/* Enable M4 */
|
||||
src_reg = (struct src *)SRC_BASE_ADDR;
|
||||
clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
|
||||
SRC_SCR_M4_ENABLE_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_auxiliary_core_check_up(u32 core_id)
|
||||
{
|
||||
struct src *src_reg = (struct src *)SRC_BASE_ADDR;
|
||||
unsigned val;
|
||||
|
||||
val = readl(&src_reg->scr);
|
||||
|
||||
if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
|
||||
return 0; /* assert in reset */
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -10,7 +10,7 @@
|
|||
#include <asm/secure.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <common.h>
|
||||
|
||||
#include <fsl_wdog.h>
|
||||
|
||||
#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
|
||||
#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
|
||||
|
@ -26,6 +26,15 @@
|
|||
#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
|
||||
#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
|
||||
|
||||
#define SNVS_LPCR 0x38
|
||||
#define BP_SNVS_LPCR_DP_EN 0x20
|
||||
#define BP_SNVS_LPCR_TOP 0x40
|
||||
|
||||
#define CCM_CCGR_SNVS 0x4250
|
||||
|
||||
#define CCM_ROOT_WDOG 0xbb80
|
||||
#define CCM_CCGR_WDOG1 0x49c0
|
||||
|
||||
static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
|
||||
{
|
||||
writel(enable, GPC_IPS_BASE_ADDR + offset);
|
||||
|
@ -74,3 +83,25 @@ __secure int imx_cpu_off(int cpu)
|
|||
writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
|
||||
return 0;
|
||||
}
|
||||
|
||||
__secure void imx_system_reset(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
/* make sure WDOG1 clock is enabled */
|
||||
writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG);
|
||||
writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
|
||||
writew(WCR_WDE, &wdog->wcr);
|
||||
}
|
||||
|
||||
__secure void imx_system_off(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* make sure SNVS clock is enabled */
|
||||
writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
|
||||
|
||||
val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
|
||||
val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
|
||||
writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
|
||||
}
|
||||
|
|
|
@ -43,4 +43,18 @@ psci_cpu_off:
|
|||
1: wfi
|
||||
b 1b
|
||||
|
||||
.globl psci_system_reset
|
||||
psci_system_reset:
|
||||
bl imx_system_reset
|
||||
|
||||
2: wfi
|
||||
b 2b
|
||||
|
||||
.globl psci_system_off
|
||||
psci_system_off:
|
||||
bl imx_system_off
|
||||
|
||||
3: wfi
|
||||
b 3b
|
||||
|
||||
.popsection
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <asm/arch/crm_regs.h>
|
||||
#include <dm.h>
|
||||
#include <imx_thermal.h>
|
||||
#include <fsl_sec.h>
|
||||
|
||||
#if defined(CONFIG_IMX_THERMAL)
|
||||
static const struct imx_thermal_plat imx7_thermal_plat = {
|
||||
|
@ -97,77 +98,6 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
|
|||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
|
||||
* defines a 2-bit SPEED_GRADING
|
||||
*/
|
||||
#define OCOTP_TESTER3_SPEED_SHIFT 8
|
||||
#define OCOTP_TESTER3_SPEED_800MHZ 0
|
||||
#define OCOTP_TESTER3_SPEED_500MHZ 1
|
||||
#define OCOTP_TESTER3_SPEED_1GHZ 2
|
||||
#define OCOTP_TESTER3_SPEED_1P2GHZ 3
|
||||
|
||||
u32 get_cpu_speed_grade_hz(void)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[1];
|
||||
struct fuse_bank1_regs *fuse =
|
||||
(struct fuse_bank1_regs *)bank->fuse_regs;
|
||||
uint32_t val;
|
||||
|
||||
val = readl(&fuse->tester3);
|
||||
val >>= OCOTP_TESTER3_SPEED_SHIFT;
|
||||
val &= 0x3;
|
||||
|
||||
switch(val) {
|
||||
case OCOTP_TESTER3_SPEED_800MHZ:
|
||||
return 800000000;
|
||||
case OCOTP_TESTER3_SPEED_500MHZ:
|
||||
return 500000000;
|
||||
case OCOTP_TESTER3_SPEED_1GHZ:
|
||||
return 1000000000;
|
||||
case OCOTP_TESTER3_SPEED_1P2GHZ:
|
||||
return 1200000000;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
|
||||
* defines a 2-bit SPEED_GRADING
|
||||
*/
|
||||
#define OCOTP_TESTER3_TEMP_SHIFT 6
|
||||
|
||||
u32 get_cpu_temp_grade(int *minc, int *maxc)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[1];
|
||||
struct fuse_bank1_regs *fuse =
|
||||
(struct fuse_bank1_regs *)bank->fuse_regs;
|
||||
uint32_t val;
|
||||
|
||||
val = readl(&fuse->tester3);
|
||||
val >>= OCOTP_TESTER3_TEMP_SHIFT;
|
||||
val &= 0x3;
|
||||
|
||||
if (minc && maxc) {
|
||||
if (val == TEMP_AUTOMOTIVE) {
|
||||
*minc = -40;
|
||||
*maxc = 125;
|
||||
} else if (val == TEMP_INDUSTRIAL) {
|
||||
*minc = -40;
|
||||
*maxc = 105;
|
||||
} else if (val == TEMP_EXTCOMMERCIAL) {
|
||||
*minc = -20;
|
||||
*maxc = 105;
|
||||
} else {
|
||||
*minc = 0;
|
||||
*maxc = 95;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
static bool is_mx7d(void)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
|
@ -262,6 +192,10 @@ int arch_misc_init(void)
|
|||
env_set("soc", "imx7s");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_CAAM
|
||||
sec_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
@ -279,74 +213,6 @@ void get_board_serial(struct tag_serialnr *serialnr)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[9];
|
||||
struct fuse_bank9_regs *fuse =
|
||||
(struct fuse_bank9_regs *)bank->fuse_regs;
|
||||
|
||||
if (0 == dev_id) {
|
||||
u32 value = readl(&fuse->mac_addr1);
|
||||
mac[0] = (value >> 8);
|
||||
mac[1] = value;
|
||||
|
||||
value = readl(&fuse->mac_addr0);
|
||||
mac[2] = value >> 24;
|
||||
mac[3] = value >> 16;
|
||||
mac[4] = value >> 8;
|
||||
mac[5] = value;
|
||||
} else {
|
||||
u32 value = readl(&fuse->mac_addr2);
|
||||
mac[0] = value >> 24;
|
||||
mac[1] = value >> 16;
|
||||
mac[2] = value >> 8;
|
||||
mac[3] = value;
|
||||
|
||||
value = readl(&fuse->mac_addr1);
|
||||
mac[4] = value >> 24;
|
||||
mac[5] = value >> 16;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMX_BOOTAUX
|
||||
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
|
||||
{
|
||||
u32 stack, pc;
|
||||
struct src *src_reg = (struct src *)SRC_BASE_ADDR;
|
||||
|
||||
if (!boot_private_data)
|
||||
return 1;
|
||||
|
||||
stack = *(u32 *)boot_private_data;
|
||||
pc = *(u32 *)(boot_private_data + 4);
|
||||
|
||||
/* Set the stack and pc to M4 bootROM */
|
||||
writel(stack, M4_BOOTROM_BASE_ADDR);
|
||||
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
|
||||
|
||||
/* Enable M4 */
|
||||
clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
|
||||
SRC_M4RCR_ENABLE_M4_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_auxiliary_core_check_up(u32 core_id)
|
||||
{
|
||||
uint32_t val;
|
||||
struct src *src_reg = (struct src *)SRC_BASE_ADDR;
|
||||
|
||||
val = readl(&src_reg->m4rcr);
|
||||
if (val & 0x00000001)
|
||||
return 0; /* assert in reset */
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
void set_wdog_reset(struct wdog_regs *wdog)
|
||||
{
|
||||
u32 reg = readw(&wdog->wcr);
|
||||
|
@ -389,62 +255,6 @@ const struct boot_mode soc_boot_modes[] = {
|
|||
{NULL, 0},
|
||||
};
|
||||
|
||||
enum boot_device get_boot_device(void)
|
||||
{
|
||||
struct bootrom_sw_info **p =
|
||||
(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
|
||||
|
||||
enum boot_device boot_dev = SD1_BOOT;
|
||||
u8 boot_type = (*p)->boot_dev_type;
|
||||
u8 boot_instance = (*p)->boot_dev_instance;
|
||||
|
||||
switch (boot_type) {
|
||||
case BOOT_TYPE_SD:
|
||||
boot_dev = boot_instance + SD1_BOOT;
|
||||
break;
|
||||
case BOOT_TYPE_MMC:
|
||||
boot_dev = boot_instance + MMC1_BOOT;
|
||||
break;
|
||||
case BOOT_TYPE_NAND:
|
||||
boot_dev = NAND_BOOT;
|
||||
break;
|
||||
case BOOT_TYPE_QSPI:
|
||||
boot_dev = QSPI_BOOT;
|
||||
break;
|
||||
case BOOT_TYPE_WEIM:
|
||||
boot_dev = WEIM_NOR_BOOT;
|
||||
break;
|
||||
case BOOT_TYPE_SPINOR:
|
||||
boot_dev = SPI_NOR_BOOT;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return boot_dev;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
__weak int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return CONFIG_SYS_MMC_ENV_DEV;
|
||||
}
|
||||
|
||||
int mmc_get_env_dev(void)
|
||||
{
|
||||
struct bootrom_sw_info **p =
|
||||
(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
|
||||
int devno = (*p)->boot_dev_instance;
|
||||
u8 boot_type = (*p)->boot_dev_type;
|
||||
|
||||
/* If not boot from sd/mmc, use default value */
|
||||
if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
|
||||
return CONFIG_SYS_MMC_ENV_DEV;
|
||||
|
||||
return board_mmc_get_env_dev(devno);
|
||||
}
|
||||
#endif
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
#if !defined CONFIG_SPL_BUILD
|
||||
|
|
10
arch/arm/mach-imx/mx8m/Kconfig
Normal file
10
arch/arm/mach-imx/mx8m/Kconfig
Normal file
|
@ -0,0 +1,10 @@
|
|||
if ARCH_MX8M
|
||||
|
||||
config MX8M
|
||||
bool
|
||||
select ROM_UNIFIED_SECTIONS
|
||||
|
||||
config SYS_SOC
|
||||
default "mx8m"
|
||||
|
||||
endif
|
8
arch/arm/mach-imx/mx8m/Makefile
Normal file
8
arch/arm/mach-imx/mx8m/Makefile
Normal file
|
@ -0,0 +1,8 @@
|
|||
#
|
||||
# Copyright 2017 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += lowlevel_init.o
|
||||
obj-y += clock.o clock_slice.o soc.o
|
795
arch/arm/mach-imx/mx8m/clock.c
Normal file
795
arch/arm/mach-imx/mx8m/clock.c
Normal file
|
@ -0,0 +1,795 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Peng Fan <peng.fan@nxp.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <errno.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
|
||||
|
||||
static u32 decode_frac_pll(enum clk_root_src frac_pll)
|
||||
{
|
||||
u32 pll_cfg0, pll_cfg1, pllout;
|
||||
u32 pll_refclk_sel, pll_refclk;
|
||||
u32 divr_val, divq_val, divf_val, divff, divfi;
|
||||
u32 pllout_div_shift, pllout_div_mask, pllout_div;
|
||||
|
||||
switch (frac_pll) {
|
||||
case ARM_PLL_CLK:
|
||||
pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
|
||||
pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
|
||||
pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
|
||||
pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
|
||||
break;
|
||||
default:
|
||||
printf("Frac PLL %d not supporte\n", frac_pll);
|
||||
return 0;
|
||||
}
|
||||
|
||||
pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
|
||||
pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
|
||||
|
||||
/* Power down */
|
||||
if (pll_cfg0 & FRAC_PLL_PD_MASK)
|
||||
return 0;
|
||||
|
||||
/* output not enabled */
|
||||
if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
|
||||
return 0;
|
||||
|
||||
pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
|
||||
|
||||
if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
|
||||
pll_refclk = 25000000u;
|
||||
else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
|
||||
pll_refclk = 27000000u;
|
||||
else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
|
||||
pll_refclk = 27000000u;
|
||||
else
|
||||
pll_refclk = 0;
|
||||
|
||||
if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
|
||||
return pll_refclk;
|
||||
|
||||
divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
|
||||
FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
|
||||
divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
|
||||
|
||||
divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
|
||||
FRAC_PLL_FRAC_DIV_CTL_SHIFT;
|
||||
divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
|
||||
|
||||
divf_val = 1 + divfi + divff / (1 << 24);
|
||||
|
||||
pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
|
||||
((divq_val + 1) * 2);
|
||||
|
||||
return pllout / (pllout_div + 1);
|
||||
}
|
||||
|
||||
static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
|
||||
{
|
||||
u32 pll_cfg0, pll_cfg1, pll_cfg2;
|
||||
u32 pll_refclk_sel, pll_refclk;
|
||||
u32 divr1, divr2, divf1, divf2, divq, div;
|
||||
u32 sse;
|
||||
u32 pll_clke;
|
||||
u32 pllout_div_shift, pllout_div_mask, pllout_div;
|
||||
u32 pllout;
|
||||
|
||||
switch (sscg_pll) {
|
||||
case SYSTEM_PLL1_800M_CLK:
|
||||
case SYSTEM_PLL1_400M_CLK:
|
||||
case SYSTEM_PLL1_266M_CLK:
|
||||
case SYSTEM_PLL1_200M_CLK:
|
||||
case SYSTEM_PLL1_160M_CLK:
|
||||
case SYSTEM_PLL1_133M_CLK:
|
||||
case SYSTEM_PLL1_100M_CLK:
|
||||
case SYSTEM_PLL1_80M_CLK:
|
||||
case SYSTEM_PLL1_40M_CLK:
|
||||
pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
|
||||
pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
|
||||
pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
|
||||
pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
|
||||
pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
|
||||
break;
|
||||
case SYSTEM_PLL2_1000M_CLK:
|
||||
case SYSTEM_PLL2_500M_CLK:
|
||||
case SYSTEM_PLL2_333M_CLK:
|
||||
case SYSTEM_PLL2_250M_CLK:
|
||||
case SYSTEM_PLL2_200M_CLK:
|
||||
case SYSTEM_PLL2_166M_CLK:
|
||||
case SYSTEM_PLL2_125M_CLK:
|
||||
case SYSTEM_PLL2_100M_CLK:
|
||||
case SYSTEM_PLL2_50M_CLK:
|
||||
pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
|
||||
pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
|
||||
pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
|
||||
pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
|
||||
pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
|
||||
break;
|
||||
case SYSTEM_PLL3_CLK:
|
||||
pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
|
||||
pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
|
||||
pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
|
||||
pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
|
||||
pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
|
||||
break;
|
||||
case DRAM_PLL1_CLK:
|
||||
pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
|
||||
pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
|
||||
pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
|
||||
pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
|
||||
pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
|
||||
break;
|
||||
default:
|
||||
printf("sscg pll %d not supporte\n", sscg_pll);
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (sscg_pll) {
|
||||
case DRAM_PLL1_CLK:
|
||||
pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
|
||||
div = 1;
|
||||
break;
|
||||
case SYSTEM_PLL3_CLK:
|
||||
pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
|
||||
div = 1;
|
||||
break;
|
||||
case SYSTEM_PLL2_1000M_CLK:
|
||||
case SYSTEM_PLL1_800M_CLK:
|
||||
pll_clke = SSCG_PLL_CLKE_MASK;
|
||||
div = 1;
|
||||
break;
|
||||
case SYSTEM_PLL2_500M_CLK:
|
||||
case SYSTEM_PLL1_400M_CLK:
|
||||
pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
|
||||
div = 2;
|
||||
break;
|
||||
case SYSTEM_PLL2_333M_CLK:
|
||||
case SYSTEM_PLL1_266M_CLK:
|
||||
pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
|
||||
div = 3;
|
||||
break;
|
||||
case SYSTEM_PLL2_250M_CLK:
|
||||
case SYSTEM_PLL1_200M_CLK:
|
||||
pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
|
||||
div = 4;
|
||||
break;
|
||||
case SYSTEM_PLL2_200M_CLK:
|
||||
case SYSTEM_PLL1_160M_CLK:
|
||||
pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
|
||||
div = 5;
|
||||
break;
|
||||
case SYSTEM_PLL2_166M_CLK:
|
||||
case SYSTEM_PLL1_133M_CLK:
|
||||
pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
|
||||
div = 6;
|
||||
break;
|
||||
case SYSTEM_PLL2_125M_CLK:
|
||||
case SYSTEM_PLL1_100M_CLK:
|
||||
pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
|
||||
div = 8;
|
||||
break;
|
||||
case SYSTEM_PLL2_100M_CLK:
|
||||
case SYSTEM_PLL1_80M_CLK:
|
||||
pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
|
||||
div = 10;
|
||||
break;
|
||||
case SYSTEM_PLL2_50M_CLK:
|
||||
case SYSTEM_PLL1_40M_CLK:
|
||||
pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
|
||||
div = 20;
|
||||
break;
|
||||
default:
|
||||
printf("sscg pll %d not supporte\n", sscg_pll);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Power down */
|
||||
if (pll_cfg0 & SSCG_PLL_PD_MASK)
|
||||
return 0;
|
||||
|
||||
/* output not enabled */
|
||||
if ((pll_cfg0 & pll_clke) == 0)
|
||||
return 0;
|
||||
|
||||
pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
|
||||
pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
|
||||
|
||||
pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
|
||||
|
||||
if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
|
||||
pll_refclk = 25000000u;
|
||||
else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
|
||||
pll_refclk = 27000000u;
|
||||
else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
|
||||
pll_refclk = 27000000u;
|
||||
else
|
||||
pll_refclk = 0;
|
||||
|
||||
/* We assume bypass1/2 are the same value */
|
||||
if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
|
||||
(pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
|
||||
return pll_refclk;
|
||||
|
||||
divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
|
||||
SSCG_PLL_REF_DIVR1_SHIFT;
|
||||
divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
|
||||
SSCG_PLL_REF_DIVR2_SHIFT;
|
||||
divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
|
||||
SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
|
||||
divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
|
||||
SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
|
||||
divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
|
||||
SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
|
||||
sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
|
||||
|
||||
if (sse)
|
||||
sse = 8;
|
||||
else
|
||||
sse = 2;
|
||||
|
||||
pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
|
||||
(divr2 + 1) * (divf2 + 1) / (divq + 1);
|
||||
|
||||
return pllout / (pllout_div + 1) / div;
|
||||
}
|
||||
|
||||
static u32 get_root_src_clk(enum clk_root_src root_src)
|
||||
{
|
||||
switch (root_src) {
|
||||
case OSC_25M_CLK:
|
||||
return 25000000;
|
||||
case OSC_27M_CLK:
|
||||
return 25000000;
|
||||
case OSC_32K_CLK:
|
||||
return 32000;
|
||||
case ARM_PLL_CLK:
|
||||
return decode_frac_pll(root_src);
|
||||
case SYSTEM_PLL1_800M_CLK:
|
||||
case SYSTEM_PLL1_400M_CLK:
|
||||
case SYSTEM_PLL1_266M_CLK:
|
||||
case SYSTEM_PLL1_200M_CLK:
|
||||
case SYSTEM_PLL1_160M_CLK:
|
||||
case SYSTEM_PLL1_133M_CLK:
|
||||
case SYSTEM_PLL1_100M_CLK:
|
||||
case SYSTEM_PLL1_80M_CLK:
|
||||
case SYSTEM_PLL1_40M_CLK:
|
||||
case SYSTEM_PLL2_1000M_CLK:
|
||||
case SYSTEM_PLL2_500M_CLK:
|
||||
case SYSTEM_PLL2_333M_CLK:
|
||||
case SYSTEM_PLL2_250M_CLK:
|
||||
case SYSTEM_PLL2_200M_CLK:
|
||||
case SYSTEM_PLL2_166M_CLK:
|
||||
case SYSTEM_PLL2_125M_CLK:
|
||||
case SYSTEM_PLL2_100M_CLK:
|
||||
case SYSTEM_PLL2_50M_CLK:
|
||||
case SYSTEM_PLL3_CLK:
|
||||
return decode_sscg_pll(root_src);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 get_root_clk(enum clk_root_index clock_id)
|
||||
{
|
||||
enum clk_root_src root_src;
|
||||
u32 post_podf, pre_podf, root_src_clk;
|
||||
|
||||
if (clock_root_enabled(clock_id) <= 0)
|
||||
return 0;
|
||||
|
||||
if (clock_get_prediv(clock_id, &pre_podf) < 0)
|
||||
return 0;
|
||||
|
||||
if (clock_get_postdiv(clock_id, &post_podf) < 0)
|
||||
return 0;
|
||||
|
||||
if (clock_get_src(clock_id, &root_src) < 0)
|
||||
return 0;
|
||||
|
||||
root_src_clk = get_root_src_clk(root_src);
|
||||
|
||||
return root_src_clk / (post_podf + 1) / (pre_podf + 1);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MXC_OCOTP
|
||||
void enable_ocotp_clk(unsigned char enable)
|
||||
{
|
||||
clock_enable(CCGR_OCOTP, !!enable);
|
||||
}
|
||||
#endif
|
||||
|
||||
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
|
||||
{
|
||||
/* 0 - 3 is valid i2c num */
|
||||
if (i2c_num > 3)
|
||||
return -EINVAL;
|
||||
|
||||
clock_enable(CCGR_I2C1 + i2c_num, !!enable);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int mxc_get_clock(enum clk_root_index clk)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (clk >= CLK_ROOT_MAX)
|
||||
return 0;
|
||||
|
||||
if (clk == MXC_ARM_CLK)
|
||||
return get_root_clk(ARM_A53_CLK_ROOT);
|
||||
|
||||
if (clk == MXC_IPG_CLK) {
|
||||
clock_get_target_val(IPG_CLK_ROOT, &val);
|
||||
val = val & 0x3;
|
||||
return get_root_clk(AHB_CLK_ROOT) / (val + 1);
|
||||
}
|
||||
|
||||
return get_root_clk(clk);
|
||||
}
|
||||
|
||||
u32 imx_get_uartclk(void)
|
||||
{
|
||||
return mxc_get_clock(UART1_CLK_ROOT);
|
||||
}
|
||||
|
||||
void mxs_set_lcdclk(u32 base_addr, u32 freq)
|
||||
{
|
||||
/*
|
||||
* LCDIF_PIXEL_CLK: select 800MHz root clock,
|
||||
* select pre divider 8, output is 100 MHz
|
||||
*/
|
||||
clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(4) |
|
||||
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
|
||||
}
|
||||
|
||||
void init_wdog_clk(void)
|
||||
{
|
||||
clock_enable(CCGR_WDOG1, 0);
|
||||
clock_enable(CCGR_WDOG2, 0);
|
||||
clock_enable(CCGR_WDOG3, 0);
|
||||
clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_enable(CCGR_WDOG1, 1);
|
||||
clock_enable(CCGR_WDOG2, 1);
|
||||
clock_enable(CCGR_WDOG3, 1);
|
||||
}
|
||||
|
||||
void init_usb_clk(void)
|
||||
{
|
||||
if (!is_usb_boot()) {
|
||||
clock_enable(CCGR_USB_CTRL1, 0);
|
||||
clock_enable(CCGR_USB_CTRL2, 0);
|
||||
clock_enable(CCGR_USB_PHY1, 0);
|
||||
clock_enable(CCGR_USB_PHY2, 0);
|
||||
/* 500MHz */
|
||||
clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(1));
|
||||
/* 100MHz */
|
||||
clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(1));
|
||||
/* 100MHz */
|
||||
clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(1));
|
||||
clock_enable(CCGR_USB_CTRL1, 1);
|
||||
clock_enable(CCGR_USB_CTRL2, 1);
|
||||
clock_enable(CCGR_USB_PHY1, 1);
|
||||
clock_enable(CCGR_USB_PHY2, 1);
|
||||
}
|
||||
}
|
||||
|
||||
void init_uart_clk(u32 index)
|
||||
{
|
||||
/* Set uart clock root 25M OSC */
|
||||
switch (index) {
|
||||
case 0:
|
||||
clock_enable(CCGR_UART1, 0);
|
||||
clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_enable(CCGR_UART1, 1);
|
||||
return;
|
||||
case 1:
|
||||
clock_enable(CCGR_UART2, 0);
|
||||
clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_enable(CCGR_UART2, 1);
|
||||
return;
|
||||
case 2:
|
||||
clock_enable(CCGR_UART3, 0);
|
||||
clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_enable(CCGR_UART3, 1);
|
||||
return;
|
||||
case 3:
|
||||
clock_enable(CCGR_UART4, 0);
|
||||
clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_enable(CCGR_UART4, 1);
|
||||
return;
|
||||
default:
|
||||
printf("Invalid uart index\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void init_clk_usdhc(u32 index)
|
||||
{
|
||||
/*
|
||||
* set usdhc clock root
|
||||
* sys pll1 400M
|
||||
*/
|
||||
switch (index) {
|
||||
case 0:
|
||||
clock_enable(CCGR_USDHC1, 0);
|
||||
clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(1) |
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
|
||||
clock_enable(CCGR_USDHC1, 1);
|
||||
return;
|
||||
case 1:
|
||||
clock_enable(CCGR_USDHC2, 0);
|
||||
clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(1) |
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
|
||||
clock_enable(CCGR_USDHC2, 1);
|
||||
return;
|
||||
default:
|
||||
printf("Invalid usdhc index\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
int set_clk_qspi(void)
|
||||
{
|
||||
/*
|
||||
* set qspi root
|
||||
* sys pll1 100M
|
||||
*/
|
||||
clock_enable(CCGR_QSPI, 0);
|
||||
clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(7));
|
||||
clock_enable(CCGR_QSPI, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int set_clk_enet(enum enet_freq type)
|
||||
{
|
||||
u32 target;
|
||||
u32 enet1_ref;
|
||||
|
||||
switch (type) {
|
||||
case ENET_125MHZ:
|
||||
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
|
||||
break;
|
||||
case ENET_50MHZ:
|
||||
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
|
||||
break;
|
||||
case ENET_25MHZ:
|
||||
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* disable the clock first */
|
||||
clock_enable(CCGR_ENET1, 0);
|
||||
clock_enable(CCGR_SIM_ENET, 0);
|
||||
|
||||
/* set enet axi clock 266Mhz */
|
||||
target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
|
||||
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
|
||||
clock_set_target_val(ENET_AXI_CLK_ROOT, target);
|
||||
|
||||
target = CLK_ROOT_ON | enet1_ref |
|
||||
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
|
||||
clock_set_target_val(ENET_REF_CLK_ROOT, target);
|
||||
|
||||
target = CLK_ROOT_ON |
|
||||
ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
|
||||
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
|
||||
clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
|
||||
|
||||
/* enable clock */
|
||||
clock_enable(CCGR_SIM_ENET, 1);
|
||||
clock_enable(CCGR_ENET1, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
u32 imx_get_fecclk(void)
|
||||
{
|
||||
return get_root_clk(ENET_AXI_CLK_ROOT);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void dram_pll_init(void)
|
||||
{
|
||||
struct src *src = (struct src *)SRC_BASE_ADDR;
|
||||
void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
|
||||
u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7));
|
||||
setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5));
|
||||
|
||||
pwdn_mask = SSCG_PLL_PD_MASK;
|
||||
pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
|
||||
bypass1 = SSCG_PLL_BYPASS1_MASK;
|
||||
bypass2 = SSCG_PLL_BYPASS2_MASK;
|
||||
|
||||
/* Enable DDR1 and DDR2 domain */
|
||||
writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr);
|
||||
writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr);
|
||||
|
||||
/* Clear power down bit */
|
||||
clrbits_le32(pll_control_reg, pwdn_mask);
|
||||
/* Eanble ARM_PLL/SYS_PLL */
|
||||
setbits_le32(pll_control_reg, pll_clke);
|
||||
|
||||
/* Clear bypass */
|
||||
clrbits_le32(pll_control_reg, bypass1);
|
||||
__udelay(100);
|
||||
clrbits_le32(pll_control_reg, bypass2);
|
||||
/* Wait lock */
|
||||
ret = readl_poll_timeout(pll_control_reg, val,
|
||||
val & SSCG_PLL_LOCK_MASK, 1);
|
||||
if (ret)
|
||||
printf("%s timeout\n", __func__);
|
||||
}
|
||||
|
||||
int frac_pll_init(u32 pll, enum frac_pll_out_val val)
|
||||
{
|
||||
void __iomem *pll_cfg0, __iomem *pll_cfg1;
|
||||
u32 val_cfg0, val_cfg1;
|
||||
int ret;
|
||||
|
||||
switch (pll) {
|
||||
case ANATOP_ARM_PLL:
|
||||
pll_cfg0 = &ana_pll->arm_pll_cfg0;
|
||||
pll_cfg1 = &ana_pll->arm_pll_cfg1;
|
||||
|
||||
if (val == FRAC_PLL_OUT_1000M)
|
||||
val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
|
||||
else
|
||||
val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
|
||||
val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
|
||||
FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
|
||||
FRAC_PLL_REFCLK_DIV_VAL(4) |
|
||||
FRAC_PLL_OUTPUT_DIV_VAL(0);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* bypass the clock */
|
||||
setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
|
||||
/* Set the value */
|
||||
writel(val_cfg1, pll_cfg1);
|
||||
writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
|
||||
val_cfg0 = readl(pll_cfg0);
|
||||
/* unbypass the clock */
|
||||
clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
|
||||
ret = readl_poll_timeout(pll_cfg0, val_cfg0,
|
||||
val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
|
||||
if (ret)
|
||||
printf("%s timeout\n", __func__);
|
||||
clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sscg_pll_init(u32 pll)
|
||||
{
|
||||
void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
|
||||
u32 val_cfg0, val_cfg1, val_cfg2, val;
|
||||
u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
|
||||
int ret;
|
||||
|
||||
switch (pll) {
|
||||
case ANATOP_SYSTEM_PLL1:
|
||||
pll_cfg0 = &ana_pll->sys_pll1_cfg0;
|
||||
pll_cfg1 = &ana_pll->sys_pll1_cfg1;
|
||||
pll_cfg2 = &ana_pll->sys_pll1_cfg2;
|
||||
/* 800MHz */
|
||||
val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
|
||||
SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
|
||||
val_cfg1 = 0;
|
||||
val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
|
||||
SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
|
||||
SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
|
||||
SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
|
||||
SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
|
||||
SSCG_PLL_REFCLK_SEL_OSC_25M;
|
||||
break;
|
||||
case ANATOP_SYSTEM_PLL2:
|
||||
pll_cfg0 = &ana_pll->sys_pll2_cfg0;
|
||||
pll_cfg1 = &ana_pll->sys_pll2_cfg1;
|
||||
pll_cfg2 = &ana_pll->sys_pll2_cfg2;
|
||||
/* 1000MHz */
|
||||
val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
|
||||
SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
|
||||
val_cfg1 = 0;
|
||||
val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
|
||||
SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
|
||||
SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
|
||||
SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
|
||||
SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
|
||||
SSCG_PLL_REFCLK_SEL_OSC_25M;
|
||||
break;
|
||||
case ANATOP_SYSTEM_PLL3:
|
||||
pll_cfg0 = &ana_pll->sys_pll3_cfg0;
|
||||
pll_cfg1 = &ana_pll->sys_pll3_cfg1;
|
||||
pll_cfg2 = &ana_pll->sys_pll3_cfg2;
|
||||
/* 800MHz */
|
||||
val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
|
||||
SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
|
||||
val_cfg1 = 0;
|
||||
val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
|
||||
SSCG_PLL_REFCLK_SEL_OSC_25M;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*bypass*/
|
||||
setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
|
||||
/* set value */
|
||||
writel(val_cfg2, pll_cfg2);
|
||||
writel(val_cfg1, pll_cfg1);
|
||||
/*unbypass1 and wait 70us */
|
||||
writel(val_cfg0 | bypass2_mask, pll_cfg1);
|
||||
|
||||
__udelay(70);
|
||||
|
||||
/* unbypass2 and wait lock */
|
||||
writel(val_cfg0, pll_cfg1);
|
||||
ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
|
||||
if (ret)
|
||||
printf("%s timeout\n", __func__);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int clock_init(void)
|
||||
{
|
||||
u32 grade;
|
||||
|
||||
clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(0));
|
||||
|
||||
/*
|
||||
* 8MQ only supports two grades: consumer and industrial.
|
||||
* We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
|
||||
*/
|
||||
grade = get_cpu_temp_grade(NULL, NULL);
|
||||
if (!grade) {
|
||||
frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
|
||||
clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(1) |
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
|
||||
} else {
|
||||
frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
|
||||
clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(1) |
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
|
||||
}
|
||||
/*
|
||||
* According to ANAMIX SPEC
|
||||
* sys pll1 fixed at 800MHz
|
||||
* sys pll2 fixed at 1GHz
|
||||
* Here we only enable the outputs.
|
||||
*/
|
||||
setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
|
||||
SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
|
||||
SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
|
||||
SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
|
||||
SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
|
||||
|
||||
setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
|
||||
SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
|
||||
SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
|
||||
SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
|
||||
SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
|
||||
|
||||
clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
|
||||
CLK_ROOT_SOURCE_SEL(1));
|
||||
|
||||
init_wdog_clk();
|
||||
clock_enable(CCGR_TSENSOR, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Dump some clockes.
|
||||
*/
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
u32 freq;
|
||||
|
||||
freq = decode_frac_pll(ARM_PLL_CLK);
|
||||
printf("ARM_PLL %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
|
||||
printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
|
||||
printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
|
||||
printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
|
||||
printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
|
||||
printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
|
||||
printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
|
||||
printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
|
||||
printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
|
||||
printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
|
||||
printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
|
||||
printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
|
||||
printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
|
||||
printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
|
||||
printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
|
||||
printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
|
||||
printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
|
||||
printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
|
||||
printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
|
||||
printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
|
||||
freq = mxc_get_clock(UART1_CLK_ROOT);
|
||||
printf("UART1 %8d MHz\n", freq / 1000000);
|
||||
freq = mxc_get_clock(USDHC1_CLK_ROOT);
|
||||
printf("USDHC1 %8d MHz\n", freq / 1000000);
|
||||
freq = mxc_get_clock(QSPI_CLK_ROOT);
|
||||
printf("QSPI %8d MHz\n", freq / 1000000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
clocks, CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks,
|
||||
"display clocks",
|
||||
""
|
||||
);
|
||||
#endif
|
742
arch/arm/mach-imx/mx8m/clock_slice.c
Normal file
742
arch/arm/mach-imx/mx8m/clock_slice.c
Normal file
|
@ -0,0 +1,742 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Peng Fan <peng.fan@nxp.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
static struct clk_root_map root_array[] = {
|
||||
{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
|
||||
{OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
|
||||
},
|
||||
{ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
|
||||
},
|
||||
{VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
|
||||
{OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
|
||||
},
|
||||
{GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
|
||||
{OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
|
||||
{OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
|
||||
},
|
||||
{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
|
||||
},
|
||||
{VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
|
||||
AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
|
||||
EXT_CLK_1, EXT_CLK_4}
|
||||
},
|
||||
{DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
|
||||
EXT_CLK_1, EXT_CLK_3}
|
||||
},
|
||||
{DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
|
||||
EXT_CLK_2, EXT_CLK_3}
|
||||
},
|
||||
{USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
|
||||
SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{IPG_CLK_ROOT, IPG_CLOCK_SLICE, 0,
|
||||
{}
|
||||
},
|
||||
{AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL1_CLK },
|
||||
},
|
||||
{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
|
||||
},
|
||||
{DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
|
||||
{OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
|
||||
SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
|
||||
},
|
||||
{VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
|
||||
{OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
|
||||
SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
|
||||
},
|
||||
{DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
|
||||
{OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
|
||||
{OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{PCIE1_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
|
||||
},
|
||||
{PCIE1_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
|
||||
SYSTEM_PLL1_400M_CLK}
|
||||
},
|
||||
{PCIE1_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
|
||||
},
|
||||
{DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
|
||||
{OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
|
||||
AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
|
||||
},
|
||||
{LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
|
||||
{OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
|
||||
AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
|
||||
},
|
||||
{SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
|
||||
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
|
||||
},
|
||||
{SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
|
||||
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
|
||||
},
|
||||
{SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
|
||||
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
|
||||
},
|
||||
{SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
|
||||
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
|
||||
},
|
||||
{SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
|
||||
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
|
||||
},
|
||||
{SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
|
||||
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
|
||||
},
|
||||
{SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
|
||||
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
|
||||
},
|
||||
{SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
|
||||
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
|
||||
},
|
||||
{ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
|
||||
},
|
||||
{ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
|
||||
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
|
||||
VIDEO_PLL_CLK}
|
||||
},
|
||||
{ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
|
||||
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
|
||||
SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
|
||||
SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
|
||||
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
|
||||
},
|
||||
{I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
|
||||
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
|
||||
},
|
||||
{I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
|
||||
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
|
||||
},
|
||||
{I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
|
||||
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
|
||||
},
|
||||
{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
|
||||
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
|
||||
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
|
||||
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
|
||||
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
|
||||
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
|
||||
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
|
||||
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
|
||||
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
|
||||
},
|
||||
{GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
|
||||
},
|
||||
{GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
|
||||
},
|
||||
{GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
|
||||
},
|
||||
{GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
|
||||
},
|
||||
{GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
|
||||
},
|
||||
{TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
|
||||
SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
|
||||
},
|
||||
{WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
|
||||
},
|
||||
{WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, OSC_27M_CLK,
|
||||
SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
|
||||
},
|
||||
{IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
|
||||
},
|
||||
{MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{OLD_MIPI_DSI_ESC_CLK_ROOT, IP_CLOCK_SLICE, 57,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
|
||||
},
|
||||
{PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
|
||||
EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
|
||||
},
|
||||
{PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
|
||||
},
|
||||
{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{OLD_MIPI_DSI_ESC_RX_ROOT, IP_CLOCK_SLICE, 68,
|
||||
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
|
||||
},
|
||||
{DISPLAY_HDMI_CLK_ROOT, IP_CLOCK_SLICE, 69,
|
||||
{OSC_25M_CLK, SYSTEM_PLL1_200M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
|
||||
},
|
||||
{DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
|
||||
{DRAM_PLL1_CLK}
|
||||
},
|
||||
{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
|
||||
{DRAM_PLL1_CLK}
|
||||
},
|
||||
};
|
||||
|
||||
static int select(enum clk_root_index clock_id)
|
||||
{
|
||||
int i, size;
|
||||
struct clk_root_map *p = root_array;
|
||||
|
||||
size = ARRAY_SIZE(root_array);
|
||||
|
||||
for (i = 0; i < size; i++, p++) {
|
||||
if (clock_id == p->entry)
|
||||
return i;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void __iomem *get_clk_root_target(enum clk_slice_type slice_type,
|
||||
u32 slice_index)
|
||||
{
|
||||
void __iomem *clk_root_target;
|
||||
|
||||
switch (slice_type) {
|
||||
case CORE_CLOCK_SLICE:
|
||||
clk_root_target =
|
||||
(void __iomem *)&ccm_reg->core_root[slice_index];
|
||||
break;
|
||||
case BUS_CLOCK_SLICE:
|
||||
clk_root_target =
|
||||
(void __iomem *)&ccm_reg->bus_root[slice_index];
|
||||
break;
|
||||
case IP_CLOCK_SLICE:
|
||||
clk_root_target =
|
||||
(void __iomem *)&ccm_reg->ip_root[slice_index];
|
||||
break;
|
||||
case AHB_CLOCK_SLICE:
|
||||
clk_root_target =
|
||||
(void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2];
|
||||
break;
|
||||
case IPG_CLOCK_SLICE:
|
||||
clk_root_target =
|
||||
(void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2 + 1];
|
||||
break;
|
||||
case CORE_SEL_CLOCK_SLICE:
|
||||
clk_root_target = (void __iomem *)&ccm_reg->core_sel;
|
||||
break;
|
||||
case DRAM_SEL_CLOCK_SLICE:
|
||||
clk_root_target = (void __iomem *)&ccm_reg->dram_sel;
|
||||
break;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return clk_root_target;
|
||||
}
|
||||
|
||||
int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
|
||||
{
|
||||
int root_entry;
|
||||
struct clk_root_map *p;
|
||||
void __iomem *clk_root_target;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
p = &root_array[root_entry];
|
||||
clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
|
||||
if (!clk_root_target)
|
||||
return -EINVAL;
|
||||
|
||||
*val = readl(clk_root_target);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_set_target_val(enum clk_root_index clock_id, u32 val)
|
||||
{
|
||||
int root_entry;
|
||||
struct clk_root_map *p;
|
||||
void __iomem *clk_root_target;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
p = &root_array[root_entry];
|
||||
clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
|
||||
if (!clk_root_target)
|
||||
return -EINVAL;
|
||||
|
||||
writel(val, clk_root_target);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_root_enabled(enum clk_root_index clock_id)
|
||||
{
|
||||
void __iomem *clk_root_target;
|
||||
u32 slice_index, slice_type;
|
||||
u32 val;
|
||||
int root_entry;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
slice_type = root_array[root_entry].slice_type;
|
||||
slice_index = root_array[root_entry].slice_index;
|
||||
|
||||
if ((slice_type == IPG_CLOCK_SLICE) ||
|
||||
(slice_type == DRAM_SEL_CLOCK_SLICE) ||
|
||||
(slice_type == CORE_SEL_CLOCK_SLICE)) {
|
||||
/*
|
||||
* Not supported, from CCM doc
|
||||
* TODO
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
clk_root_target = get_clk_root_target(slice_type, slice_index);
|
||||
if (!clk_root_target)
|
||||
return -EINVAL;
|
||||
|
||||
val = readl(clk_root_target);
|
||||
|
||||
return (val & CLK_ROOT_ON) ? 1 : 0;
|
||||
}
|
||||
|
||||
/* CCGR CLK gate operation */
|
||||
int clock_enable(enum clk_ccgr_index index, bool enable)
|
||||
{
|
||||
void __iomem *ccgr;
|
||||
|
||||
if (index >= CCGR_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
if (enable)
|
||||
ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_set;
|
||||
else
|
||||
ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_clr;
|
||||
|
||||
writel(CCGR_CLK_ON_MASK, ccgr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
|
||||
{
|
||||
u32 val;
|
||||
int root_entry;
|
||||
struct clk_root_map *p;
|
||||
void __iomem *clk_root_target;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
p = &root_array[root_entry];
|
||||
|
||||
if ((p->slice_type == CORE_CLOCK_SLICE) ||
|
||||
(p->slice_type == IPG_CLOCK_SLICE) ||
|
||||
(p->slice_type == CORE_SEL_CLOCK_SLICE) ||
|
||||
(p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
|
||||
*pre_div = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
|
||||
if (!clk_root_target)
|
||||
return -EINVAL;
|
||||
|
||||
val = readl(clk_root_target);
|
||||
val &= CLK_ROOT_PRE_DIV_MASK;
|
||||
val >>= CLK_ROOT_PRE_DIV_SHIFT;
|
||||
|
||||
*pre_div = val;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_get_postdiv(enum clk_root_index clock_id,
|
||||
enum root_post_div *post_div)
|
||||
{
|
||||
u32 val, mask;
|
||||
int root_entry;
|
||||
struct clk_root_map *p;
|
||||
void __iomem *clk_root_target;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
p = &root_array[root_entry];
|
||||
|
||||
if ((p->slice_type == CORE_SEL_CLOCK_SLICE) ||
|
||||
(p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
|
||||
*post_div = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
|
||||
if (!clk_root_target)
|
||||
return -EINVAL;
|
||||
|
||||
if (p->slice_type == IPG_CLOCK_SLICE)
|
||||
mask = CLK_ROOT_IPG_POST_DIV_MASK;
|
||||
else if (p->slice_type == CORE_CLOCK_SLICE)
|
||||
mask = CLK_ROOT_CORE_POST_DIV_MASK;
|
||||
else
|
||||
mask = CLK_ROOT_POST_DIV_MASK;
|
||||
|
||||
val = readl(clk_root_target);
|
||||
val &= mask;
|
||||
val >>= CLK_ROOT_POST_DIV_SHIFT;
|
||||
|
||||
*post_div = val;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
|
||||
{
|
||||
u32 val;
|
||||
int root_entry;
|
||||
struct clk_root_map *p;
|
||||
void __iomem *clk_root_target;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
p = &root_array[root_entry];
|
||||
|
||||
clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
|
||||
if (!clk_root_target)
|
||||
return -EINVAL;
|
||||
|
||||
val = readl(clk_root_target);
|
||||
val &= CLK_ROOT_SRC_MUX_MASK;
|
||||
val >>= CLK_ROOT_SRC_MUX_SHIFT;
|
||||
|
||||
*p_clock_src = p->src_mux[val];
|
||||
|
||||
return 0;
|
||||
}
|
63
arch/arm/mach-imx/mx8m/lowlevel_init.S
Normal file
63
arch/arm/mach-imx/mx8m/lowlevel_init.S
Normal file
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
.align 8
|
||||
.global rom_pointer
|
||||
rom_pointer:
|
||||
.space 256
|
||||
|
||||
/*
|
||||
* Routine: save_boot_params (called after reset from start.S)
|
||||
*/
|
||||
|
||||
.global save_boot_params
|
||||
save_boot_params:
|
||||
/* The firmware provided ATAG/FDT address can be found in r2/x0 */
|
||||
adr x0, rom_pointer
|
||||
stp x1, x2, [x0], #16
|
||||
stp x3, x4, [x0], #16
|
||||
stp x5, x6, [x0], #16
|
||||
stp x7, x8, [x0], #16
|
||||
stp x9, x10, [x0], #16
|
||||
stp x11, x12, [x0], #16
|
||||
stp x13, x14, [x0], #16
|
||||
stp x15, x16, [x0], #16
|
||||
stp x17, x18, [x0], #16
|
||||
stp x19, x20, [x0], #16
|
||||
stp x21, x22, [x0], #16
|
||||
stp x23, x24, [x0], #16
|
||||
stp x25, x26, [x0], #16
|
||||
stp x27, x28, [x0], #16
|
||||
stp x29, x30, [x0], #16
|
||||
mov x30, sp
|
||||
str x30, [x0], #8
|
||||
|
||||
/* Returns */
|
||||
b save_boot_params_ret
|
||||
|
||||
.global restore_boot_params
|
||||
restore_boot_params:
|
||||
adr x0, rom_pointer
|
||||
ldp x1, x2, [x0], #16
|
||||
ldp x3, x4, [x0], #16
|
||||
ldp x5, x6, [x0], #16
|
||||
ldp x7, x8, [x0], #16
|
||||
ldp x9, x10, [x0], #16
|
||||
ldp x11, x12, [x0], #16
|
||||
ldp x13, x14, [x0], #16
|
||||
ldp x15, x16, [x0], #16
|
||||
ldp x17, x18, [x0], #16
|
||||
ldp x19, x20, [x0], #16
|
||||
ldp x21, x22, [x0], #16
|
||||
ldp x23, x24, [x0], #16
|
||||
ldp x25, x26, [x0], #16
|
||||
ldp x27, x28, [x0], #16
|
||||
ldp x29, x30, [x0], #16
|
||||
ldr x0, [x0]
|
||||
mov sp, x0
|
||||
ret
|
227
arch/arm/mach-imx/mx8m/soc.c
Normal file
227
arch/arm/mach-imx/mx8m/soc.c
Normal file
|
@ -0,0 +1,227 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Peng Fan <peng.fan@nxp.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/hab.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/mach-imx/syscounter.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <errno.h>
|
||||
#include <fdt_support.h>
|
||||
#include <fsl_wdog.h>
|
||||
#include <imx_sip.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_SECURE_BOOT)
|
||||
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
|
||||
.bank = 1,
|
||||
.word = 3,
|
||||
};
|
||||
#endif
|
||||
|
||||
int timer_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
|
||||
unsigned long freq = readl(&sctr->cntfid0);
|
||||
|
||||
/* Update with accurate clock frequency */
|
||||
asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
|
||||
|
||||
clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
|
||||
SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
|
||||
#endif
|
||||
|
||||
gd->arch.tbl = 0;
|
||||
gd->arch.tbu = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void enable_tzc380(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *gpr =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
/* Enable TZASC and lock setting */
|
||||
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
|
||||
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
|
||||
}
|
||||
|
||||
void set_wdog_reset(struct wdog_regs *wdog)
|
||||
{
|
||||
/*
|
||||
* Output WDOG_B signal to reset external pmic or POR_B decided by
|
||||
* the board design. Without external reset, the peripherals/DDR/
|
||||
* PMIC are not reset, that may cause system working abnormal.
|
||||
* WDZST bit is write-once only bit. Align this bit in kernel,
|
||||
* otherwise kernel code will have no chance to set this bit.
|
||||
*/
|
||||
setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
|
||||
}
|
||||
|
||||
static struct mm_region imx8m_mem_map[] = {
|
||||
{
|
||||
/* ROM */
|
||||
.virt = 0x0UL,
|
||||
.phys = 0x0UL,
|
||||
.size = 0x100000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_OUTER_SHARE
|
||||
}, {
|
||||
/* OCRAM */
|
||||
.virt = 0x900000UL,
|
||||
.phys = 0x900000UL,
|
||||
.size = 0x200000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_OUTER_SHARE
|
||||
}, {
|
||||
/* AIPS */
|
||||
.virt = 0xB00000UL,
|
||||
.phys = 0xB00000UL,
|
||||
.size = 0x3f500000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* DRAM1 */
|
||||
.virt = 0x40000000UL,
|
||||
.phys = 0x40000000UL,
|
||||
.size = 0xC0000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_OUTER_SHARE
|
||||
}, {
|
||||
/* DRAM2 */
|
||||
.virt = 0x100000000UL,
|
||||
.phys = 0x100000000UL,
|
||||
.size = 0x040000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_OUTER_SHARE
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = imx8m_mem_map;
|
||||
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
|
||||
u32 reg = readl(&ana_pll->digprog);
|
||||
u32 type = (reg >> 16) & 0xff;
|
||||
u32 rom_version;
|
||||
|
||||
reg &= 0xff;
|
||||
|
||||
if (reg == CHIP_REV_1_0) {
|
||||
/*
|
||||
* For B0 chip, the DIGPROG is not updated, still TO1.0.
|
||||
* we have to check ROM version further
|
||||
*/
|
||||
rom_version = readl((void __iomem *)ROM_VERSION_A0);
|
||||
if (rom_version != CHIP_REV_1_0) {
|
||||
rom_version = readl((void __iomem *)ROM_VERSION_B0);
|
||||
if (rom_version >= CHIP_REV_2_0)
|
||||
reg = CHIP_REV_2_0;
|
||||
}
|
||||
}
|
||||
|
||||
return (type << 12) | reg;
|
||||
}
|
||||
|
||||
static void imx_set_wdog_powerdown(bool enable)
|
||||
{
|
||||
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
|
||||
struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
|
||||
|
||||
/* Write to the PDE (Power Down Enable) bit */
|
||||
writew(enable, &wdog1->wmcr);
|
||||
writew(enable, &wdog2->wmcr);
|
||||
writew(enable, &wdog3->wmcr);
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
/*
|
||||
* Init timer at very early state, because sscg pll setting
|
||||
* will use it
|
||||
*/
|
||||
timer_init();
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
clock_init();
|
||||
imx_set_wdog_powerdown(false);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool is_usb_boot(void)
|
||||
{
|
||||
return get_boot_device() == USB_BOOT;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_SYSTEM_SETUP
|
||||
int ft_system_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int i = 0;
|
||||
int rc;
|
||||
int nodeoff;
|
||||
|
||||
/* Disable the CPU idle for A0 chip since the HW does not support it */
|
||||
if (is_soc_rev(CHIP_REV_1_0)) {
|
||||
static const char * const nodes_path[] = {
|
||||
"/cpus/cpu@0",
|
||||
"/cpus/cpu@1",
|
||||
"/cpus/cpu@2",
|
||||
"/cpus/cpu@3",
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
|
||||
nodeoff = fdt_path_offset(blob, nodes_path[i]);
|
||||
if (nodeoff < 0)
|
||||
continue; /* Not found, skip it */
|
||||
|
||||
printf("Found %s node\n", nodes_path[i]);
|
||||
|
||||
rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
|
||||
if (rc) {
|
||||
printf("Unable to update property %s:%s, err=%s\n",
|
||||
nodes_path[i], "status", fdt_strerror(rc));
|
||||
return rc;
|
||||
}
|
||||
|
||||
printf("Remove %s:%s\n", nodes_path[i],
|
||||
"cpu-idle-states");
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
/* Clear WDA to trigger WDOG_B immediately */
|
||||
writew((WCR_WDE | WCR_SRS), &wdog->wcr);
|
||||
|
||||
while (1) {
|
||||
/*
|
||||
* spin for .5 seconds before reset
|
||||
*/
|
||||
}
|
||||
}
|
23
arch/arm/mach-imx/sip.c
Normal file
23
arch/arm/mach-imx/sip.c
Normal file
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
|
||||
unsigned long reg1, unsigned long reg2)
|
||||
{
|
||||
struct pt_regs regs;
|
||||
|
||||
regs.regs[0] = id;
|
||||
regs.regs[1] = reg0;
|
||||
regs.regs[2] = reg1;
|
||||
regs.regs[3] = reg2;
|
||||
|
||||
smc_call(®s);
|
||||
|
||||
return regs.regs[0];
|
||||
}
|
|
@ -97,8 +97,8 @@ u32 spl_boot_device(void)
|
|||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_MX7)
|
||||
/* Translate iMX7 boot device to the SPL boot device enumeration */
|
||||
#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M)
|
||||
/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
enum boot_device boot_device_spl = get_boot_device();
|
||||
|
@ -115,11 +115,13 @@ u32 spl_boot_device(void)
|
|||
return BOOT_DEVICE_NAND;
|
||||
case SPI_NOR_BOOT:
|
||||
return BOOT_DEVICE_SPI;
|
||||
case USB_BOOT:
|
||||
return BOOT_DEVICE_USB;
|
||||
default:
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_MX6 || CONFIG_MX7 */
|
||||
#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */
|
||||
|
||||
#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
|
||||
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
|
||||
|
|
|
@ -31,45 +31,6 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static uint32_t mx53_dram_size[2];
|
||||
|
||||
phys_size_t get_effective_memsize(void)
|
||||
{
|
||||
/*
|
||||
* WARNING: We must override get_effective_memsize() function here
|
||||
* to report only the size of the first DRAM bank. This is to make
|
||||
* U-Boot relocator place U-Boot into valid memory, that is, at the
|
||||
* end of the first DRAM bank. If we did not override this function
|
||||
* like so, U-Boot would be placed at the address of the first DRAM
|
||||
* bank + total DRAM size - sizeof(uboot), which in the setup where
|
||||
* each DRAM bank contains 512MiB of DRAM would result in placing
|
||||
* U-Boot into invalid memory area close to the end of the first
|
||||
* DRAM bank.
|
||||
*/
|
||||
return mx53_dram_size[0];
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
|
||||
mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
|
||||
|
||||
gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = mx53_dram_size[0];
|
||||
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = mx53_dram_size[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t uart_pads[] = {
|
||||
|
|
|
@ -59,45 +59,6 @@ static const u32 CCAT_MODE_RUN = 0x0033DC8F;
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static uint32_t mx53_dram_size[2];
|
||||
|
||||
phys_size_t get_effective_memsize(void)
|
||||
{
|
||||
/*
|
||||
* WARNING: We must override get_effective_memsize() function here
|
||||
* to report only the size of the first DRAM bank. This is to make
|
||||
* U-Boot relocator place U-Boot into valid memory, that is, at the
|
||||
* end of the first DRAM bank. If we did not override this function
|
||||
* like so, U-Boot would be placed at the address of the first DRAM
|
||||
* bank + total DRAM size - sizeof(uboot), which in the setup where
|
||||
* each DRAM bank contains 512MiB of DRAM would result in placing
|
||||
* U-Boot into invalid memory area close to the end of the first
|
||||
* DRAM bank.
|
||||
*/
|
||||
return mx53_dram_size[0];
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
|
||||
mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
|
||||
|
||||
gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = mx53_dram_size[0];
|
||||
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = mx53_dram_size[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
|
||||
|
|
|
@ -39,12 +39,17 @@ static void setenv_fdt_file(void)
|
|||
if (!strcmp(cmp_dtb, "imx6q-icore")) {
|
||||
if (is_mx6dq())
|
||||
env_set("fdt_file", "imx6q-icore.dtb");
|
||||
else if(is_mx6dl() || is_mx6solo())
|
||||
else if (is_mx6dl() || is_mx6solo())
|
||||
env_set("fdt_file", "imx6dl-icore.dtb");
|
||||
} else if (!strcmp(cmp_dtb, "imx6q-icore-mipi")) {
|
||||
if (is_mx6dq())
|
||||
env_set("fdt_file", "imx6q-icore-mipi.dtb");
|
||||
else if (is_mx6dl() || is_mx6solo())
|
||||
env_set("fdt_file", "imx6dl-icore-mipi.dtb");
|
||||
} else if (!strcmp(cmp_dtb, "imx6q-icore-rqs")) {
|
||||
if (is_mx6dq())
|
||||
env_set("fdt_file", "imx6q-icore-rqs.dtb");
|
||||
else if(is_mx6dl() || is_mx6solo())
|
||||
else if (is_mx6dl() || is_mx6solo())
|
||||
env_set("fdt_file", "imx6dl-icore-rqs.dtb");
|
||||
} else if (!strcmp(cmp_dtb, "imx6ul-geam-kit"))
|
||||
env_set("fdt_file", "imx6ul-geam-kit.dtb");
|
||||
|
|
|
@ -31,45 +31,6 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static uint32_t mx53_dram_size[2];
|
||||
|
||||
phys_size_t get_effective_memsize(void)
|
||||
{
|
||||
/*
|
||||
* WARNING: We must override get_effective_memsize() function here
|
||||
* to report only the size of the first DRAM bank. This is to make
|
||||
* U-Boot relocator place U-Boot into valid memory, that is, at the
|
||||
* end of the first DRAM bank. If we did not override this function
|
||||
* like so, U-Boot would be placed at the address of the first DRAM
|
||||
* bank + total DRAM size - sizeof(uboot), which in the setup where
|
||||
* each DRAM bank contains 512MiB of DRAM would result in placing
|
||||
* U-Boot into invalid memory area close to the end of the first
|
||||
* DRAM bank.
|
||||
*/
|
||||
return mx53_dram_size[0];
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
|
||||
mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
|
||||
|
||||
gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = mx53_dram_size[0];
|
||||
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = mx53_dram_size[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
|
||||
|
|
|
@ -453,5 +453,4 @@ void board_init_f(ulong dummy)
|
|||
display_calibration(&calibration);
|
||||
}
|
||||
}
|
||||
reset_cpu(0);
|
||||
}
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <mmc.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <miiphy.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/mxc_hdmi.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
|
@ -28,7 +29,9 @@
|
|||
#include <input.h>
|
||||
#include <pwm.h>
|
||||
#include <stdlib.h>
|
||||
#include "../common/ge_common.h"
|
||||
#include "../common/vpd_reader.h"
|
||||
#include "../../../drivers/net/e1000.h"
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
|
||||
|
@ -37,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_I2C_EEPROM_BUS
|
||||
#define CONFIG_SYS_I2C_EEPROM_BUS 2
|
||||
#define CONFIG_SYS_I2C_EEPROM_BUS 4
|
||||
#endif
|
||||
|
||||
#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
||||
|
@ -546,63 +549,78 @@ int overwrite_console(void)
|
|||
#define VPD_PRODUCT_B850 1
|
||||
#define VPD_PRODUCT_B650 2
|
||||
#define VPD_PRODUCT_B450 3
|
||||
#define VPD_HAS_MAC1 0x1
|
||||
#define VPD_HAS_MAC2 0x2
|
||||
#define VPD_MAC_ADDRESS_LENGTH 6
|
||||
|
||||
struct vpd_cache {
|
||||
uint8_t product_id;
|
||||
uint8_t macbits;
|
||||
unsigned char mac1[6];
|
||||
u8 product_id;
|
||||
u8 has;
|
||||
unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
|
||||
unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
|
||||
};
|
||||
|
||||
/*
|
||||
* Extracts MAC and product information from the VPD.
|
||||
*/
|
||||
static int vpd_callback(
|
||||
void *userdata,
|
||||
uint8_t id,
|
||||
uint8_t version,
|
||||
uint8_t type,
|
||||
size_t size,
|
||||
uint8_t const *data)
|
||||
static int vpd_callback(void *userdata, u8 id, u8 version, u8 type,
|
||||
size_t size, u8 const *data)
|
||||
{
|
||||
struct vpd_cache *vpd = (struct vpd_cache *)userdata;
|
||||
|
||||
if ( id == VPD_BLOCK_HWID
|
||||
&& version == 1
|
||||
&& type != VPD_TYPE_INVALID
|
||||
&& size >= 1) {
|
||||
if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
|
||||
size >= 1) {
|
||||
vpd->product_id = data[0];
|
||||
|
||||
} else if ( id == VPD_BLOCK_NETWORK
|
||||
&& version == 1
|
||||
&& type != VPD_TYPE_INVALID
|
||||
&& size >= 6) {
|
||||
vpd->macbits |= 1;
|
||||
memcpy(vpd->mac1, data, 6);
|
||||
} else if (id == VPD_BLOCK_NETWORK && version == 1 &&
|
||||
type != VPD_TYPE_INVALID) {
|
||||
if (size >= 6) {
|
||||
vpd->has |= VPD_HAS_MAC1;
|
||||
memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
|
||||
}
|
||||
if (size >= 12) {
|
||||
vpd->has |= VPD_HAS_MAC2;
|
||||
memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void set_eth0_mac_address(unsigned char * mac)
|
||||
{
|
||||
uint32_t *ENET_TCR = (uint32_t*)0x21880c4;
|
||||
uint32_t *ENET_PALR = (uint32_t*)0x21880e4;
|
||||
uint32_t *ENET_PAUR = (uint32_t*)0x21880e8;
|
||||
|
||||
*ENET_TCR |= 0x100; /* ADDINS */
|
||||
*ENET_PALR |= (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
|
||||
*ENET_PAUR |= (mac[4] << 24) | (mac[5] << 16);
|
||||
}
|
||||
|
||||
static void process_vpd(struct vpd_cache *vpd)
|
||||
{
|
||||
if ( vpd->product_id == VPD_PRODUCT_B850
|
||||
|| vpd->product_id == VPD_PRODUCT_B650
|
||||
|| vpd->product_id == VPD_PRODUCT_B450) {
|
||||
if (vpd->macbits & 1) {
|
||||
set_eth0_mac_address(vpd->mac1);
|
||||
}
|
||||
int fec_index = -1;
|
||||
int i210_index = -1;
|
||||
|
||||
switch (vpd->product_id) {
|
||||
case VPD_PRODUCT_B450:
|
||||
env_set("confidx", "1");
|
||||
break;
|
||||
case VPD_PRODUCT_B650:
|
||||
env_set("confidx", "2");
|
||||
break;
|
||||
case VPD_PRODUCT_B850:
|
||||
env_set("confidx", "3");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (vpd->product_id) {
|
||||
case VPD_PRODUCT_B450:
|
||||
/* fall thru */
|
||||
case VPD_PRODUCT_B650:
|
||||
i210_index = 0;
|
||||
fec_index = 1;
|
||||
break;
|
||||
case VPD_PRODUCT_B850:
|
||||
i210_index = 1;
|
||||
fec_index = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
|
||||
eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
|
||||
|
||||
if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
|
||||
eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
|
||||
}
|
||||
|
||||
static int read_vpd(uint eeprom_bus)
|
||||
|
@ -641,6 +659,8 @@ int board_eth_init(bd_t *bis)
|
|||
setup_iomux_enet();
|
||||
setup_pcie();
|
||||
|
||||
e1000_initialize(bis);
|
||||
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
|
@ -652,6 +672,7 @@ static iomux_v3_cfg_t const misc_pads[] = {
|
|||
MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
||||
MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
||||
MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
||||
MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
|
||||
};
|
||||
#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
|
||||
#define WIFI_EN IMX_GPIO_NR(6, 14)
|
||||
|
@ -694,8 +715,6 @@ int board_init(void)
|
|||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
|
||||
|
||||
read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -761,6 +780,8 @@ void pmic_init(void)
|
|||
|
||||
int board_late_init(void)
|
||||
{
|
||||
read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
@ -785,6 +806,35 @@ int board_late_init(void)
|
|||
/* board specific pmic init */
|
||||
pmic_init();
|
||||
|
||||
check_time();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Removes the 'eth[0-9]*addr' environment variable with the given index
|
||||
*
|
||||
* @param index [in] the index of the eth_device whose variable is to be removed
|
||||
*/
|
||||
static void remove_ethaddr_env_var(int index)
|
||||
{
|
||||
char env_var_name[9];
|
||||
|
||||
sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
|
||||
env_set(env_var_name, NULL);
|
||||
}
|
||||
|
||||
int last_stage_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Remove first three ethaddr which may have been created by
|
||||
* function process_vpd().
|
||||
*/
|
||||
for (i = 0; i < 3; ++i)
|
||||
remove_ethaddr_env_var(i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -13,6 +13,6 @@ config MX6Q
|
|||
default y
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/boundary/nitrogen6x/nitrogen6q2g.cfg"
|
||||
default "board/tbs/tbs2910/tbs2910.cfg"
|
||||
|
||||
endif
|
||||
|
|
115
board/tbs/tbs2910/tbs2910.cfg
Normal file
115
board/tbs/tbs2910/tbs2910.cfg
Normal file
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* Copyright (C) 2017 Soeren Moch <smoch@web.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include "asm/arch/crm_regs.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
|
||||
/* image version 2 for imx6 */
|
||||
IMAGE_VERSION 2
|
||||
BOOT_FROM sd
|
||||
|
||||
/* set the default clock gates to save power */
|
||||
DATA 4, CCM_CCGR0, 0x00C03F3F
|
||||
DATA 4, CCM_CCGR1, 0x0030FC03
|
||||
DATA 4, CCM_CCGR2, 0x0FFFC000
|
||||
DATA 4, CCM_CCGR3, 0x3FF00000
|
||||
DATA 4, CCM_CCGR4, 0x00FFF300
|
||||
DATA 4, CCM_CCGR5, 0x0F0000C3
|
||||
DATA 4, CCM_CCGR6, 0x000003FF
|
||||
/* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */
|
||||
DATA 4, CCM_CCOSR, 0x000000fb
|
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
|
||||
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
|
||||
DATA 4, MX6_IOMUXC_GPR6, 0x77177717
|
||||
DATA 4, MX6_IOMUXC_GPR7, 0x77177717
|
||||
|
||||
|
||||
/*
|
||||
* DDR3/DDR3L settings
|
||||
* use default 40 Ohm pad drive strength, no odt
|
||||
* 4x256Mx16 DDR3L-1066 7-7-7
|
||||
*/
|
||||
|
||||
/* disable dq pullup */
|
||||
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
||||
/* disable dqs pullup */
|
||||
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
|
||||
/* set ddr input mode for dq signals */
|
||||
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
||||
/* set ddr input mode for dqs signals */
|
||||
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
||||
/* set pad calibration type to DDR3 */
|
||||
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
|
||||
/* ZQ calibration */
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
||||
/* dqs write delay */
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f
|
||||
/* dqs read delay */
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
|
||||
/* dqs read gating control */
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300
|
||||
/* start delay line calibration */
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
/* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
|
||||
/* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
|
||||
/* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
||||
/* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
||||
/* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
|
||||
/* ODT timing */
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
|
||||
/* read odt settings, 120 Ohm */
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
|
||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
|
||||
/* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
|
||||
/* interleaved bank access (row/bank/col), 5 cycles additional read delay */
|
||||
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
|
||||
/* 2GiByte RAM at cs0 */
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
|
||||
/* load mode registers of external ddr chips */
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
/* externel chip ZQ calibration */
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
/* configure and start refreshes, 8 refresh commands at 32 kHz */
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
|
||||
/* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
|
||||
/* set automatic self refresh */
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
||||
/* controller configuration finished */
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
|
@ -15,7 +15,6 @@ CONFIG_CMD_GPIO=y
|
|||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
# CONFIG_CMD_NET is not set
|
||||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
|
@ -28,3 +27,9 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_CMD_NET=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_CMD_E1000=y
|
||||
CONFIG_FIT=y
|
||||
|
|
|
@ -15,7 +15,6 @@ CONFIG_CMD_GPIO=y
|
|||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
# CONFIG_CMD_NET is not set
|
||||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
|
@ -28,3 +27,9 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_CMD_NET=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_CMD_E1000=y
|
||||
CONFIG_FIT=y
|
||||
|
|
|
@ -13,9 +13,9 @@ CONFIG_CMD_BOOTZ=y
|
|||
# CONFIG_CMD_FPGA is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_RTC_RX8010SJ=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
# CONFIG_CMD_NET is not set
|
||||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
|
@ -28,3 +28,9 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_CMD_NET=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_CMD_E1000=y
|
||||
CONFIG_FIT=y
|
||||
|
|
49
configs/imx6qdl_icore_mipi_defconfig
Normal file
49
configs/imx6qdl_icore_mipi_defconfig
Normal file
|
@ -0,0 +1,49 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TARGET_MX6Q_ENGICAM=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
# CONFIG_CMD_BMODE is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_SIGNATURE=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_EXT_SUPPORT=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="icorem6qdl-mipi> "
|
||||
CONFIG_CRC32_VERIFY=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_LIST="imx6q-icore-mipi imx6dl-icore-mipi"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_DEBUG_UART_MXC=y
|
||||
CONFIG_DEBUG_UART_BASE=0x021f0000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_IMX_THERMAL=y
|
|
@ -34,9 +34,14 @@ CONFIG_CMD_EXT4=y
|
|||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel),1m(dtb),-(rootfs)"
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_OF_LIST="imx6q-icore imx6dl-icore"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_NAND_MXS=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_FEC_MXC=y
|
||||
|
|
|
@ -8,26 +8,35 @@ CONFIG_SPL_SERIAL_SUPPORT=y
|
|||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL"
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_USB_HOST_SUPPORT=y
|
||||
CONFIG_SPL_USB_GADGET_SUPPORT=y
|
||||
CONFIG_SPL_USBETH_SUPPORT=y
|
||||
CONFIG_SPL_USB_SDP_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_MMC is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_BOOTM is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_SAVEENV is not set
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
# CONFIG_CMD_NET is not set
|
||||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_REGEX=y
|
||||
|
|
|
@ -20,6 +20,12 @@ CONFIG_SPL_USB_HOST_SUPPORT=y
|
|||
CONFIG_SPL_USB_GADGET_SUPPORT=y
|
||||
CONFIG_SPL_USB_SDP_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
|
||||
CONFIG_FASTBOOT_USB_DEV=0
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_SPL=y
|
||||
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
|
||||
|
@ -32,6 +38,7 @@ CONFIG_CMD_PCI=y
|
|||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_SDP=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
|
|
|
@ -41,6 +41,9 @@ CONFIG_DM_GPIO=y
|
|||
CONFIG_DM_74X164=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -43,6 +43,9 @@ CONFIG_DM_GPIO=y
|
|||
CONFIG_DM_74X164=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -68,13 +68,10 @@ the CSF file.
|
|||
|
||||
The DEK blob is generated by an authenticated U-Boot image with
|
||||
the dek_blob cmd enabled. The image used for DEK blob generation
|
||||
needs to have the following configurations enabled:
|
||||
needs to have the following configurations enabled in Kconfig:
|
||||
|
||||
CONFIG_SECURE_BOOT
|
||||
CONFIG_SYS_FSL_SEC_COMPAT 4 /* HAB version */
|
||||
CONFIG_FSL_CAAM
|
||||
CONFIG_CMD_DEKBLOB
|
||||
CONFIG_SYS_FSL_SEC_LE
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_CMD_DEKBLOB=y
|
||||
|
||||
Note: The encrypted boot feature is only supported by HABv4 or
|
||||
greater.
|
||||
|
|
|
@ -566,6 +566,8 @@ int sec_init_idx(uint8_t sec_idx)
|
|||
{
|
||||
ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
|
||||
uint32_t mcr = sec_in32(&sec->mcfgr);
|
||||
uint32_t jrown_ns;
|
||||
int i;
|
||||
int ret = 0;
|
||||
|
||||
#ifdef CONFIG_FSL_CORENET
|
||||
|
@ -621,6 +623,13 @@ int sec_init_idx(uint8_t sec_idx)
|
|||
#endif
|
||||
#endif
|
||||
|
||||
/* Set ownership of job rings to non-TrustZone mode by default */
|
||||
for (i = 0; i < ARRAY_SIZE(sec->jrliodnr); i++) {
|
||||
jrown_ns = sec_in32(&sec->jrliodnr[i].ms);
|
||||
jrown_ns |= JROWN_NS | JRMID_NS;
|
||||
sec_out32(&sec->jrliodnr[i].ms, jrown_ns);
|
||||
}
|
||||
|
||||
ret = jr_init(sec_idx);
|
||||
if (ret < 0) {
|
||||
printf("SEC initialization failed\n");
|
||||
|
|
|
@ -34,6 +34,8 @@
|
|||
#define JRNSLIODN_MASK 0x0fff0000
|
||||
#define JRSLIODN_SHIFT 0
|
||||
#define JRSLIODN_MASK 0x00000fff
|
||||
#define JROWN_NS 0x00000008
|
||||
#define JRMID_NS 0x00000001
|
||||
|
||||
#define JQ_DEQ_ERR -1
|
||||
#define JQ_DEQ_TO_ERR -2
|
||||
|
|
|
@ -41,13 +41,13 @@ static unsigned long gpio_ports[] = {
|
|||
[2] = GPIO3_BASE_ADDR,
|
||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
|
||||
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
|
||||
defined(CONFIG_MX7)
|
||||
defined(CONFIG_MX7) || defined(CONFIG_MX8M)
|
||||
[3] = GPIO4_BASE_ADDR,
|
||||
#endif
|
||||
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
|
||||
defined(CONFIG_MX7)
|
||||
defined(CONFIG_MX7) || defined(CONFIG_MX8M)
|
||||
[4] = GPIO5_BASE_ADDR,
|
||||
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
|
||||
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M))
|
||||
[5] = GPIO6_BASE_ADDR,
|
||||
#endif
|
||||
#endif
|
||||
|
@ -349,13 +349,17 @@ static const struct mxc_gpio_plat mxc_plat[] = {
|
|||
{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
|
||||
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
|
||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
|
||||
defined(CONFIG_MX53) || defined(CONFIG_MX6)
|
||||
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
|
||||
defined(CONFIG_MX8M)
|
||||
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
|
||||
#endif
|
||||
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
|
||||
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
|
||||
defined(CONFIG_MX8M)
|
||||
{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
|
||||
#ifndef CONFIG_MX8M
|
||||
{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
|
||||
#endif
|
||||
#endif
|
||||
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
|
||||
{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
|
||||
#endif
|
||||
|
@ -366,13 +370,17 @@ U_BOOT_DEVICES(mxc_gpios) = {
|
|||
{ "gpio_mxc", &mxc_plat[1] },
|
||||
{ "gpio_mxc", &mxc_plat[2] },
|
||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
|
||||
defined(CONFIG_MX53) || defined(CONFIG_MX6)
|
||||
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
|
||||
defined(CONFIG_MX8M)
|
||||
{ "gpio_mxc", &mxc_plat[3] },
|
||||
#endif
|
||||
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
|
||||
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
|
||||
defined(CONFIG_MX8M)
|
||||
{ "gpio_mxc", &mxc_plat[4] },
|
||||
#ifndef CONFIG_MX8M
|
||||
{ "gpio_mxc", &mxc_plat[5] },
|
||||
#endif
|
||||
#endif
|
||||
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
|
||||
{ "gpio_mxc", &mxc_plat[6] },
|
||||
#endif
|
||||
|
|
|
@ -35,6 +35,8 @@
|
|||
#define BM_OUT_STATUS_DED 0x00000400
|
||||
#define BM_OUT_STATUS_LOCKED 0x00000800
|
||||
#define BM_OUT_STATUS_PROGFAIL 0x00001000
|
||||
#elif defined(CONFIG_MX8M)
|
||||
#define BM_CTRL_ADDR 0x000000ff
|
||||
#else
|
||||
#define BM_CTRL_ADDR 0x0000007f
|
||||
#endif
|
||||
|
@ -79,6 +81,9 @@
|
|||
#elif defined(CONFIG_MX7ULP)
|
||||
#define FUSE_BANK_SIZE 0x80
|
||||
#define FUSE_BANKS 31
|
||||
#elif defined(CONFIG_MX8M)
|
||||
#define FUSE_BANK_SIZE 0x40
|
||||
#define FUSE_BANKS 64
|
||||
#else
|
||||
#error "Unsupported architecture\n"
|
||||
#endif
|
||||
|
@ -294,6 +299,8 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
|
|||
u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
|
||||
#ifdef CONFIG_MX7
|
||||
u32 addr = bank;
|
||||
#elif defined CONFIG_MX8M
|
||||
u32 addr = bank << 2 | word;
|
||||
#else
|
||||
u32 addr;
|
||||
/* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <dm.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <dm/pinctrl.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -32,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
|
||||
IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
|
||||
IRQSTATEN_DINT)
|
||||
#define MAX_TUNING_LOOP 40
|
||||
|
||||
struct fsl_esdhc {
|
||||
uint dsaddr; /* SDMA system address register */
|
||||
|
@ -61,23 +63,27 @@ struct fsl_esdhc {
|
|||
uint dllctrl;
|
||||
uint dllstat;
|
||||
uint clktunectrlstatus;
|
||||
char reserved3[84];
|
||||
char reserved3[4];
|
||||
uint strobe_dllctrl;
|
||||
uint strobe_dllstat;
|
||||
char reserved4[72];
|
||||
uint vendorspec;
|
||||
uint mmcboot;
|
||||
uint vendorspec2;
|
||||
char reserved4[48];
|
||||
uint tuning_ctrl; /* on i.MX6/7/8 */
|
||||
char reserved5[44];
|
||||
uint hostver; /* Host controller version register */
|
||||
char reserved5[4]; /* reserved */
|
||||
uint dmaerraddr; /* DMA error address register */
|
||||
char reserved6[4]; /* reserved */
|
||||
uint dmaerrattr; /* DMA error attribute register */
|
||||
uint dmaerraddr; /* DMA error address register */
|
||||
char reserved7[4]; /* reserved */
|
||||
uint dmaerrattr; /* DMA error attribute register */
|
||||
char reserved8[4]; /* reserved */
|
||||
uint hostcapblt2; /* Host controller capabilities register 2 */
|
||||
char reserved8[8]; /* reserved */
|
||||
char reserved9[8]; /* reserved */
|
||||
uint tcr; /* Tuning control register */
|
||||
char reserved9[28]; /* reserved */
|
||||
char reserved10[28]; /* reserved */
|
||||
uint sddirctl; /* SD direction control register */
|
||||
char reserved10[712];/* reserved */
|
||||
char reserved11[712];/* reserved */
|
||||
uint scr; /* eSDHC control register */
|
||||
};
|
||||
|
||||
|
@ -86,6 +92,11 @@ struct fsl_esdhc_plat {
|
|||
struct mmc mmc;
|
||||
};
|
||||
|
||||
struct esdhc_soc_data {
|
||||
u32 flags;
|
||||
u32 caps;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fsl_esdhc_priv
|
||||
*
|
||||
|
@ -99,12 +110,20 @@ struct fsl_esdhc_plat {
|
|||
* @non_removable: 0: removable; 1: non-removable
|
||||
* @wp_enable: 1: enable checking wp; 0: no check
|
||||
* @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
|
||||
* @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
|
||||
* @caps: controller capabilities
|
||||
* @tuning_step: tuning step setting in tuning_ctrl register
|
||||
* @start_tuning_tap: the start point for tuning in tuning_ctrl register
|
||||
* @strobe_dll_delay_target: settings in strobe_dllctrl
|
||||
* @signal_voltage: indicating the current voltage
|
||||
* @cd_gpio: gpio for card detection
|
||||
* @wp_gpio: gpio for write protection
|
||||
*/
|
||||
struct fsl_esdhc_priv {
|
||||
struct fsl_esdhc *esdhc_regs;
|
||||
unsigned int sdhc_clk;
|
||||
unsigned int clock;
|
||||
unsigned int mode;
|
||||
unsigned int bus_width;
|
||||
#if !CONFIG_IS_ENABLED(BLK)
|
||||
struct mmc *mmc;
|
||||
|
@ -113,6 +132,16 @@ struct fsl_esdhc_priv {
|
|||
int non_removable;
|
||||
int wp_enable;
|
||||
int vs18_enable;
|
||||
u32 flags;
|
||||
u32 caps;
|
||||
u32 tuning_step;
|
||||
u32 tuning_start_tap;
|
||||
u32 strobe_dll_delay_target;
|
||||
u32 signal_voltage;
|
||||
#if IS_ENABLED(CONFIG_DM_REGULATOR)
|
||||
struct udevice *vqmmc_dev;
|
||||
struct udevice *vmmc_dev;
|
||||
#endif
|
||||
#ifdef CONFIG_DM_GPIO
|
||||
struct gpio_desc cd_gpio;
|
||||
struct gpio_desc wp_gpio;
|
||||
|
@ -228,7 +257,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|||
{
|
||||
int timeout;
|
||||
struct fsl_esdhc *regs = priv->esdhc_regs;
|
||||
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
|
||||
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
|
||||
defined(CONFIG_MX8M)
|
||||
dma_addr_t addr;
|
||||
#endif
|
||||
uint wml_value;
|
||||
|
@ -241,7 +271,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|||
|
||||
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
|
||||
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
|
||||
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
|
||||
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
|
||||
defined(CONFIG_MX8M)
|
||||
addr = virt_to_phys((void *)(data->dest));
|
||||
if (upper_32_bits(addr))
|
||||
printf("Error found for upper 32 bits\n");
|
||||
|
@ -270,7 +301,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|||
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
|
||||
wml_value << 16);
|
||||
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
|
||||
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
|
||||
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
|
||||
defined(CONFIG_MX8M)
|
||||
addr = virt_to_phys((void *)(data->src));
|
||||
if (upper_32_bits(addr))
|
||||
printf("Error found for upper 32 bits\n");
|
||||
|
@ -335,7 +367,8 @@ static void check_and_invalidate_dcache_range
|
|||
unsigned end = 0;
|
||||
unsigned size = roundup(ARCH_DMA_MINALIGN,
|
||||
data->blocks*data->blocksize);
|
||||
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
|
||||
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
|
||||
defined(CONFIG_MX8M)
|
||||
dma_addr_t addr;
|
||||
|
||||
addr = virt_to_phys((void *)(data->dest));
|
||||
|
@ -360,6 +393,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|||
int err = 0;
|
||||
uint xfertyp;
|
||||
uint irqstat;
|
||||
u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
|
||||
struct fsl_esdhc *regs = priv->esdhc_regs;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
|
@ -413,8 +447,12 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|||
esdhc_write32(®s->xfertyp, xfertyp);
|
||||
#endif
|
||||
|
||||
if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
|
||||
(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
|
||||
flags = IRQSTAT_BRR;
|
||||
|
||||
/* Wait for the command to complete */
|
||||
while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
|
||||
while (!(esdhc_read32(®s->irqstat) & flags))
|
||||
;
|
||||
|
||||
irqstat = esdhc_read32(®s->irqstat);
|
||||
|
@ -476,6 +514,12 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|||
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
|
||||
esdhc_pio_read_write(priv, data);
|
||||
#else
|
||||
flags = DATA_COMPLETE;
|
||||
if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
|
||||
(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
|
||||
flags = IRQSTAT_BRR;
|
||||
}
|
||||
|
||||
do {
|
||||
irqstat = esdhc_read32(®s->irqstat);
|
||||
|
||||
|
@ -488,7 +532,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|||
err = -ECOMM;
|
||||
goto out;
|
||||
}
|
||||
} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
|
||||
} while ((irqstat & flags) != flags);
|
||||
|
||||
/*
|
||||
* Need invalidate the dcache here again to avoid any
|
||||
|
@ -574,6 +618,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
|
|||
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
|
||||
#endif
|
||||
|
||||
priv->clock = clock;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
||||
|
@ -605,9 +650,239 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef MMC_SUPPORTS_TUNING
|
||||
static int esdhc_change_pinstate(struct udevice *dev)
|
||||
{
|
||||
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
switch (priv->mode) {
|
||||
case UHS_SDR50:
|
||||
case UHS_DDR50:
|
||||
ret = pinctrl_select_state(dev, "state_100mhz");
|
||||
break;
|
||||
case UHS_SDR104:
|
||||
case MMC_HS_200:
|
||||
ret = pinctrl_select_state(dev, "state_200mhz");
|
||||
break;
|
||||
default:
|
||||
ret = pinctrl_select_state(dev, "default");
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret)
|
||||
printf("%s %d error\n", __func__, priv->mode);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void esdhc_reset_tuning(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
|
||||
struct fsl_esdhc *regs = priv->esdhc_regs;
|
||||
|
||||
if (priv->flags & ESDHC_FLAG_USDHC) {
|
||||
if (priv->flags & ESDHC_FLAG_STD_TUNING) {
|
||||
esdhc_clrbits32(®s->autoc12err,
|
||||
MIX_CTRL_SMPCLK_SEL |
|
||||
MIX_CTRL_EXE_TUNE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int esdhc_set_timing(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
|
||||
struct fsl_esdhc *regs = priv->esdhc_regs;
|
||||
u32 mixctrl;
|
||||
|
||||
mixctrl = readl(®s->mixctrl);
|
||||
mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
|
||||
|
||||
switch (mmc->selected_mode) {
|
||||
case MMC_LEGACY:
|
||||
case SD_LEGACY:
|
||||
esdhc_reset_tuning(mmc);
|
||||
break;
|
||||
case MMC_HS:
|
||||
case MMC_HS_52:
|
||||
case MMC_HS_200:
|
||||
case SD_HS:
|
||||
case UHS_SDR12:
|
||||
case UHS_SDR25:
|
||||
case UHS_SDR50:
|
||||
case UHS_SDR104:
|
||||
writel(mixctrl, ®s->mixctrl);
|
||||
break;
|
||||
case UHS_DDR50:
|
||||
case MMC_DDR_52:
|
||||
mixctrl |= MIX_CTRL_DDREN;
|
||||
writel(mixctrl, ®s->mixctrl);
|
||||
break;
|
||||
default:
|
||||
printf("Not supported %d\n", mmc->selected_mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv->mode = mmc->selected_mode;
|
||||
|
||||
return esdhc_change_pinstate(mmc->dev);
|
||||
}
|
||||
|
||||
static int esdhc_set_voltage(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
|
||||
struct fsl_esdhc *regs = priv->esdhc_regs;
|
||||
int ret;
|
||||
|
||||
priv->signal_voltage = mmc->signal_voltage;
|
||||
switch (mmc->signal_voltage) {
|
||||
case MMC_SIGNAL_VOLTAGE_330:
|
||||
if (priv->vs18_enable)
|
||||
return -EIO;
|
||||
#ifdef CONFIG_DM_REGULATOR
|
||||
if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
|
||||
ret = regulator_set_value(priv->vqmmc_dev, 3300000);
|
||||
if (ret) {
|
||||
printf("Setting to 3.3V error");
|
||||
return -EIO;
|
||||
}
|
||||
/* Wait for 5ms */
|
||||
mdelay(5);
|
||||
}
|
||||
#endif
|
||||
|
||||
esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
|
||||
if (!(esdhc_read32(®s->vendorspec) &
|
||||
ESDHC_VENDORSPEC_VSELECT))
|
||||
return 0;
|
||||
|
||||
return -EAGAIN;
|
||||
case MMC_SIGNAL_VOLTAGE_180:
|
||||
#ifdef CONFIG_DM_REGULATOR
|
||||
if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
|
||||
ret = regulator_set_value(priv->vqmmc_dev, 1800000);
|
||||
if (ret) {
|
||||
printf("Setting to 1.8V error");
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
|
||||
if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
|
||||
return 0;
|
||||
|
||||
return -EAGAIN;
|
||||
case MMC_SIGNAL_VOLTAGE_120:
|
||||
return -ENOTSUPP;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void esdhc_stop_tuning(struct mmc *mmc)
|
||||
{
|
||||
struct mmc_cmd cmd;
|
||||
|
||||
cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
|
||||
cmd.cmdarg = 0;
|
||||
cmd.resp_type = MMC_RSP_R1b;
|
||||
|
||||
dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
|
||||
}
|
||||
|
||||
static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
|
||||
{
|
||||
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
|
||||
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
||||
struct fsl_esdhc *regs = priv->esdhc_regs;
|
||||
struct mmc *mmc = &plat->mmc;
|
||||
u32 irqstaten = readl(®s->irqstaten);
|
||||
u32 irqsigen = readl(®s->irqsigen);
|
||||
int i, ret = -ETIMEDOUT;
|
||||
u32 val, mixctrl;
|
||||
|
||||
/* clock tuning is not needed for upto 52MHz */
|
||||
if (mmc->clock <= 52000000)
|
||||
return 0;
|
||||
|
||||
/* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
|
||||
if (priv->flags & ESDHC_FLAG_STD_TUNING) {
|
||||
val = readl(®s->autoc12err);
|
||||
mixctrl = readl(®s->mixctrl);
|
||||
val &= ~MIX_CTRL_SMPCLK_SEL;
|
||||
mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
|
||||
|
||||
val |= MIX_CTRL_EXE_TUNE;
|
||||
mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
|
||||
|
||||
writel(val, ®s->autoc12err);
|
||||
writel(mixctrl, ®s->mixctrl);
|
||||
}
|
||||
|
||||
/* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
|
||||
mixctrl = readl(®s->mixctrl);
|
||||
mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
|
||||
writel(mixctrl, ®s->mixctrl);
|
||||
|
||||
writel(IRQSTATEN_BRR, ®s->irqstaten);
|
||||
writel(IRQSTATEN_BRR, ®s->irqsigen);
|
||||
|
||||
/*
|
||||
* Issue opcode repeatedly till Execute Tuning is set to 0 or the number
|
||||
* of loops reaches 40 times.
|
||||
*/
|
||||
for (i = 0; i < MAX_TUNING_LOOP; i++) {
|
||||
u32 ctrl;
|
||||
|
||||
if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
|
||||
if (mmc->bus_width == 8)
|
||||
writel(0x7080, ®s->blkattr);
|
||||
else if (mmc->bus_width == 4)
|
||||
writel(0x7040, ®s->blkattr);
|
||||
} else {
|
||||
writel(0x7040, ®s->blkattr);
|
||||
}
|
||||
|
||||
/* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
|
||||
val = readl(®s->mixctrl);
|
||||
val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
|
||||
writel(val, ®s->mixctrl);
|
||||
|
||||
/* We are using STD tuning, no need to check return value */
|
||||
mmc_send_tuning(mmc, opcode, NULL);
|
||||
|
||||
ctrl = readl(®s->autoc12err);
|
||||
if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
|
||||
(ctrl & MIX_CTRL_SMPCLK_SEL)) {
|
||||
/*
|
||||
* need to wait some time, make sure sd/mmc fininsh
|
||||
* send out tuning data, otherwise, the sd/mmc can't
|
||||
* response to any command when the card still out
|
||||
* put the tuning data.
|
||||
*/
|
||||
mdelay(1);
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Add 1ms delay for SD and eMMC */
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
writel(irqstaten, ®s->irqstaten);
|
||||
writel(irqsigen, ®s->irqsigen);
|
||||
|
||||
esdhc_stop_tuning(mmc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc *regs = priv->esdhc_regs;
|
||||
int ret __maybe_unused;
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
||||
/* Select to use peripheral clock */
|
||||
|
@ -616,7 +891,41 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
|
|||
esdhc_clock_control(priv, true);
|
||||
#endif
|
||||
/* Set the clock speed */
|
||||
set_sysctl(priv, mmc, mmc->clock);
|
||||
if (priv->clock != mmc->clock)
|
||||
set_sysctl(priv, mmc, mmc->clock);
|
||||
|
||||
#ifdef MMC_SUPPORTS_TUNING
|
||||
if (mmc->clk_disable) {
|
||||
#ifdef CONFIG_FSL_USDHC
|
||||
esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
|
||||
#else
|
||||
esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
|
||||
#endif
|
||||
} else {
|
||||
#ifdef CONFIG_FSL_USDHC
|
||||
esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
|
||||
VENDORSPEC_CKEN);
|
||||
#else
|
||||
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
|
||||
#endif
|
||||
}
|
||||
|
||||
if (priv->mode != mmc->selected_mode) {
|
||||
ret = esdhc_set_timing(mmc);
|
||||
if (ret) {
|
||||
printf("esdhc_set_timing error %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (priv->signal_voltage != mmc->signal_voltage) {
|
||||
ret = esdhc_set_voltage(mmc);
|
||||
if (ret) {
|
||||
printf("esdhc_set_voltage error %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set the bus width */
|
||||
esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
|
||||
|
@ -791,6 +1100,10 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
|
|||
#ifndef CONFIG_FSL_USDHC
|
||||
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
|
||||
| SYSCTL_IPGEN | SYSCTL_CKEN);
|
||||
/* Clearing tuning bits in case ROM has set it already */
|
||||
esdhc_write32(®s->mixctrl, 0);
|
||||
esdhc_write32(®s->autoc12err, 0);
|
||||
esdhc_write32(®s->clktunectrlstatus, 0);
|
||||
#else
|
||||
esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
|
||||
VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
|
||||
|
@ -864,11 +1177,27 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
|
|||
cfg->host_caps &= ~MMC_MODE_8BIT;
|
||||
#endif
|
||||
|
||||
cfg->host_caps |= priv->caps;
|
||||
|
||||
cfg->f_min = 400000;
|
||||
cfg->f_max = min(priv->sdhc_clk, (u32)52000000);
|
||||
cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
|
||||
|
||||
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
||||
|
||||
writel(0, ®s->dllctrl);
|
||||
if (priv->flags & ESDHC_FLAG_USDHC) {
|
||||
if (priv->flags & ESDHC_FLAG_STD_TUNING) {
|
||||
u32 val = readl(®s->tuning_ctrl);
|
||||
|
||||
val |= ESDHC_STD_TUNING_EN;
|
||||
val &= ~ESDHC_TUNING_START_TAP_MASK;
|
||||
val |= priv->tuning_start_tap;
|
||||
val &= ~ESDHC_TUNING_STEP_MASK;
|
||||
val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
|
||||
writel(val, ®s->tuning_ctrl);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -1027,6 +1356,10 @@ static int fsl_esdhc_probe(struct udevice *dev)
|
|||
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
||||
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
|
||||
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
||||
const void *fdt = gd->fdt_blob;
|
||||
int node = dev_of_offset(dev);
|
||||
struct esdhc_soc_data *data =
|
||||
(struct esdhc_soc_data *)dev_get_driver_data(dev);
|
||||
#ifdef CONFIG_DM_REGULATOR
|
||||
struct udevice *vqmmc_dev;
|
||||
#endif
|
||||
|
@ -1041,6 +1374,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
|
|||
|
||||
priv->esdhc_regs = (struct fsl_esdhc *)addr;
|
||||
priv->dev = dev;
|
||||
priv->mode = -1;
|
||||
if (data) {
|
||||
priv->flags = data->flags;
|
||||
priv->caps = data->caps;
|
||||
}
|
||||
|
||||
val = dev_read_u32_default(dev, "bus-width", -1);
|
||||
if (val == 8)
|
||||
|
@ -1050,6 +1388,15 @@ static int fsl_esdhc_probe(struct udevice *dev)
|
|||
else
|
||||
priv->bus_width = 1;
|
||||
|
||||
val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
|
||||
priv->tuning_step = val;
|
||||
val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
|
||||
ESDHC_TUNING_START_TAP_DEFAULT);
|
||||
priv->tuning_start_tap = val;
|
||||
val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
|
||||
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
|
||||
priv->strobe_dll_delay_target = val;
|
||||
|
||||
if (dev_read_bool(dev, "non-removable")) {
|
||||
priv->non_removable = 1;
|
||||
} else {
|
||||
|
@ -1091,6 +1438,9 @@ static int fsl_esdhc_probe(struct udevice *dev)
|
|||
}
|
||||
#endif
|
||||
|
||||
if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
|
||||
priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200);
|
||||
|
||||
/*
|
||||
* TODO:
|
||||
* Because lack of clk driver, if SDHC clk is not enabled,
|
||||
|
@ -1163,15 +1513,26 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
|
|||
.get_cd = fsl_esdhc_get_cd,
|
||||
.send_cmd = fsl_esdhc_send_cmd,
|
||||
.set_ios = fsl_esdhc_set_ios,
|
||||
#ifdef MMC_SUPPORTS_TUNING
|
||||
.execute_tuning = fsl_esdhc_execute_tuning,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct esdhc_soc_data usdhc_imx7d_data = {
|
||||
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
|
||||
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
|
||||
| ESDHC_FLAG_HS400,
|
||||
.caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
|
||||
MMC_MODE_HS_52MHz | MMC_MODE_HS,
|
||||
};
|
||||
|
||||
static const struct udevice_id fsl_esdhc_ids[] = {
|
||||
{ .compatible = "fsl,imx6ul-usdhc", },
|
||||
{ .compatible = "fsl,imx6sx-usdhc", },
|
||||
{ .compatible = "fsl,imx6sl-usdhc", },
|
||||
{ .compatible = "fsl,imx6q-usdhc", },
|
||||
{ .compatible = "fsl,imx7d-usdhc", },
|
||||
{ .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
|
||||
{ .compatible = "fsl,imx7ulp-usdhc", },
|
||||
{ .compatible = "fsl,esdhc", },
|
||||
{ /* sentinel */ }
|
||||
|
|
|
@ -150,6 +150,7 @@ static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
|
|||
|
||||
#ifndef CONFIG_E1000_NO_NVM
|
||||
static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
|
||||
static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
|
||||
static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
|
||||
uint16_t words,
|
||||
uint16_t *data);
|
||||
|
@ -861,6 +862,174 @@ e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
|
|||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_DM_ETH
|
||||
/******************************************************************************
|
||||
* e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
|
||||
* @hw: pointer to the HW structure
|
||||
* @offset: offset within the Shadow Ram to be written to
|
||||
* @words: number of words to write
|
||||
* @data: 16 bit word(s) to be written to the Shadow Ram
|
||||
*
|
||||
* Writes data to Shadow Ram at offset using EEWR register.
|
||||
*
|
||||
* If e1000_update_eeprom_checksum_i210 is not called after this function, the
|
||||
* Shadow Ram will most likely contain an invalid checksum.
|
||||
*****************************************************************************/
|
||||
static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
|
||||
uint16_t words, uint16_t *data)
|
||||
{
|
||||
struct e1000_eeprom_info *eeprom = &hw->eeprom;
|
||||
uint32_t i, k, eewr = 0;
|
||||
uint32_t attempts = 100000;
|
||||
int32_t ret_val = 0;
|
||||
|
||||
/* A check for invalid values: offset too large, too many words,
|
||||
* too many words for the offset, and not enough words.
|
||||
*/
|
||||
if ((offset >= eeprom->word_size) ||
|
||||
(words > (eeprom->word_size - offset)) || (words == 0)) {
|
||||
DEBUGOUT("nvm parameter(s) out of bounds\n");
|
||||
ret_val = -E1000_ERR_EEPROM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < words; i++) {
|
||||
eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
|
||||
| (data[i] << E1000_EEPROM_RW_REG_DATA) |
|
||||
E1000_EEPROM_RW_REG_START;
|
||||
|
||||
E1000_WRITE_REG(hw, I210_EEWR, eewr);
|
||||
|
||||
for (k = 0; k < attempts; k++) {
|
||||
if (E1000_EEPROM_RW_REG_DONE &
|
||||
E1000_READ_REG(hw, I210_EEWR)) {
|
||||
ret_val = 0;
|
||||
break;
|
||||
}
|
||||
udelay(5);
|
||||
}
|
||||
|
||||
if (ret_val) {
|
||||
DEBUGOUT("Shadow RAM write EEWR timed out\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
*****************************************************************************/
|
||||
static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
|
||||
{
|
||||
int32_t ret_val = -E1000_ERR_EEPROM;
|
||||
uint32_t i, reg;
|
||||
|
||||
for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
|
||||
reg = E1000_READ_REG(hw, EECD);
|
||||
if (reg & E1000_EECD_FLUDONE_I210) {
|
||||
ret_val = 0;
|
||||
break;
|
||||
}
|
||||
udelay(5);
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* e1000_update_flash_i210 - Commit EEPROM to the flash
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
*****************************************************************************/
|
||||
static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
|
||||
{
|
||||
int32_t ret_val = 0;
|
||||
uint32_t flup;
|
||||
|
||||
ret_val = e1000_pool_flash_update_done_i210(hw);
|
||||
if (ret_val == -E1000_ERR_EEPROM) {
|
||||
DEBUGOUT("Flash update time out\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
|
||||
E1000_WRITE_REG(hw, EECD, flup);
|
||||
|
||||
ret_val = e1000_pool_flash_update_done_i210(hw);
|
||||
if (ret_val)
|
||||
DEBUGOUT("Flash update time out\n");
|
||||
else
|
||||
DEBUGOUT("Flash update complete\n");
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Updates the EEPROM checksum by reading/adding each word of the EEPROM
|
||||
* up to the checksum. Then calculates the EEPROM checksum and writes the
|
||||
* value to the EEPROM. Next commit EEPROM data onto the Flash.
|
||||
*****************************************************************************/
|
||||
static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
|
||||
{
|
||||
int32_t ret_val = 0;
|
||||
uint16_t checksum = 0;
|
||||
uint16_t i, nvm_data;
|
||||
|
||||
/* Read the first word from the EEPROM. If this times out or fails, do
|
||||
* not continue or we could be in for a very long wait while every
|
||||
* EEPROM read fails
|
||||
*/
|
||||
ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
|
||||
if (ret_val) {
|
||||
DEBUGOUT("EEPROM read failed\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (!(e1000_get_hw_eeprom_semaphore(hw))) {
|
||||
/* Do not use hw->nvm.ops.write, hw->nvm.ops.read
|
||||
* because we do not want to take the synchronization
|
||||
* semaphores twice here.
|
||||
*/
|
||||
|
||||
for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
|
||||
ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
|
||||
if (ret_val) {
|
||||
e1000_put_hw_eeprom_semaphore(hw);
|
||||
DEBUGOUT("EEPROM Read Error while updating checksum.\n");
|
||||
goto out;
|
||||
}
|
||||
checksum += nvm_data;
|
||||
}
|
||||
checksum = (uint16_t)EEPROM_SUM - checksum;
|
||||
ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
|
||||
&checksum);
|
||||
if (ret_val) {
|
||||
e1000_put_hw_eeprom_semaphore(hw);
|
||||
DEBUGOUT("EEPROM Write Error while updating checksum.\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
e1000_put_hw_eeprom_semaphore(hw);
|
||||
|
||||
ret_val = e1000_update_flash_i210(hw);
|
||||
} else {
|
||||
ret_val = -E1000_ERR_SWFW_SYNC;
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
* Verifies that the EEPROM has a valid checksum
|
||||
*
|
||||
|
@ -970,7 +1139,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
|
|||
|
||||
DEBUGFUNC();
|
||||
|
||||
if (hw->mac_type != e1000_80003es2lan)
|
||||
if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
|
||||
return E1000_SUCCESS;
|
||||
|
||||
while (timeout) {
|
||||
|
@ -1044,7 +1213,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
|
|||
if (!hw->eeprom_semaphore_present)
|
||||
return E1000_SUCCESS;
|
||||
|
||||
if (hw->mac_type == e1000_80003es2lan) {
|
||||
if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
|
||||
/* Get the SW semaphore. */
|
||||
if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
|
||||
return -E1000_ERR_EEPROM;
|
||||
|
@ -1144,33 +1313,21 @@ static bool e1000_is_second_port(struct e1000_hw *hw)
|
|||
|
||||
#ifndef CONFIG_E1000_NO_NVM
|
||||
/******************************************************************************
|
||||
* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
|
||||
* second function of dual function devices
|
||||
* Reads the adapter's MAC address from the EEPROM
|
||||
*
|
||||
* nic - Struct containing variables accessed by shared code
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* enetaddr - buffering where the MAC address will be stored
|
||||
*****************************************************************************/
|
||||
static int
|
||||
e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
|
||||
static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
|
||||
unsigned char enetaddr[6])
|
||||
{
|
||||
uint16_t offset;
|
||||
uint16_t eeprom_data;
|
||||
uint32_t reg_data = 0;
|
||||
int i;
|
||||
|
||||
DEBUGFUNC();
|
||||
|
||||
for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
|
||||
offset = i >> 1;
|
||||
if (hw->mac_type == e1000_igb) {
|
||||
/* i210 preloads MAC address into RAL/RAH registers */
|
||||
if (offset == 0)
|
||||
reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
|
||||
else if (offset == 1)
|
||||
reg_data >>= 16;
|
||||
else if (offset == 2)
|
||||
reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
|
||||
eeprom_data = reg_data & 0xffff;
|
||||
} else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
|
||||
if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
|
||||
DEBUGOUT("EEPROM Read Error\n");
|
||||
return -E1000_ERR_EEPROM;
|
||||
}
|
||||
|
@ -1178,6 +1335,63 @@ e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
|
|||
enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Reads the adapter's MAC address from the RAL/RAH registers
|
||||
*
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* enetaddr - buffering where the MAC address will be stored
|
||||
*****************************************************************************/
|
||||
static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
|
||||
unsigned char enetaddr[6])
|
||||
{
|
||||
uint16_t offset, tmp;
|
||||
uint32_t reg_data = 0;
|
||||
int i;
|
||||
|
||||
if (hw->mac_type != e1000_igb)
|
||||
return -E1000_ERR_MAC_TYPE;
|
||||
|
||||
for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
|
||||
offset = i >> 1;
|
||||
|
||||
if (offset == 0)
|
||||
reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
|
||||
else if (offset == 1)
|
||||
reg_data >>= 16;
|
||||
else if (offset == 2)
|
||||
reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
|
||||
tmp = reg_data & 0xffff;
|
||||
|
||||
enetaddr[i] = tmp & 0xff;
|
||||
enetaddr[i + 1] = (tmp >> 8) & 0xff;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
|
||||
* second function of dual function devices
|
||||
*
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* enetaddr - buffering where the MAC address will be stored
|
||||
*****************************************************************************/
|
||||
static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
|
||||
{
|
||||
int ret_val;
|
||||
|
||||
if (hw->mac_type == e1000_igb) {
|
||||
/* i210 preloads MAC address into RAL/RAH registers */
|
||||
ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
|
||||
} else {
|
||||
ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
|
||||
}
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
/* Invert the last bit if this is the second device */
|
||||
if (e1000_is_second_port(hw))
|
||||
enetaddr[5] ^= 1;
|
||||
|
@ -5435,6 +5649,45 @@ e1000_poll(struct eth_device *nic)
|
|||
return len ? 1 : 0;
|
||||
}
|
||||
|
||||
static int e1000_write_hwaddr(struct eth_device *dev)
|
||||
{
|
||||
#ifndef CONFIG_E1000_NO_NVM
|
||||
unsigned char *mac = dev->enetaddr;
|
||||
unsigned char current_mac[6];
|
||||
struct e1000_hw *hw = dev->priv;
|
||||
uint16_t data[3];
|
||||
int ret_val, i;
|
||||
|
||||
DEBUGOUT("%s: mac=%pM\n", __func__, mac);
|
||||
|
||||
memset(current_mac, 0, 6);
|
||||
|
||||
/* Read from EEPROM, not from registers, to make sure
|
||||
* the address is persistently configured
|
||||
*/
|
||||
ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
|
||||
DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
|
||||
|
||||
/* Only write to EEPROM if the given address is different or
|
||||
* reading the current address failed
|
||||
*/
|
||||
if (!ret_val && memcmp(current_mac, mac, 6) == 0)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < 3; ++i)
|
||||
data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
|
||||
|
||||
ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
|
||||
|
||||
if (!ret_val)
|
||||
ret_val = e1000_update_eeprom_checksum_i210(hw);
|
||||
|
||||
return ret_val;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
PROBE - Look for an adapter, this routine's visible to the outside
|
||||
You should omit the last argument struct pci_device * for a non-PCI NIC
|
||||
|
@ -5484,6 +5737,7 @@ e1000_initialize(bd_t * bis)
|
|||
nic->recv = e1000_poll;
|
||||
nic->send = e1000_transmit;
|
||||
nic->halt = e1000_disable;
|
||||
nic->write_hwaddr = e1000_write_hwaddr;
|
||||
eth_register(nic);
|
||||
}
|
||||
|
||||
|
|
|
@ -1242,6 +1242,9 @@ struct e1000_hw {
|
|||
#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
|
||||
#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
|
||||
#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
|
||||
#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
|
||||
#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
|
||||
#define E1000_FLUDONE_ATTEMPTS 20000
|
||||
#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
|
||||
#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
|
||||
#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
|
||||
|
|
|
@ -284,7 +284,7 @@ static int fec_tx_task_disable(struct fec_priv *fec)
|
|||
static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
|
||||
{
|
||||
uint32_t size;
|
||||
uint8_t *data;
|
||||
ulong data;
|
||||
int i;
|
||||
|
||||
/*
|
||||
|
@ -293,9 +293,9 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
|
|||
*/
|
||||
size = roundup(dsize, ARCH_DMA_MINALIGN);
|
||||
for (i = 0; i < count; i++) {
|
||||
data = (uint8_t *)fec->rbd_base[i].data_pointer;
|
||||
memset(data, 0, dsize);
|
||||
flush_dcache_range((uint32_t)data, (uint32_t)data + size);
|
||||
data = fec->rbd_base[i].data_pointer;
|
||||
memset((void *)data, 0, dsize);
|
||||
flush_dcache_range(data, data + size);
|
||||
|
||||
fec->rbd_base[i].status = FEC_RBD_EMPTY;
|
||||
fec->rbd_base[i].data_length = 0;
|
||||
|
@ -305,8 +305,8 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
|
|||
fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
|
||||
fec->rbd_index = 0;
|
||||
|
||||
flush_dcache_range((unsigned)fec->rbd_base,
|
||||
(unsigned)fec->rbd_base + size);
|
||||
flush_dcache_range((ulong)fec->rbd_base,
|
||||
(ulong)fec->rbd_base + size);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -323,7 +323,7 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
|
|||
*/
|
||||
static void fec_tbd_init(struct fec_priv *fec)
|
||||
{
|
||||
unsigned addr = (unsigned)fec->tbd_base;
|
||||
ulong addr = (ulong)fec->tbd_base;
|
||||
unsigned size = roundup(2 * sizeof(struct fec_bd),
|
||||
ARCH_DMA_MINALIGN);
|
||||
|
||||
|
@ -423,7 +423,7 @@ static int fec_open(struct eth_device *edev)
|
|||
struct fec_priv *fec = (struct fec_priv *)edev->priv;
|
||||
#endif
|
||||
int speed;
|
||||
uint32_t addr, size;
|
||||
ulong addr, size;
|
||||
int i;
|
||||
|
||||
debug("fec_open: fec_open(dev)\n");
|
||||
|
@ -439,7 +439,7 @@ static int fec_open(struct eth_device *edev)
|
|||
/* Flush the descriptors into RAM */
|
||||
size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
|
||||
ARCH_DMA_MINALIGN);
|
||||
addr = (uint32_t)fec->rbd_base;
|
||||
addr = (ulong)fec->rbd_base;
|
||||
flush_dcache_range(addr, addr + size);
|
||||
|
||||
#ifdef FEC_QUIRK_ENET_MAC
|
||||
|
@ -533,8 +533,9 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
|
|||
#else
|
||||
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
||||
#endif
|
||||
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
|
||||
int i;
|
||||
u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
|
||||
u8 *i;
|
||||
ulong addr;
|
||||
|
||||
/* Initialize MAC address */
|
||||
#ifdef CONFIG_DM_ETH
|
||||
|
@ -562,8 +563,8 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
|
|||
writel(0x00000000, &fec->eth->gaddr1);
|
||||
writel(0x00000000, &fec->eth->gaddr2);
|
||||
|
||||
/* Do not access reserved register for i.MX6UL */
|
||||
if (!is_mx6ul() && !is_mx6ull()) {
|
||||
/* Do not access reserved register */
|
||||
if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
|
||||
/* clear MIB RAM */
|
||||
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
|
||||
writel(0, i);
|
||||
|
@ -574,8 +575,12 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
|
|||
|
||||
/* size and address of each buffer */
|
||||
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
|
||||
writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
|
||||
writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
|
||||
|
||||
addr = (ulong)fec->tbd_base;
|
||||
writel((uint32_t)addr, &fec->eth->etdsr);
|
||||
|
||||
addr = (ulong)fec->rbd_base;
|
||||
writel((uint32_t)addr, &fec->eth->erdsr);
|
||||
|
||||
#ifndef CONFIG_PHYLIB
|
||||
if (fec->xcv_type != SEVENWIRE)
|
||||
|
@ -640,8 +645,8 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
|
|||
#endif
|
||||
{
|
||||
unsigned int status;
|
||||
uint32_t size, end;
|
||||
uint32_t addr;
|
||||
u32 size;
|
||||
ulong addr, end;
|
||||
int timeout = FEC_XFER_TIMEOUT;
|
||||
int ret = 0;
|
||||
|
||||
|
@ -672,13 +677,13 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
|
|||
swap_packet((uint32_t *)packet, length);
|
||||
#endif
|
||||
|
||||
addr = (uint32_t)packet;
|
||||
addr = (ulong)packet;
|
||||
end = roundup(addr + length, ARCH_DMA_MINALIGN);
|
||||
addr &= ~(ARCH_DMA_MINALIGN - 1);
|
||||
flush_dcache_range(addr, end);
|
||||
|
||||
writew(length, &fec->tbd_base[fec->tbd_index].data_length);
|
||||
writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
|
||||
writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
|
||||
|
||||
/*
|
||||
* update BD's status now
|
||||
|
@ -698,7 +703,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
|
|||
* can start DMA.
|
||||
*/
|
||||
size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
|
||||
addr = (uint32_t)fec->tbd_base;
|
||||
addr = (ulong)fec->tbd_base;
|
||||
flush_dcache_range(addr, addr + size);
|
||||
|
||||
/*
|
||||
|
@ -799,7 +804,7 @@ static int fec_recv(struct eth_device *dev)
|
|||
unsigned long ievent;
|
||||
int frame_length, len = 0;
|
||||
uint16_t bd_status;
|
||||
uint32_t addr, size, end;
|
||||
ulong addr, size, end;
|
||||
int i;
|
||||
ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
|
||||
|
||||
|
@ -854,7 +859,7 @@ static int fec_recv(struct eth_device *dev)
|
|||
* the descriptor. The solution is to mark the whole cache line when all
|
||||
* descriptors in the cache line are processed.
|
||||
*/
|
||||
addr = (uint32_t)rbd;
|
||||
addr = (ulong)rbd;
|
||||
addr &= ~(ARCH_DMA_MINALIGN - 1);
|
||||
size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
|
||||
invalidate_dcache_range(addr, addr + size);
|
||||
|
@ -882,8 +887,8 @@ static int fec_recv(struct eth_device *dev)
|
|||
len = frame_length;
|
||||
} else {
|
||||
if (bd_status & FEC_RBD_ERR)
|
||||
debug("error frame: 0x%08x 0x%08x\n",
|
||||
addr, bd_status);
|
||||
debug("error frame: 0x%08lx 0x%08x\n",
|
||||
addr, bd_status);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -895,7 +900,7 @@ static int fec_recv(struct eth_device *dev)
|
|||
size = RXDESC_PER_CACHELINE - 1;
|
||||
if ((fec->rbd_index & size) == size) {
|
||||
i = fec->rbd_index - size;
|
||||
addr = (uint32_t)&fec->rbd_base[i];
|
||||
addr = (ulong)&fec->rbd_base[i];
|
||||
for (; i <= fec->rbd_index ; i++) {
|
||||
fec_rbd_clean(i == (FEC_RBD_NUM - 1),
|
||||
&fec->rbd_base[i]);
|
||||
|
@ -922,6 +927,7 @@ static int fec_alloc_descs(struct fec_priv *fec)
|
|||
unsigned int size;
|
||||
int i;
|
||||
uint8_t *data;
|
||||
ulong addr;
|
||||
|
||||
/* Allocate TX descriptors. */
|
||||
size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
|
||||
|
@ -950,11 +956,12 @@ static int fec_alloc_descs(struct fec_priv *fec)
|
|||
|
||||
memset(data, 0, size);
|
||||
|
||||
fec->rbd_base[i].data_pointer = (uint32_t)data;
|
||||
addr = (ulong)data;
|
||||
fec->rbd_base[i].data_pointer = (uint32_t)addr;
|
||||
fec->rbd_base[i].status = FEC_RBD_EMPTY;
|
||||
fec->rbd_base[i].data_length = 0;
|
||||
/* Flush the buffer to memory. */
|
||||
flush_dcache_range((uint32_t)data, (uint32_t)data + size);
|
||||
flush_dcache_range(addr, addr + size);
|
||||
}
|
||||
|
||||
/* Mark the last RBD to close the ring. */
|
||||
|
@ -966,8 +973,10 @@ static int fec_alloc_descs(struct fec_priv *fec)
|
|||
return 0;
|
||||
|
||||
err_ring:
|
||||
for (; i >= 0; i--)
|
||||
free((void *)fec->rbd_base[i].data_pointer);
|
||||
for (; i >= 0; i--) {
|
||||
addr = fec->rbd_base[i].data_pointer;
|
||||
free((void *)addr);
|
||||
}
|
||||
free(fec->rbd_base);
|
||||
err_rx:
|
||||
free(fec->tbd_base);
|
||||
|
@ -978,9 +987,12 @@ err_tx:
|
|||
static void fec_free_descs(struct fec_priv *fec)
|
||||
{
|
||||
int i;
|
||||
ulong addr;
|
||||
|
||||
for (i = 0; i < FEC_RBD_NUM; i++)
|
||||
free((void *)fec->rbd_base[i].data_pointer);
|
||||
for (i = 0; i < FEC_RBD_NUM; i++) {
|
||||
addr = fec->rbd_base[i].data_pointer;
|
||||
free((void *)addr);
|
||||
}
|
||||
free(fec->rbd_base);
|
||||
free(fec->tbd_base);
|
||||
}
|
||||
|
@ -995,7 +1007,7 @@ struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
|
|||
struct fec_priv *priv = dev_get_priv(dev);
|
||||
struct ethernet_regs *eth = priv->eth;
|
||||
#else
|
||||
struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
|
||||
struct ethernet_regs *eth = (struct ethernet_regs *)(ulong)base_addr;
|
||||
#endif
|
||||
struct mii_dev *bus;
|
||||
int ret;
|
||||
|
@ -1065,7 +1077,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
|
|||
edev->halt = fec_halt;
|
||||
edev->write_hwaddr = fec_set_hwaddr;
|
||||
|
||||
fec->eth = (struct ethernet_regs *)base_addr;
|
||||
fec->eth = (struct ethernet_regs *)(ulong)base_addr;
|
||||
fec->bd = bd;
|
||||
|
||||
fec->xcv_type = CONFIG_FEC_XCV_TYPE;
|
||||
|
|
|
@ -8,7 +8,7 @@
|
|||
obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
|
||||
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
|
||||
obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
|
||||
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
|
||||
obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
|
||||
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
|
||||
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
|
||||
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
|
||||
|
|
|
@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
|
|||
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
|
||||
obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
|
||||
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
|
||||
obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
|
||||
obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
|
||||
obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
|
||||
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
|
||||
obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
|
||||
|
|
|
@ -30,6 +30,12 @@ config RTC_DS1307
|
|||
Support for Dallas Semiconductor (now Maxim) DS1307 and DS1338/9 and
|
||||
compatible Real Time Clock devices.
|
||||
|
||||
config RTC_RX8010SJ
|
||||
bool "Enable RX8010SJ driver"
|
||||
depends on DM_RTC
|
||||
help
|
||||
Support for Epson RX8010SJ Real Time Clock devices.
|
||||
|
||||
config RTC_S35392A
|
||||
bool "Enable S35392A driver"
|
||||
select BITREVERSE
|
||||
|
|
|
@ -48,6 +48,7 @@ obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
|
|||
obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o
|
||||
obj-$(CONFIG_RTC_RV3029) += rv3029.o
|
||||
obj-$(CONFIG_RTC_RX8025) += rx8025.o
|
||||
obj-$(CONFIG_RTC_RX8010SJ) += rx8010sj.o
|
||||
obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
|
||||
obj-$(CONFIG_RTC_S35392A) += s35392a.o
|
||||
obj-$(CONFIG_SANDBOX) += sandbox_rtc.o
|
||||
|
|
378
drivers/rtc/rx8010sj.c
Normal file
378
drivers/rtc/rx8010sj.c
Normal file
|
@ -0,0 +1,378 @@
|
|||
/*
|
||||
* Epson RX8010 RTC driver.
|
||||
*
|
||||
* Copyright (c) 2017, General Electric Company
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <command.h>
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <i2c.h>
|
||||
#include <rtc.h>
|
||||
|
||||
/*---------------------------------------------------------------------*/
|
||||
/* #undef DEBUG_RTC */
|
||||
|
||||
#ifdef DEBUG_RTC
|
||||
#define DEBUGR(fmt, args...) printf(fmt, ##args)
|
||||
#else
|
||||
#define DEBUGR(fmt, args...)
|
||||
#endif
|
||||
/*---------------------------------------------------------------------*/
|
||||
|
||||
#ifndef CONFIG_SYS_I2C_RTC_ADDR
|
||||
# define CONFIG_SYS_I2C_RTC_ADDR 0x32
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RTC register addresses
|
||||
*/
|
||||
#define RX8010_SEC 0x10
|
||||
#define RX8010_MIN 0x11
|
||||
#define RX8010_HOUR 0x12
|
||||
#define RX8010_WDAY 0x13
|
||||
#define RX8010_MDAY 0x14
|
||||
#define RX8010_MONTH 0x15
|
||||
#define RX8010_YEAR 0x16
|
||||
#define RX8010_YEAR 0x16
|
||||
#define RX8010_RESV17 0x17
|
||||
#define RX8010_ALMIN 0x18
|
||||
#define RX8010_ALHOUR 0x19
|
||||
#define RX8010_ALWDAY 0x1A
|
||||
#define RX8010_TCOUNT0 0x1B
|
||||
#define RX8010_TCOUNT1 0x1C
|
||||
#define RX8010_EXT 0x1D
|
||||
#define RX8010_FLAG 0x1E
|
||||
#define RX8010_CTRL 0x1F
|
||||
/* 0x20 to 0x2F are user registers */
|
||||
#define RX8010_RESV30 0x30
|
||||
#define RX8010_RESV31 0x32
|
||||
#define RX8010_IRQ 0x32
|
||||
|
||||
#define RX8010_EXT_WADA BIT(3)
|
||||
|
||||
#define RX8010_FLAG_VLF BIT(1)
|
||||
#define RX8010_FLAG_AF BIT(3)
|
||||
#define RX8010_FLAG_TF BIT(4)
|
||||
#define RX8010_FLAG_UF BIT(5)
|
||||
|
||||
#define RX8010_CTRL_AIE BIT(3)
|
||||
#define RX8010_CTRL_UIE BIT(5)
|
||||
#define RX8010_CTRL_STOP BIT(6)
|
||||
#define RX8010_CTRL_TEST BIT(7)
|
||||
|
||||
#define RX8010_ALARM_AE BIT(7)
|
||||
|
||||
#ifdef CONFIG_DM_RTC
|
||||
|
||||
#define DEV_TYPE struct udevice
|
||||
|
||||
#else
|
||||
|
||||
/* Local udevice */
|
||||
struct ludevice {
|
||||
u8 chip;
|
||||
};
|
||||
|
||||
#define DEV_TYPE struct ludevice
|
||||
|
||||
#endif
|
||||
|
||||
static int rx8010sj_rtc_read8(DEV_TYPE *dev, unsigned int reg)
|
||||
{
|
||||
u8 val;
|
||||
int ret;
|
||||
|
||||
#ifdef CONFIG_DM_RTC
|
||||
ret = dm_i2c_read(dev, reg, &val, sizeof(val));
|
||||
#else
|
||||
ret = i2c_read(dev->chip, reg, 1, &val, 1);
|
||||
#endif
|
||||
|
||||
return ret < 0 ? ret : val;
|
||||
}
|
||||
|
||||
static int rx8010sj_rtc_write8(DEV_TYPE *dev, unsigned int reg, int val)
|
||||
{
|
||||
int ret;
|
||||
u8 lval = val;
|
||||
|
||||
#ifdef CONFIG_DM_RTC
|
||||
ret = dm_i2c_write(dev, reg, &lval, 1);
|
||||
#else
|
||||
ret = i2c_write(dev->chip, reg, 1, &lval, 1);
|
||||
#endif
|
||||
|
||||
return ret < 0 ? ret : 0;
|
||||
}
|
||||
|
||||
static int validate_time(const struct rtc_time *tm)
|
||||
{
|
||||
if ((tm->tm_year < 2000) || (tm->tm_year > 2099))
|
||||
return -EINVAL;
|
||||
|
||||
if ((tm->tm_mon < 1) || (tm->tm_mon > 12))
|
||||
return -EINVAL;
|
||||
|
||||
if ((tm->tm_mday < 1) || (tm->tm_mday > 31))
|
||||
return -EINVAL;
|
||||
|
||||
if ((tm->tm_wday < 0) || (tm->tm_wday > 6))
|
||||
return -EINVAL;
|
||||
|
||||
if ((tm->tm_hour < 0) || (tm->tm_hour > 23))
|
||||
return -EINVAL;
|
||||
|
||||
if ((tm->tm_min < 0) || (tm->tm_min > 59))
|
||||
return -EINVAL;
|
||||
|
||||
if ((tm->tm_sec < 0) || (tm->tm_sec > 59))
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rx8010sj_rtc_init(DEV_TYPE *dev)
|
||||
{
|
||||
u8 ctrl[2];
|
||||
int need_clear = 0, ret = 0;
|
||||
|
||||
/* Initialize reserved registers as specified in datasheet */
|
||||
ret = rx8010sj_rtc_write8(dev, RX8010_RESV17, 0xD8);
|
||||
if (ret < 0)
|
||||
goto error;
|
||||
|
||||
ret = rx8010sj_rtc_write8(dev, RX8010_RESV30, 0x00);
|
||||
if (ret < 0)
|
||||
goto error;
|
||||
|
||||
ret = rx8010sj_rtc_write8(dev, RX8010_RESV31, 0x08);
|
||||
if (ret < 0)
|
||||
goto error;
|
||||
|
||||
ret = rx8010sj_rtc_write8(dev, RX8010_IRQ, 0x00);
|
||||
if (ret < 0)
|
||||
goto error;
|
||||
|
||||
for (int i = 0; i < 2; i++) {
|
||||
ret = rx8010sj_rtc_read8(dev, RX8010_FLAG + i);
|
||||
if (ret < 0)
|
||||
goto error;
|
||||
|
||||
ctrl[i] = ret;
|
||||
}
|
||||
|
||||
if (ctrl[0] & RX8010_FLAG_VLF)
|
||||
printf("RTC low voltage detected\n");
|
||||
|
||||
if (ctrl[0] & RX8010_FLAG_AF) {
|
||||
printf("Alarm was detected\n");
|
||||
need_clear = 1;
|
||||
}
|
||||
|
||||
if (ctrl[0] & RX8010_FLAG_TF)
|
||||
need_clear = 1;
|
||||
|
||||
if (ctrl[0] & RX8010_FLAG_UF)
|
||||
need_clear = 1;
|
||||
|
||||
if (need_clear) {
|
||||
ctrl[0] &= ~(RX8010_FLAG_AF | RX8010_FLAG_TF | RX8010_FLAG_UF);
|
||||
ret = rx8010sj_rtc_write8(dev, RX8010_FLAG, ctrl[0]);
|
||||
if (ret < 0)
|
||||
goto error;
|
||||
}
|
||||
|
||||
return;
|
||||
|
||||
error:
|
||||
printf("Error rtc init.\n");
|
||||
}
|
||||
|
||||
/* Get the current time from the RTC */
|
||||
static int rx8010sj_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp)
|
||||
{
|
||||
u8 date[7];
|
||||
int flagreg;
|
||||
int ret;
|
||||
|
||||
flagreg = rx8010sj_rtc_read8(dev, RX8010_FLAG);
|
||||
if (flagreg < 0) {
|
||||
DEBUGR("Error reading from RTC. err: %d\n", flagreg);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (flagreg & RX8010_FLAG_VLF) {
|
||||
DEBUGR("RTC low voltage detected\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (int i = 0; i < 7; i++) {
|
||||
ret = rx8010sj_rtc_read8(dev, RX8010_SEC + i);
|
||||
if (ret < 0) {
|
||||
DEBUGR("Error reading from RTC. err: %d\n", ret);
|
||||
return -EIO;
|
||||
}
|
||||
date[i] = ret;
|
||||
}
|
||||
|
||||
tmp->tm_sec = bcd2bin(date[RX8010_SEC - RX8010_SEC] & 0x7f);
|
||||
tmp->tm_min = bcd2bin(date[RX8010_MIN - RX8010_SEC] & 0x7f);
|
||||
tmp->tm_hour = bcd2bin(date[RX8010_HOUR - RX8010_SEC] & 0x3f);
|
||||
tmp->tm_mday = bcd2bin(date[RX8010_MDAY - RX8010_SEC] & 0x3f);
|
||||
tmp->tm_mon = bcd2bin(date[RX8010_MONTH - RX8010_SEC] & 0x1f);
|
||||
tmp->tm_year = bcd2bin(date[RX8010_YEAR - RX8010_SEC]) + 2000;
|
||||
tmp->tm_wday = 0;
|
||||
tmp->tm_yday = 0;
|
||||
tmp->tm_isdst = 0;
|
||||
|
||||
DEBUGR("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
|
||||
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
|
||||
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Set the RTC */
|
||||
static int rx8010sj_rtc_set(DEV_TYPE *dev, const struct rtc_time *tm)
|
||||
{
|
||||
u8 date[7];
|
||||
int ctrl, flagreg;
|
||||
int ret;
|
||||
|
||||
ret = validate_time(tm);
|
||||
if (ret < 0)
|
||||
return -EINVAL;
|
||||
|
||||
/* set STOP bit before changing clock/calendar */
|
||||
ctrl = rx8010sj_rtc_read8(dev, RX8010_CTRL);
|
||||
if (ctrl < 0)
|
||||
return ctrl;
|
||||
ret = rx8010sj_rtc_write8(dev, RX8010_CTRL, ctrl | RX8010_CTRL_STOP);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
date[RX8010_SEC - RX8010_SEC] = bin2bcd(tm->tm_sec);
|
||||
date[RX8010_MIN - RX8010_SEC] = bin2bcd(tm->tm_min);
|
||||
date[RX8010_HOUR - RX8010_SEC] = bin2bcd(tm->tm_hour);
|
||||
date[RX8010_MDAY - RX8010_SEC] = bin2bcd(tm->tm_mday);
|
||||
date[RX8010_MONTH - RX8010_SEC] = bin2bcd(tm->tm_mon);
|
||||
date[RX8010_YEAR - RX8010_SEC] = bin2bcd(tm->tm_year - 2000);
|
||||
date[RX8010_WDAY - RX8010_SEC] = bin2bcd(tm->tm_wday);
|
||||
|
||||
for (int i = 0; i < 7; i++) {
|
||||
ret = rx8010sj_rtc_write8(dev, RX8010_SEC + i, date[i]);
|
||||
if (ret < 0) {
|
||||
DEBUGR("Error writing to RTC. err: %d\n", ret);
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
|
||||
/* clear STOP bit after changing clock/calendar */
|
||||
ctrl = rx8010sj_rtc_read8(dev, RX8010_CTRL);
|
||||
if (ctrl < 0)
|
||||
return ctrl;
|
||||
|
||||
ret = rx8010sj_rtc_write8(dev, RX8010_CTRL, ctrl & ~RX8010_CTRL_STOP);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
flagreg = rx8010sj_rtc_read8(dev, RX8010_FLAG);
|
||||
if (flagreg < 0)
|
||||
return flagreg;
|
||||
|
||||
if (flagreg & RX8010_FLAG_VLF)
|
||||
ret = rx8010sj_rtc_write8(dev, RX8010_FLAG,
|
||||
flagreg & ~RX8010_FLAG_VLF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Reset the RTC. */
|
||||
static int rx8010sj_rtc_reset(DEV_TYPE *dev)
|
||||
{
|
||||
/* Not needed */
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_DM_RTC
|
||||
|
||||
int rtc_get(struct rtc_time *tm)
|
||||
{
|
||||
struct ludevice dev = {
|
||||
.chip = CONFIG_SYS_I2C_RTC_ADDR,
|
||||
};
|
||||
|
||||
return rx8010sj_rtc_get(&dev, tm);
|
||||
}
|
||||
|
||||
int rtc_set(struct rtc_time *tm)
|
||||
{
|
||||
struct ludevice dev = {
|
||||
.chip = CONFIG_SYS_I2C_RTC_ADDR,
|
||||
};
|
||||
|
||||
return rx8010sj_rtc_set(&dev, tm);
|
||||
}
|
||||
|
||||
void rtc_reset(void)
|
||||
{
|
||||
struct ludevice dev = {
|
||||
.chip = CONFIG_SYS_I2C_RTC_ADDR,
|
||||
};
|
||||
|
||||
rx8010sj_rtc_reset(&dev);
|
||||
}
|
||||
|
||||
void rtc_init(void)
|
||||
{
|
||||
struct ludevice dev = {
|
||||
.chip = CONFIG_SYS_I2C_RTC_ADDR,
|
||||
};
|
||||
|
||||
rx8010sj_rtc_init(&dev);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static int rx8010sj_probe(struct udevice *dev)
|
||||
{
|
||||
rx8010sj_rtc_init(&dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct rtc_ops rx8010sj_rtc_ops = {
|
||||
.get = rx8010sj_rtc_get,
|
||||
.set = rx8010sj_rtc_set,
|
||||
.read8 = rx8010sj_rtc_read8,
|
||||
.write8 = rx8010sj_rtc_write8,
|
||||
.reset = rx8010sj_rtc_reset,
|
||||
};
|
||||
|
||||
static const struct udevice_id rx8010sj_rtc_ids[] = {
|
||||
{ .compatible = "epson,rx8010sj-rtc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rx8010sj_rtc) = {
|
||||
.name = "rx8010sj_rtc",
|
||||
.id = UCLASS_RTC,
|
||||
.probe = rx8010sj_probe,
|
||||
.of_match = rx8010sj_rtc_ids,
|
||||
.ops = &rx8010sj_rtc_ops,
|
||||
};
|
||||
|
||||
#endif
|
|
@ -44,6 +44,12 @@
|
|||
#define CONFIG_REVISION_TAG
|
||||
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
|
||||
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
#define CONFIG_IMX_WATCHDOG
|
||||
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
|
||||
|
||||
#define CONFIG_LAST_STAGE_INIT
|
||||
|
||||
#define CONFIG_MXC_GPIO
|
||||
#define CONFIG_MXC_UART
|
||||
|
||||
|
@ -102,121 +108,67 @@
|
|||
#define CONFIG_SYS_TEXT_BASE 0x17800000
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=/boot/uImage\0" \
|
||||
"uboot=u-boot.imx\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x18000000\0" \
|
||||
"boot_fdt=yes\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"bootcause=POR\0" \
|
||||
"bootlimit=10\0" \
|
||||
"image=/boot/fitImage\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"dev=mmc\0" \
|
||||
"devnum=1\0" \
|
||||
"rootdev=mmcblk0p\0" \
|
||||
"quiet=quiet loglevel=0\0" \
|
||||
"console=" CONSOLE_DEV "\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"sddev=0\0" \
|
||||
"emmcdev=1\0" \
|
||||
"partnum=1\0" \
|
||||
"update_sd_firmware=" \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"if mmc dev ${mmcdev}; then " \
|
||||
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200; " \
|
||||
"setexpr fw_sz ${fw_sz} + 1; " \
|
||||
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"update_sf_uboot=" \
|
||||
"if tftp $loadaddr $uboot; then " \
|
||||
"sf probe; " \
|
||||
"sf erase 0 0xC0000; " \
|
||||
"sf write $loadaddr 0x400 $filesize; " \
|
||||
"echo 'U-Boot upgraded. Please reset'; " \
|
||||
"fi\0" \
|
||||
"setargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/${rootdev} rw rootwait cma=128M " \
|
||||
"setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
|
||||
"ro rootwait cma=128M " \
|
||||
"bootcause=${bootcause} " \
|
||||
"${quiet} console=${console} ${rtc_status} " \
|
||||
BX50V3_BOOTARGS_EXTRA "\0" \
|
||||
"loadbootscript=" \
|
||||
"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
|
||||
" source\0" \
|
||||
"doquiet=" \
|
||||
"if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
|
||||
"then setenv quiet; fi\0" \
|
||||
"hasfirstboot=" \
|
||||
"ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
|
||||
"/boot/bootcause/firstboot\0" \
|
||||
"swappartitions=" \
|
||||
"setexpr partnum 3 - ${partnum}\0" \
|
||||
"failbootcmd=" \
|
||||
"msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \
|
||||
"echo $msg; " \
|
||||
"setenv stdout vga; " \
|
||||
"echo \"\n\n\n\n \" $msg; " \
|
||||
"setenv stdout serial; " \
|
||||
"mw.b 0x7000A000 0xbc; " \
|
||||
"mw.b 0x7000A001 0x00; " \
|
||||
"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
|
||||
"altbootcmd=" \
|
||||
"run doquiet; " \
|
||||
"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
|
||||
"run hasfirstboot || setenv partnum 0; " \
|
||||
"if test ${partnum} != 0; then " \
|
||||
"setenv bootcause REVERT; " \
|
||||
"run swappartitions loadimage doboot; " \
|
||||
"fi; " \
|
||||
"run failbootcmd\0" \
|
||||
"loadimage=" \
|
||||
"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=ext2load ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
|
||||
"tryboot=" \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run doboot; " \
|
||||
"fi; " \
|
||||
"fi;\0" \
|
||||
"doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \
|
||||
"doboot=" \
|
||||
"echo Booting from ${dev}:${devnum}:${partnum} ...; " \
|
||||
"run setargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0" \
|
||||
"bootm ${loadaddr}#conf@${confidx}\0" \
|
||||
"tryboot=" \
|
||||
"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
|
||||
"run loadimage || run swappartitions && run loadimage || " \
|
||||
"setenv partnum 0 && echo MISSING IMAGE;" \
|
||||
"run doboot; " \
|
||||
"run failbootcmd\0" \
|
||||
|
||||
#define CONFIG_MMCBOOTCOMMAND \
|
||||
"setenv dev mmc; " \
|
||||
"setenv rootdev mmcblk0p${partnum}; " \
|
||||
\
|
||||
"setenv devnum ${sddev}; " \
|
||||
"if mmc dev ${devnum}; then " \
|
||||
"run tryboot; " \
|
||||
"setenv rootdev mmcblk1p${partnum}; " \
|
||||
"fi; " \
|
||||
\
|
||||
"setenv devnum ${emmcdev}; " \
|
||||
"if mmc dev ${devnum}; then " \
|
||||
"run doquiet; " \
|
||||
"run tryboot; " \
|
||||
"fi; " \
|
||||
|
||||
#define CONFIG_USBBOOTCOMMAND \
|
||||
"usb start; " \
|
||||
"setenv dev usb; " \
|
||||
"setenv devnum 0; " \
|
||||
"setenv rootdev sda${partnum}; " \
|
||||
"run tryboot; " \
|
||||
\
|
||||
CONFIG_MMCBOOTCOMMAND \
|
||||
"bmode usb; " \
|
||||
"echo Unsupported; " \
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
|
||||
|
@ -266,27 +218,32 @@
|
|||
#define CONFIG_SYS_FSL_USDHC_NUM 3
|
||||
|
||||
/* Framebuffer */
|
||||
#define CONFIG_VIDEO
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_IPUV3
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||||
#define CONFIG_SYS_CONSOLE_FG_COL 0xFF
|
||||
#define CONFIG_SYS_CONSOLE_BG_COL 0x00
|
||||
#define CONFIG_HIDE_LOGO_VERSION
|
||||
#define CONFIG_IMX_HDMI
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
#define CONFIG_CMD_BMP
|
||||
#endif
|
||||
|
||||
#define CONFIG_PWM_IMX
|
||||
#define CONFIG_IMX6_PWM_PER_CLK 66000000
|
||||
|
||||
#ifdef CONFIG_CMD_PCI
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
#define CONFIG_PCIE_IMX
|
||||
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
|
||||
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
|
||||
#endif
|
||||
|
||||
#define CONFIG_RTC_RX8010SJ
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 2
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x32
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
|
@ -296,9 +253,11 @@
|
|||
#define CONFIG_SYS_I2C_MXC_I2C2
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3
|
||||
|
||||
#define CONFIG_SYS_NUM_I2C_BUSES 9
|
||||
#define CONFIG_SYS_NUM_I2C_BUSES 11
|
||||
#define CONFIG_SYS_I2C_MAX_HOPS 1
|
||||
#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
|
||||
{1, {I2C_NULL_HOP} }, \
|
||||
{2, {I2C_NULL_HOP} }, \
|
||||
{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
|
||||
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
|
||||
{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
|
||||
|
@ -311,4 +270,11 @@
|
|||
|
||||
#define CONFIG_BCH
|
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT
|
||||
#define CONFIG_BOOTCOUNT_EXT
|
||||
#define CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE "mmc"
|
||||
#define CONFIG_SYS_BOOTCOUNT_EXT_DEVPART "1:5"
|
||||
#define CONFIG_SYS_BOOTCOUNT_EXT_NAME "/boot/failures"
|
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x7000A000
|
||||
|
||||
#endif /* __GE_BX50V3_CONFIG_H */
|
||||
|
|
|
@ -208,7 +208,7 @@
|
|||
|
||||
/* SPL */
|
||||
#ifdef CONFIG_SPL
|
||||
# ifdef CONFIG_NAND_MXS
|
||||
# ifdef CONFIG_ENV_IS_IN_NAND
|
||||
# define CONFIG_SPL_NAND_SUPPORT
|
||||
# else
|
||||
# define CONFIG_SPL_MMC_SUPPORT
|
||||
|
|
|
@ -1,8 +1,7 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2010-2018 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Boundary Devices Nitrogen6X
|
||||
* and Freescale i.MX6Q Sabre Lite boards.
|
||||
* Configuration settings for the virtual mx6memcal board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
@ -56,4 +55,6 @@
|
|||
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
|
||||
#define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
@ -208,8 +208,6 @@
|
|||
#define CONFIG_IMX_HDMI
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
|
||||
#ifndef CONFIG_SPL
|
||||
#define CONFIG_USBD_HS
|
||||
#endif
|
||||
|
||||
#endif /* __MX6QSABRE_COMMON_CONFIG_H */
|
||||
|
|
|
@ -61,6 +61,8 @@
|
|||
|
||||
#define CONFIG_ARMV7_SECURE_BASE 0x00900000
|
||||
|
||||
#define CONFIG_ARMV7_PSCI_1_0
|
||||
|
||||
/* Secure boot (HAB) support */
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
#define CONFIG_CSF_SIZE 0x2000
|
||||
|
|
612
include/dt-bindings/clock/imx8mq-clock.h
Normal file
612
include/dt-bindings/clock/imx8mq-clock.h
Normal file
|
@ -0,0 +1,612 @@
|
|||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX8MQ_H
|
||||
|
||||
#define IMX8MQ_CLK_DUMMY 0
|
||||
#define IMX8MQ_CLK_32K 1
|
||||
#define IMX8MQ_CLK_25M 2
|
||||
#define IMX8MQ_CLK_27M 3
|
||||
#define IMX8MQ_CLK_EXT1 4
|
||||
#define IMX8MQ_CLK_EXT2 5
|
||||
#define IMX8MQ_CLK_EXT3 6
|
||||
#define IMX8MQ_CLK_EXT4 7
|
||||
|
||||
/* ANAMIX PLL clocks */
|
||||
/* FRAC PLLs */
|
||||
/* ARM PLL */
|
||||
#define IMX8MQ_ARM_PLL_REF_SEL 8
|
||||
#define IMX8MQ_ARM_PLL_REF_DIV 9
|
||||
#define IMX8MQ_ARM_PLL 10
|
||||
#define IMX8MQ_ARM_PLL_BYPASS 11
|
||||
#define IMX8MQ_ARM_PLL_OUT 12
|
||||
|
||||
/* GPU PLL */
|
||||
#define IMX8MQ_GPU_PLL_REF_SEL 13
|
||||
#define IMX8MQ_GPU_PLL_REF_DIV 14
|
||||
#define IMX8MQ_GPU_PLL 15
|
||||
#define IMX8MQ_GPU_PLL_BYPASS 16
|
||||
#define IMX8MQ_GPU_PLL_OUT 17
|
||||
|
||||
/* VPU PLL */
|
||||
#define IMX8MQ_VPU_PLL_REF_SEL 18
|
||||
#define IMX8MQ_VPU_PLL_REF_DIV 19
|
||||
#define IMX8MQ_VPU_PLL 20
|
||||
#define IMX8MQ_VPU_PLL_BYPASS 21
|
||||
#define IMX8MQ_VPU_PLL_OUT 22
|
||||
|
||||
/* AUDIO PLL1 */
|
||||
#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
|
||||
#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
|
||||
#define IMX8MQ_AUDIO_PLL1 25
|
||||
#define IMX8MQ_AUDIO_PLL1_BYPASS 26
|
||||
#define IMX8MQ_AUDIO_PLL1_OUT 27
|
||||
|
||||
/* AUDIO PLL2 */
|
||||
#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
|
||||
#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
|
||||
#define IMX8MQ_AUDIO_PLL2 30
|
||||
#define IMX8MQ_AUDIO_PLL2_BYPASS 31
|
||||
#define IMX8MQ_AUDIO_PLL2_OUT 32
|
||||
|
||||
/* VIDEO PLL1 */
|
||||
#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
|
||||
#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
|
||||
#define IMX8MQ_VIDEO_PLL1 35
|
||||
#define IMX8MQ_VIDEO_PLL1_BYPASS 36
|
||||
#define IMX8MQ_VIDEO_PLL1_OUT 37
|
||||
|
||||
/* SYS1 PLL */
|
||||
#define IMX8MQ_SYS1_PLL1_REF_SEL 38
|
||||
#define IMX8MQ_SYS1_PLL1_REF_DIV 39
|
||||
#define IMX8MQ_SYS1_PLL1 40
|
||||
#define IMX8MQ_SYS1_PLL1_OUT 41
|
||||
#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
|
||||
#define IMX8MQ_SYS1_PLL2 43
|
||||
#define IMX8MQ_SYS1_PLL2_DIV 44
|
||||
#define IMX8MQ_SYS1_PLL2_OUT 45
|
||||
|
||||
/* SYS2 PLL */
|
||||
#define IMX8MQ_SYS2_PLL1_REF_SEL 46
|
||||
#define IMX8MQ_SYS2_PLL1_REF_DIV 47
|
||||
#define IMX8MQ_SYS2_PLL1 48
|
||||
#define IMX8MQ_SYS2_PLL1_OUT 49
|
||||
#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
|
||||
#define IMX8MQ_SYS2_PLL2 51
|
||||
#define IMX8MQ_SYS2_PLL2_DIV 52
|
||||
#define IMX8MQ_SYS2_PLL2_OUT 53
|
||||
|
||||
/* SYS3 PLL */
|
||||
#define IMX8MQ_SYS3_PLL1_REF_SEL 54
|
||||
#define IMX8MQ_SYS3_PLL1_REF_DIV 55
|
||||
#define IMX8MQ_SYS3_PLL1 56
|
||||
#define IMX8MQ_SYS3_PLL1_OUT 57
|
||||
#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
|
||||
#define IMX8MQ_SYS3_PLL2 59
|
||||
#define IMX8MQ_SYS3_PLL2_DIV 60
|
||||
#define IMX8MQ_SYS3_PLL2_OUT 61
|
||||
|
||||
/* DRAM PLL */
|
||||
#define IMX8MQ_DRAM_PLL1_REF_SEL 62
|
||||
#define IMX8MQ_DRAM_PLL1_REF_DIV 63
|
||||
#define IMX8MQ_DRAM_PLL1 64
|
||||
#define IMX8MQ_DRAM_PLL1_OUT 65
|
||||
#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
|
||||
#define IMX8MQ_DRAM_PLL2 67
|
||||
#define IMX8MQ_DRAM_PLL2_DIV 68
|
||||
#define IMX8MQ_DRAM_PLL2_OUT 69
|
||||
|
||||
/* SYS PLL DIV */
|
||||
#define IMX8MQ_SYS1_PLL_40M 70
|
||||
#define IMX8MQ_SYS1_PLL_80M 71
|
||||
#define IMX8MQ_SYS1_PLL_100M 72
|
||||
#define IMX8MQ_SYS1_PLL_133M 73
|
||||
#define IMX8MQ_SYS1_PLL_160M 74
|
||||
#define IMX8MQ_SYS1_PLL_200M 75
|
||||
#define IMX8MQ_SYS1_PLL_266M 76
|
||||
#define IMX8MQ_SYS1_PLL_400M 77
|
||||
#define IMX8MQ_SYS1_PLL_800M 78
|
||||
|
||||
#define IMX8MQ_SYS2_PLL_50M 79
|
||||
#define IMX8MQ_SYS2_PLL_100M 80
|
||||
#define IMX8MQ_SYS2_PLL_125M 81
|
||||
#define IMX8MQ_SYS2_PLL_166M 82
|
||||
#define IMX8MQ_SYS2_PLL_200M 83
|
||||
#define IMX8MQ_SYS2_PLL_250M 84
|
||||
#define IMX8MQ_SYS2_PLL_333M 85
|
||||
#define IMX8MQ_SYS2_PLL_500M 86
|
||||
#define IMX8MQ_SYS2_PLL_1000M 87
|
||||
|
||||
/* CCM ROOT clocks */
|
||||
/* A53 */
|
||||
#define IMX8MQ_CLK_A53_SRC 88
|
||||
#define IMX8MQ_CLK_A53_CG 89
|
||||
#define IMX8MQ_CLK_A53_DIV 90
|
||||
/* M4 */
|
||||
#define IMX8MQ_CLK_M4_SRC 91
|
||||
#define IMX8MQ_CLK_M4_CG 92
|
||||
#define IMX8MQ_CLK_M4_DIV 93
|
||||
/* VPU */
|
||||
#define IMX8MQ_CLK_VPU_SRC 94
|
||||
#define IMX8MQ_CLK_VPU_CG 95
|
||||
#define IMX8MQ_CLK_VPU_DIV 96
|
||||
/* GPU CORE */
|
||||
#define IMX8MQ_CLK_GPU_CORE_SRC 97
|
||||
#define IMX8MQ_CLK_GPU_CORE_CG 98
|
||||
#define IMX8MQ_CLK_GPU_CORE_DIV 99
|
||||
/* GPU SHADER */
|
||||
#define IMX8MQ_CLK_GPU_SHADER_SRC 100
|
||||
#define IMX8MQ_CLK_GPU_SHADER_CG 101
|
||||
#define IMX8MQ_CLK_GPU_SHADER_DIV 102
|
||||
|
||||
/* BUS TYPE */
|
||||
/* MAIN AXI */
|
||||
#define IMX8MQ_CLK_MAIN_AXI_SRC 103
|
||||
#define IMX8MQ_CLK_MAIN_AXI_CG 104
|
||||
#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV 105
|
||||
#define IMX8MQ_CLK_MAIN_AXI_DIV 106
|
||||
/* ENET AXI */
|
||||
#define IMX8MQ_CLK_ENET_AXI_SRC 107
|
||||
#define IMX8MQ_CLK_ENET_AXI_CG 108
|
||||
#define IMX8MQ_CLK_ENET_AXI_PRE_DIV 109
|
||||
#define IMX8MQ_CLK_ENET_AXI_DIV 110
|
||||
/* NAND_USDHC_BUS */
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC 111
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_CG 112
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV 113
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV 114
|
||||
/* VPU BUS */
|
||||
#define IMX8MQ_CLK_VPU_BUS_SRC 115
|
||||
#define IMX8MQ_CLK_VPU_BUS_CG 116
|
||||
#define IMX8MQ_CLK_VPU_BUS_PRE_DIV 117
|
||||
#define IMX8MQ_CLK_VPU_BUS_DIV 118
|
||||
/* DISP_AXI */
|
||||
#define IMX8MQ_CLK_DISP_AXI_SRC 119
|
||||
#define IMX8MQ_CLK_DISP_AXI_CG 120
|
||||
#define IMX8MQ_CLK_DISP_AXI_PRE_DIV 121
|
||||
#define IMX8MQ_CLK_DISP_AXI_DIV 122
|
||||
/* DISP APB */
|
||||
#define IMX8MQ_CLK_DISP_APB_SRC 123
|
||||
#define IMX8MQ_CLK_DISP_APB_CG 124
|
||||
#define IMX8MQ_CLK_DISP_APB_PRE_DIV 125
|
||||
#define IMX8MQ_CLK_DISP_APB_DIV 126
|
||||
/* DISP RTRM */
|
||||
#define IMX8MQ_CLK_DISP_RTRM_SRC 127
|
||||
#define IMX8MQ_CLK_DISP_RTRM_CG 128
|
||||
#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV 129
|
||||
#define IMX8MQ_CLK_DISP_RTRM_DIV 130
|
||||
/* USB_BUS */
|
||||
#define IMX8MQ_CLK_USB_BUS_SRC 131
|
||||
#define IMX8MQ_CLK_USB_BUS_CG 132
|
||||
#define IMX8MQ_CLK_USB_BUS_PRE_DIV 133
|
||||
#define IMX8MQ_CLK_USB_BUS_DIV 134
|
||||
/* GPU_AXI */
|
||||
#define IMX8MQ_CLK_GPU_AXI_SRC 135
|
||||
#define IMX8MQ_CLK_GPU_AXI_CG 136
|
||||
#define IMX8MQ_CLK_GPU_AXI_PRE_DIV 137
|
||||
#define IMX8MQ_CLK_GPU_AXI_DIV 138
|
||||
/* GPU_AHB */
|
||||
#define IMX8MQ_CLK_GPU_AHB_SRC 139
|
||||
#define IMX8MQ_CLK_GPU_AHB_CG 140
|
||||
#define IMX8MQ_CLK_GPU_AHB_PRE_DIV 141
|
||||
#define IMX8MQ_CLK_GPU_AHB_DIV 142
|
||||
/* NOC */
|
||||
#define IMX8MQ_CLK_NOC_SRC 143
|
||||
#define IMX8MQ_CLK_NOC_CG 144
|
||||
#define IMX8MQ_CLK_NOC_PRE_DIV 145
|
||||
#define IMX8MQ_CLK_NOC_DIV 146
|
||||
/* NOC_APB */
|
||||
#define IMX8MQ_CLK_NOC_APB_SRC 147
|
||||
#define IMX8MQ_CLK_NOC_APB_CG 148
|
||||
#define IMX8MQ_CLK_NOC_APB_PRE_DIV 149
|
||||
#define IMX8MQ_CLK_NOC_APB_DIV 150
|
||||
|
||||
/* AHB */
|
||||
#define IMX8MQ_CLK_AHB_SRC 151
|
||||
#define IMX8MQ_CLK_AHB_CG 152
|
||||
#define IMX8MQ_CLK_AHB_PRE_DIV 153
|
||||
#define IMX8MQ_CLK_AHB_DIV 154
|
||||
/* AUDIO AHB */
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_SRC 155
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_CG 156
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 157
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_DIV 158
|
||||
|
||||
/* DRAM_ALT */
|
||||
#define IMX8MQ_CLK_DRAM_ALT_SRC 159
|
||||
#define IMX8MQ_CLK_DRAM_ALT_CG 160
|
||||
#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV 161
|
||||
#define IMX8MQ_CLK_DRAM_ALT_DIV 162
|
||||
/* DRAM APB */
|
||||
#define IMX8MQ_CLK_DRAM_APB_SRC 163
|
||||
#define IMX8MQ_CLK_DRAM_APB_CG 164
|
||||
#define IMX8MQ_CLK_DRAM_APB_PRE_DIV 165
|
||||
#define IMX8MQ_CLK_DRAM_APB_DIV 166
|
||||
/* VPU_G1 */
|
||||
#define IMX8MQ_CLK_VPU_G1_SRC 167
|
||||
#define IMX8MQ_CLK_VPU_G1_CG 168
|
||||
#define IMX8MQ_CLK_VPU_G1_PRE_DIV 169
|
||||
#define IMX8MQ_CLK_VPU_G1_DIV 170
|
||||
/* VPU_G2 */
|
||||
#define IMX8MQ_CLK_VPU_G2_SRC 171
|
||||
#define IMX8MQ_CLK_VPU_G2_CG 172
|
||||
#define IMX8MQ_CLK_VPU_G2_PRE_DIV 173
|
||||
#define IMX8MQ_CLK_VPU_G2_DIV 174
|
||||
/* DISP_DTRC */
|
||||
#define IMX8MQ_CLK_DISP_DTRC_SRC 175
|
||||
#define IMX8MQ_CLK_DISP_DTRC_CG 176
|
||||
#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV 177
|
||||
#define IMX8MQ_CLK_DISP_DTRC_DIV 178
|
||||
/* DISP_DC8000 */
|
||||
#define IMX8MQ_CLK_DISP_DC8000_SRC 179
|
||||
#define IMX8MQ_CLK_DISP_DC8000_CG 180
|
||||
#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV 181
|
||||
#define IMX8MQ_CLK_DISP_DC8000_DIV 182
|
||||
/* PCIE_CTRL */
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_SRC 183
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_CG 184
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 185
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_DIV 186
|
||||
/* PCIE_PHY */
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_SRC 187
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_CG 188
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 189
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_DIV 190
|
||||
/* PCIE_AUX */
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_SRC 191
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_CG 192
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 193
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_DIV 194
|
||||
/* DC_PIXEL */
|
||||
#define IMX8MQ_CLK_DC_PIXEL_SRC 195
|
||||
#define IMX8MQ_CLK_DC_PIXEL_CG 196
|
||||
#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV 197
|
||||
#define IMX8MQ_CLK_DC_PIXEL_DIV 198
|
||||
/* LCDIF_PIXEL */
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_SRC 199
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_CG 200
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV 201
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_DIV 202
|
||||
/* SAI1~6 */
|
||||
#define IMX8MQ_CLK_SAI1_SRC 203
|
||||
#define IMX8MQ_CLK_SAI1_CG 204
|
||||
#define IMX8MQ_CLK_SAI1_PRE_DIV 205
|
||||
#define IMX8MQ_CLK_SAI1_DIV 206
|
||||
|
||||
#define IMX8MQ_CLK_SAI2_SRC 207
|
||||
#define IMX8MQ_CLK_SAI2_CG 208
|
||||
#define IMX8MQ_CLK_SAI2_PRE_DIV 209
|
||||
#define IMX8MQ_CLK_SAI2_DIV 210
|
||||
|
||||
#define IMX8MQ_CLK_SAI3_SRC 211
|
||||
#define IMX8MQ_CLK_SAI3_CG 212
|
||||
#define IMX8MQ_CLK_SAI3_PRE_DIV 213
|
||||
#define IMX8MQ_CLK_SAI3_DIV 214
|
||||
|
||||
#define IMX8MQ_CLK_SAI4_SRC 215
|
||||
#define IMX8MQ_CLK_SAI4_CG 216
|
||||
#define IMX8MQ_CLK_SAI4_PRE_DIV 217
|
||||
#define IMX8MQ_CLK_SAI4_DIV 218
|
||||
|
||||
#define IMX8MQ_CLK_SAI5_SRC 219
|
||||
#define IMX8MQ_CLK_SAI5_CG 220
|
||||
#define IMX8MQ_CLK_SAI5_PRE_DIV 221
|
||||
#define IMX8MQ_CLK_SAI5_DIV 222
|
||||
|
||||
#define IMX8MQ_CLK_SAI6_SRC 223
|
||||
#define IMX8MQ_CLK_SAI6_CG 224
|
||||
#define IMX8MQ_CLK_SAI6_PRE_DIV 225
|
||||
#define IMX8MQ_CLK_SAI6_DIV 226
|
||||
/* SPDIF1 */
|
||||
#define IMX8MQ_CLK_SPDIF1_SRC 227
|
||||
#define IMX8MQ_CLK_SPDIF1_CG 228
|
||||
#define IMX8MQ_CLK_SPDIF1_PRE_DIV 229
|
||||
#define IMX8MQ_CLK_SPDIF1_DIV 230
|
||||
/* SPDIF2 */
|
||||
#define IMX8MQ_CLK_SPDIF2_SRC 231
|
||||
#define IMX8MQ_CLK_SPDIF2_CG 232
|
||||
#define IMX8MQ_CLK_SPDIF2_PRE_DIV 233
|
||||
#define IMX8MQ_CLK_SPDIF2_DIV 234
|
||||
/* ENET_REF */
|
||||
#define IMX8MQ_CLK_ENET_REF_SRC 235
|
||||
#define IMX8MQ_CLK_ENET_REF_CG 236
|
||||
#define IMX8MQ_CLK_ENET_REF_PRE_DIV 237
|
||||
#define IMX8MQ_CLK_ENET_REF_DIV 238
|
||||
/* ENET_TIMER */
|
||||
#define IMX8MQ_CLK_ENET_TIMER_SRC 239
|
||||
#define IMX8MQ_CLK_ENET_TIMER_CG 240
|
||||
#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 241
|
||||
#define IMX8MQ_CLK_ENET_TIMER_DIV 242
|
||||
/* ENET_PHY */
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_SRC 243
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_CG 244
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 245
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_DIV 246
|
||||
/* NAND */
|
||||
#define IMX8MQ_CLK_NAND_SRC 247
|
||||
#define IMX8MQ_CLK_NAND_CG 248
|
||||
#define IMX8MQ_CLK_NAND_PRE_DIV 249
|
||||
#define IMX8MQ_CLK_NAND_DIV 250
|
||||
/* QSPI */
|
||||
#define IMX8MQ_CLK_QSPI_SRC 251
|
||||
#define IMX8MQ_CLK_QSPI_CG 252
|
||||
#define IMX8MQ_CLK_QSPI_PRE_DIV 253
|
||||
#define IMX8MQ_CLK_QSPI_DIV 254
|
||||
/* USDHC1 */
|
||||
#define IMX8MQ_CLK_USDHC1_SRC 255
|
||||
#define IMX8MQ_CLK_USDHC1_CG 256
|
||||
#define IMX8MQ_CLK_USDHC1_PRE_DIV 257
|
||||
#define IMX8MQ_CLK_USDHC1_DIV 258
|
||||
/* USDHC2 */
|
||||
#define IMX8MQ_CLK_USDHC2_SRC 259
|
||||
#define IMX8MQ_CLK_USDHC2_CG 260
|
||||
#define IMX8MQ_CLK_USDHC2_PRE_DIV 261
|
||||
#define IMX8MQ_CLK_USDHC2_DIV 262
|
||||
/* I2C1 */
|
||||
#define IMX8MQ_CLK_I2C1_SRC 263
|
||||
#define IMX8MQ_CLK_I2C1_CG 264
|
||||
#define IMX8MQ_CLK_I2C1_PRE_DIV 265
|
||||
#define IMX8MQ_CLK_I2C1_DIV 266
|
||||
/* I2C2 */
|
||||
#define IMX8MQ_CLK_I2C2_SRC 267
|
||||
#define IMX8MQ_CLK_I2C2_CG 268
|
||||
#define IMX8MQ_CLK_I2C2_PRE_DIV 269
|
||||
#define IMX8MQ_CLK_I2C2_DIV 270
|
||||
/* I2C3 */
|
||||
#define IMX8MQ_CLK_I2C3_SRC 271
|
||||
#define IMX8MQ_CLK_I2C3_CG 272
|
||||
#define IMX8MQ_CLK_I2C3_PRE_DIV 273
|
||||
#define IMX8MQ_CLK_I2C3_DIV 274
|
||||
/* I2C4 */
|
||||
#define IMX8MQ_CLK_I2C4_SRC 275
|
||||
#define IMX8MQ_CLK_I2C4_CG 276
|
||||
#define IMX8MQ_CLK_I2C4_PRE_DIV 277
|
||||
#define IMX8MQ_CLK_I2C4_DIV 278
|
||||
/* UART1 */
|
||||
#define IMX8MQ_CLK_UART1_SRC 279
|
||||
#define IMX8MQ_CLK_UART1_CG 280
|
||||
#define IMX8MQ_CLK_UART1_PRE_DIV 281
|
||||
#define IMX8MQ_CLK_UART1_DIV 282
|
||||
/* UART2 */
|
||||
#define IMX8MQ_CLK_UART2_SRC 283
|
||||
#define IMX8MQ_CLK_UART2_CG 284
|
||||
#define IMX8MQ_CLK_UART2_PRE_DIV 285
|
||||
#define IMX8MQ_CLK_UART2_DIV 286
|
||||
/* UART3 */
|
||||
#define IMX8MQ_CLK_UART3_SRC 287
|
||||
#define IMX8MQ_CLK_UART3_CG 288
|
||||
#define IMX8MQ_CLK_UART3_PRE_DIV 289
|
||||
#define IMX8MQ_CLK_UART3_DIV 290
|
||||
/* UART4 */
|
||||
#define IMX8MQ_CLK_UART4_SRC 291
|
||||
#define IMX8MQ_CLK_UART4_CG 292
|
||||
#define IMX8MQ_CLK_UART4_PRE_DIV 293
|
||||
#define IMX8MQ_CLK_UART4_DIV 294
|
||||
/* USB_CORE_REF */
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_SRC 295
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_CG 296
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 297
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_DIV 298
|
||||
/* USB_PHY_REF */
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_SRC 299
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_CG 300
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 301
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_DIV 302
|
||||
/* ECSPI1 */
|
||||
#define IMX8MQ_CLK_ECSPI1_SRC 303
|
||||
#define IMX8MQ_CLK_ECSPI1_CG 304
|
||||
#define IMX8MQ_CLK_ECSPI1_PRE_DIV 305
|
||||
#define IMX8MQ_CLK_ECSPI1_DIV 306
|
||||
/* ECSPI2 */
|
||||
#define IMX8MQ_CLK_ECSPI2_SRC 307
|
||||
#define IMX8MQ_CLK_ECSPI2_CG 308
|
||||
#define IMX8MQ_CLK_ECSPI2_PRE_DIV 309
|
||||
#define IMX8MQ_CLK_ECSPI2_DIV 310
|
||||
/* PWM1 */
|
||||
#define IMX8MQ_CLK_PWM1_SRC 311
|
||||
#define IMX8MQ_CLK_PWM1_CG 312
|
||||
#define IMX8MQ_CLK_PWM1_PRE_DIV 313
|
||||
#define IMX8MQ_CLK_PWM1_DIV 314
|
||||
/* PWM2 */
|
||||
#define IMX8MQ_CLK_PWM2_SRC 315
|
||||
#define IMX8MQ_CLK_PWM2_CG 316
|
||||
#define IMX8MQ_CLK_PWM2_PRE_DIV 317
|
||||
#define IMX8MQ_CLK_PWM2_DIV 318
|
||||
/* PWM3 */
|
||||
#define IMX8MQ_CLK_PWM3_SRC 319
|
||||
#define IMX8MQ_CLK_PWM3_CG 320
|
||||
#define IMX8MQ_CLK_PWM3_PRE_DIV 321
|
||||
#define IMX8MQ_CLK_PWM3_DIV 322
|
||||
/* PWM4 */
|
||||
#define IMX8MQ_CLK_PWM4_SRC 323
|
||||
#define IMX8MQ_CLK_PWM4_CG 324
|
||||
#define IMX8MQ_CLK_PWM4_PRE_DIV 325
|
||||
#define IMX8MQ_CLK_PWM4_DIV 326
|
||||
/* GPT1 */
|
||||
#define IMX8MQ_CLK_GPT1_SRC 327
|
||||
#define IMX8MQ_CLK_GPT1_CG 328
|
||||
#define IMX8MQ_CLK_GPT1_PRE_DIV 329
|
||||
#define IMX8MQ_CLK_GPT1_DIV 330
|
||||
/* WDOG */
|
||||
#define IMX8MQ_CLK_WDOG_SRC 331
|
||||
#define IMX8MQ_CLK_WDOG_CG 332
|
||||
#define IMX8MQ_CLK_WDOG_PRE_DIV 333
|
||||
#define IMX8MQ_CLK_WDOG_DIV 334
|
||||
/* WRCLK */
|
||||
#define IMX8MQ_CLK_WRCLK_SRC 335
|
||||
#define IMX8MQ_CLK_WRCLK_CG 336
|
||||
#define IMX8MQ_CLK_WRCLK_PRE_DIV 337
|
||||
#define IMX8MQ_CLK_WRCLK_DIV 338
|
||||
/* DSI_CORE */
|
||||
#define IMX8MQ_CLK_DSI_CORE_SRC 339
|
||||
#define IMX8MQ_CLK_DSI_CORE_CG 340
|
||||
#define IMX8MQ_CLK_DSI_CORE_PRE_DIV 341
|
||||
#define IMX8MQ_CLK_DSI_CORE_DIV 342
|
||||
/* DSI_PHY */
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_SRC 343
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_CG 344
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV 345
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_DIV 346
|
||||
/* DSI_DBI */
|
||||
#define IMX8MQ_CLK_DSI_DBI_SRC 347
|
||||
#define IMX8MQ_CLK_DSI_DBI_CG 348
|
||||
#define IMX8MQ_CLK_DSI_DBI_PRE_DIV 349
|
||||
#define IMX8MQ_CLK_DSI_DBI_DIV 350
|
||||
/*DSI_ESC */
|
||||
#define IMX8MQ_CLK_DSI_ESC_SRC 351
|
||||
#define IMX8MQ_CLK_DSI_ESC_CG 352
|
||||
#define IMX8MQ_CLK_DSI_ESC_PRE_DIV 353
|
||||
#define IMX8MQ_CLK_DSI_ESC_DIV 354
|
||||
/* CSI1_CORE */
|
||||
#define IMX8MQ_CLK_CSI1_CORE_SRC 355
|
||||
#define IMX8MQ_CLK_CSI1_CORE_CG 356
|
||||
#define IMX8MQ_CLK_CSI1_CORE_PRE_DIV 357
|
||||
#define IMX8MQ_CLK_CSI1_CORE_DIV 358
|
||||
/* CSI1_PHY */
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_SRC 359
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_CG 360
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV 361
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_DIV 362
|
||||
/* CSI_ESC */
|
||||
#define IMX8MQ_CLK_CSI1_ESC_SRC 363
|
||||
#define IMX8MQ_CLK_CSI1_ESC_CG 364
|
||||
#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV 365
|
||||
#define IMX8MQ_CLK_CSI1_ESC_DIV 366
|
||||
/* CSI2_CORE */
|
||||
#define IMX8MQ_CLK_CSI2_CORE_SRC 367
|
||||
#define IMX8MQ_CLK_CSI2_CORE_CG 368
|
||||
#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV 369
|
||||
#define IMX8MQ_CLK_CSI2_CORE_DIV 370
|
||||
/* CSI2_PHY */
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_SRC 371
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_CG 372
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV 373
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_DIV 374
|
||||
/* CSI2_ESC */
|
||||
#define IMX8MQ_CLK_CSI2_ESC_SRC 375
|
||||
#define IMX8MQ_CLK_CSI2_ESC_CG 376
|
||||
#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV 377
|
||||
#define IMX8MQ_CLK_CSI2_ESC_DIV 378
|
||||
/* PCIE2_CTRL */
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_SRC 379
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_CG 380
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 381
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_DIV 382
|
||||
/* PCIE2_PHY */
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_SRC 383
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_CG 384
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 385
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_DIV 386
|
||||
/* PCIE2_AUX */
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_SRC 387
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_CG 388
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 389
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_DIV 390
|
||||
/* ECSPI3 */
|
||||
#define IMX8MQ_CLK_ECSPI3_SRC 391
|
||||
#define IMX8MQ_CLK_ECSPI3_CG 392
|
||||
#define IMX8MQ_CLK_ECSPI3_PRE_DIV 393
|
||||
#define IMX8MQ_CLK_ECSPI3_DIV 394
|
||||
|
||||
/* CCGR clocks */
|
||||
#define IMX8MQ_CLK_A53_ROOT 395
|
||||
#define IMX8MQ_CLK_DRAM_ROOT 396
|
||||
#define IMX8MQ_CLK_ECSPI1_ROOT 397
|
||||
#define IMX8MQ_CLK_ECSPI2_ROOT 398
|
||||
#define IMX8MQ_CLK_ECSPI3_ROOT 399
|
||||
#define IMX8MQ_CLK_ENET1_ROOT 400
|
||||
#define IMX8MQ_CLK_GPT1_ROOT 401
|
||||
#define IMX8MQ_CLK_I2C1_ROOT 402
|
||||
#define IMX8MQ_CLK_I2C2_ROOT 403
|
||||
#define IMX8MQ_CLK_I2C3_ROOT 404
|
||||
#define IMX8MQ_CLK_I2C4_ROOT 405
|
||||
#define IMX8MQ_CLK_M4_ROOT 406
|
||||
#define IMX8MQ_CLK_PCIE1_ROOT 407
|
||||
#define IMX8MQ_CLK_PCIE2_ROOT 408
|
||||
#define IMX8MQ_CLK_PWM1_ROOT 409
|
||||
#define IMX8MQ_CLK_PWM2_ROOT 410
|
||||
#define IMX8MQ_CLK_PWM3_ROOT 411
|
||||
#define IMX8MQ_CLK_PWM4_ROOT 412
|
||||
#define IMX8MQ_CLK_QSPI_ROOT 413
|
||||
#define IMX8MQ_CLK_SAI1_ROOT 414
|
||||
#define IMX8MQ_CLK_SAI2_ROOT 415
|
||||
#define IMX8MQ_CLK_SAI3_ROOT 416
|
||||
#define IMX8MQ_CLK_SAI4_ROOT 417
|
||||
#define IMX8MQ_CLK_SAI5_ROOT 418
|
||||
#define IMX8MQ_CLK_SAI6_ROOT 419
|
||||
#define IMX8MQ_CLK_UART1_ROOT 420
|
||||
#define IMX8MQ_CLK_UART2_ROOT 421
|
||||
#define IMX8MQ_CLK_UART3_ROOT 422
|
||||
#define IMX8MQ_CLK_UART4_ROOT 423
|
||||
#define IMX8MQ_CLK_USB1_CTRL_ROOT 424
|
||||
#define IMX8MQ_CLK_USB2_CTRL_ROOT 425
|
||||
#define IMX8MQ_CLK_USB1_PHY_ROOT 426
|
||||
#define IMX8MQ_CLK_USB2_PHY_ROOT 427
|
||||
#define IMX8MQ_CLK_USDHC1_ROOT 428
|
||||
#define IMX8MQ_CLK_USDHC2_ROOT 429
|
||||
#define IMX8MQ_CLK_WDOG1_ROOT 430
|
||||
#define IMX8MQ_CLK_WDOG2_ROOT 431
|
||||
#define IMX8MQ_CLK_WDOG3_ROOT 432
|
||||
#define IMX8MQ_CLK_GPU_ROOT 433
|
||||
#define IMX8MQ_CLK_HEVC_ROOT 434
|
||||
#define IMX8MQ_CLK_AVC_ROOT 435
|
||||
#define IMX8MQ_CLK_VP9_ROOT 436
|
||||
#define IMX8MQ_CLK_HEVC_INTER_ROOT 437
|
||||
#define IMX8MQ_CLK_DISP_ROOT 438
|
||||
#define IMX8MQ_CLK_HDMI_ROOT 439
|
||||
#define IMX8MQ_CLK_HDMI_PHY_ROOT 440
|
||||
#define IMX8MQ_CLK_VPU_DEC_ROOT 441
|
||||
#define IMX8MQ_CLK_CSI1_ROOT 442
|
||||
#define IMX8MQ_CLK_CSI2_ROOT 443
|
||||
#define IMX8MQ_CLK_RAWNAND_ROOT 444
|
||||
#define IMX8MQ_CLK_SDMA1_ROOT 445
|
||||
#define IMX8MQ_CLK_SDMA2_ROOT 446
|
||||
#define IMX8MQ_CLK_VPU_G1_ROOT 447
|
||||
#define IMX8MQ_CLK_VPU_G2_ROOT 448
|
||||
|
||||
/* SCCG PLL GATE */
|
||||
#define IMX8MQ_SYS1_PLL_OUT 449
|
||||
#define IMX8MQ_SYS2_PLL_OUT 450
|
||||
#define IMX8MQ_SYS3_PLL_OUT 451
|
||||
#define IMX8MQ_DRAM_PLL_OUT 452
|
||||
|
||||
#define IMX8MQ_GPT_3M_CLK 453
|
||||
|
||||
#define IMX8MQ_CLK_IPG_ROOT 454
|
||||
#define IMX8MQ_CLK_IPG_AUDIO_ROOT 455
|
||||
#define IMX8MQ_CLK_SAI1_IPG 456
|
||||
#define IMX8MQ_CLK_SAI2_IPG 457
|
||||
#define IMX8MQ_CLK_SAI3_IPG 458
|
||||
#define IMX8MQ_CLK_SAI4_IPG 459
|
||||
#define IMX8MQ_CLK_SAI5_IPG 460
|
||||
#define IMX8MQ_CLK_SAI6_IPG 461
|
||||
|
||||
/* DSI AHB/IPG clocks */
|
||||
/* rxesc clock */
|
||||
#define IMX8MQ_CLK_DSI_AHB_SRC 462
|
||||
#define IMX8MQ_CLK_DSI_AHB_CG 463
|
||||
#define IMX8MQ_CLK_DSI_AHB_PRE_DIV 464
|
||||
#define IMX8MQ_CLK_DSI_AHB_DIV 465
|
||||
/* txesc clock */
|
||||
#define IMX8MQ_CLK_DSI_IPG_DIV 466
|
||||
|
||||
/* VIDEO2 PLL */
|
||||
#define IMX8MQ_VIDEO2_PLL1_REF_SEL 467
|
||||
#define IMX8MQ_VIDEO2_PLL1_REF_DIV 468
|
||||
#define IMX8MQ_VIDEO2_PLL1 469
|
||||
#define IMX8MQ_VIDEO2_PLL1_OUT 470
|
||||
#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 471
|
||||
#define IMX8MQ_VIDEO2_PLL2 472
|
||||
#define IMX8MQ_VIDEO2_PLL2_DIV 473
|
||||
#define IMX8MQ_VIDEO2_PLL2_OUT 474
|
||||
#define IMX8MQ_CLK_TMU_ROOT 475
|
||||
|
||||
#define IMX8MQ_CLK_END 476
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
|
632
include/dt-bindings/pinctrl/pins-imx8mq.h
Normal file
632
include/dt-bindings/pinctrl/pins-imx8mq.h
Normal file
|
@ -0,0 +1,632 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __DTS_IMX8MQ_PINFUNC_H
|
||||
#define __DTS_IMX8MQ_PINFUNC_H
|
||||
|
||||
/*
|
||||
* The pin function ID is a tuple of
|
||||
* <mux_reg conf_reg input_reg mux_mode input_val>
|
||||
*/
|
||||
|
||||
#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0
|
||||
|
||||
#endif /* __DTS_IMX8MQ_PINFUNC_H */
|
|
@ -10,6 +10,7 @@
|
|||
#ifndef __FSL_ESDHC_H__
|
||||
#define __FSL_ESDHC_H__
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
|
@ -173,6 +174,52 @@
|
|||
|
||||
#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
|
||||
|
||||
/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
|
||||
#define MIX_CTRL_DDREN BIT(3)
|
||||
#define MIX_CTRL_DTDSEL_READ BIT(4)
|
||||
#define MIX_CTRL_AC23EN BIT(7)
|
||||
#define MIX_CTRL_EXE_TUNE BIT(22)
|
||||
#define MIX_CTRL_SMPCLK_SEL BIT(23)
|
||||
#define MIX_CTRL_AUTO_TUNE_EN BIT(24)
|
||||
#define MIX_CTRL_FBCLK_SEL BIT(25)
|
||||
#define MIX_CTRL_HS400_EN BIT(26)
|
||||
#define MIX_CTRL_HS400_ES BIT(27)
|
||||
/* Bits 3 and 6 are not SDHCI standard definitions */
|
||||
#define MIX_CTRL_SDHCI_MASK 0xb7
|
||||
/* Tuning bits */
|
||||
#define MIX_CTRL_TUNING_MASK 0x03c00000
|
||||
|
||||
/* strobe dll register */
|
||||
#define ESDHC_STROBE_DLL_CTRL 0x70
|
||||
#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0)
|
||||
#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
|
||||
#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
|
||||
#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
|
||||
|
||||
#define ESDHC_STROBE_DLL_STATUS 0x74
|
||||
#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
|
||||
#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
|
||||
#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
|
||||
|
||||
#define ESDHC_STD_TUNING_EN BIT(24)
|
||||
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
|
||||
#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
|
||||
#define ESDHC_TUNING_START_TAP_MASK 0xff
|
||||
#define ESDHC_TUNING_STEP_MASK 0x00070000
|
||||
#define ESDHC_TUNING_STEP_SHIFT 16
|
||||
|
||||
#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
|
||||
#define ESDHC_FLAG_ENGCM07207 BIT(2)
|
||||
#define ESDHC_FLAG_USDHC BIT(3)
|
||||
#define ESDHC_FLAG_MAN_TUNING BIT(4)
|
||||
#define ESDHC_FLAG_STD_TUNING BIT(5)
|
||||
#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
|
||||
#define ESDHC_FLAG_ERR004536 BIT(7)
|
||||
#define ESDHC_FLAG_HS200 BIT(8)
|
||||
#define ESDHC_FLAG_HS400 BIT(9)
|
||||
#define ESDHC_FLAG_ERR010450 BIT(10)
|
||||
#define ESDHC_FLAG_HS400_ES BIT(11)
|
||||
|
||||
struct fsl_esdhc_cfg {
|
||||
phys_addr_t esdhc_base;
|
||||
u32 sdhc_clk;
|
||||
|
|
14
include/imx_sip.h
Normal file
14
include/imx_sip.h
Normal file
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _IMX_SIP_H__
|
||||
#define _IMX_SIP_H_
|
||||
|
||||
#define IMX_SIP_SRC 0xC2000005
|
||||
#define IMX_SIP_SRC_M4_START 0x00
|
||||
#define IMX_SIP_SRC_M4_STARTED 0x01
|
||||
|
||||
#endif
|
Loading…
Add table
Reference in a new issue