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edminiv2: add ethernet support
Add edminiv2 board support for mv_egiga. Add edminiv2 config to enable mv_egiga. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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3 changed files with 92 additions and 4 deletions
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@ -27,6 +27,7 @@
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#include <common.h>
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#include <miiphy.h>
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#include <asm/arch/orion5x.h>
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#include "edminiv2.h"
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DECLARE_GLOBAL_DATA_PTR;
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@ -90,3 +91,38 @@ int board_init(void)
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return 0;
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}
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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/* Configure and enable MV88E1116 PHY */
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void reset_phy(void)
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{
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u16 reg;
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u16 devadr;
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char *name = "egiga0";
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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printf("Err..%s could not read PHY dev address\n",
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__func__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, devadr);
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printf("88E1116 Initialized on %s\n", name);
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}
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#endif /* CONFIG_RESET_PHY_R */
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41
board/LaCie/edminiv2/edminiv2.h
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41
board/LaCie/edminiv2/edminiv2.h
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@ -0,0 +1,41 @@
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/*
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* (C) Copyright 2009
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* Net Insight <www.netinsight.net>
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* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
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*
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* Based on sheevaplug.h:
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef __EDMINIV2_BASE_H
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#define __EDMINIV2_BASE_H
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/* PHY related */
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#define MV88E1116_LED_FCTRL_REG 10
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#define MV88E1116_CPRSP_CR3_REG 21
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#define MV88E1116_MAC_CTRL_REG 21
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#define MV88E1116_PGADR_REG 22
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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#endif /* __EDMINIV2_BASE_H */
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@ -131,12 +131,23 @@
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* Commands configuration - using default command set for now
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*/
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#include <config_cmd_default.h>
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/*
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* Disabling some default commands for staggered bring-up
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* Network
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*/
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#undef CONFIG_CMD_BOOTD /* no bootd since no net */
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#undef CONFIG_CMD_NET /* no net since no eth */
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#undef CONFIG_CMD_NFS /* no NFS since no net */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_MVGBE /* Enable Marvell GbE Driver */
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#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
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#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
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#define CONFIG_PHY_BASE_ADR 0x8
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#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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#define CONFIG_NET_MULTI /* specify more that one ports available */
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#define CONFIG_MII /* expose smi ove miiphy interface */
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#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
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#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
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#endif
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/*
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* Environment variables configurations
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