mirror of
https://github.com/Fishwaldo/u-boot.git
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OMAP3: Clean up MMC code
Clean up OMAP3 MMC code: * Convert register access to struct & readx/writex style * Replace hardcode values by macros * Remove macro defined twice Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
This commit is contained in:
Dirk Behme
Jean-Christophe PLAGNIOL-VILLARD
parent
cfcdf4a9b3
commit
aba45c85b2
3 changed files with 114 additions and 90 deletions
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@ -28,6 +28,7 @@
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#include <mmc.h>
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#include <part.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/mmc.h>
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const unsigned short mmc_transspeed_val[15][4] = {
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@ -50,6 +51,7 @@ const unsigned short mmc_transspeed_val[15][4] = {
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mmc_card_data cur_card_data;
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static block_dev_desc_t mmc_blk_dev;
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static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC_BASE;
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block_dev_desc_t *mmc_get_dev(int dev)
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{
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@ -60,55 +62,49 @@ void twl4030_mmc_config(void)
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{
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unsigned char data;
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data = 0x20;
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i2c_write(0x4B, 0x82, 1, &data, 1);
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data = 0x2;
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i2c_write(0x4B, 0x85, 1, &data, 1);
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data = DEV_GRP_P1;
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i2c_write(PWRMGT_ADDR_ID4, VMMC1_DEV_GRP, 1, &data, 1);
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data = VMMC1_VSEL_30;
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i2c_write(PWRMGT_ADDR_ID4, VMMC1_DEDICATED, 1, &data, 1);
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}
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unsigned char mmc_board_init(void)
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{
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unsigned int value = 0;
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t2_t *t2_base = (t2_t *)T2_BASE;
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twl4030_mmc_config();
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value = CONTROL_PBIAS_LITE;
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CONTROL_PBIAS_LITE = value | (1 << 2) | (1 << 1) | (1 << 9);
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writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
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PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
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&t2_base->pbias_lite);
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value = CONTROL_DEV_CONF0;
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CONTROL_DEV_CONF0 = value | (1 << 24);
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writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
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&t2_base->devconf0);
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return 1;
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}
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void mmc_init_stream(void)
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{
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volatile unsigned int mmc_stat;
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writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
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OMAP_HSMMC_CON |= INIT_INITSTREAM;
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writel(MMC_CMD0, &mmc_base->cmd);
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while (!(readl(&mmc_base->stat) & CC_MASK));
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OMAP_HSMMC_CMD = MMC_CMD0;
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do {
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mmc_stat = OMAP_HSMMC_STAT;
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} while (!(mmc_stat & CC_MASK));
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writel(CC_MASK, &mmc_base->stat);
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OMAP_HSMMC_STAT = CC_MASK;
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writel(MMC_CMD0, &mmc_base->cmd);
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while (!(readl(&mmc_base->stat) & CC_MASK));
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OMAP_HSMMC_CMD = MMC_CMD0;
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do {
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mmc_stat = OMAP_HSMMC_STAT;
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} while (!(mmc_stat & CC_MASK));
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OMAP_HSMMC_STAT = OMAP_HSMMC_STAT;
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OMAP_HSMMC_CON &= ~INIT_INITSTREAM;
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writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
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}
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unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div)
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{
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unsigned int val;
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mmc_reg_out(OMAP_HSMMC_SYSCTL, (ICE_MASK | DTO_MASK | CEN_MASK),
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(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
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mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
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(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
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switch (iclk) {
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case CLK_INITSEQ:
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@ -123,12 +119,12 @@ unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div)
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default:
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return 0;
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}
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mmc_reg_out(OMAP_HSMMC_SYSCTL,
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ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE);
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mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
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(val << CLKD_OFFSET) | ICE_OSCILLATE);
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while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) ;
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while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY);
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OMAP_HSMMC_SYSCTL |= CEN_ENABLE;
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writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
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return 1;
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}
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@ -138,59 +134,63 @@ unsigned char mmc_init_setup(void)
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mmc_board_init();
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OMAP_HSMMC_SYSCONFIG |= MMC_SOFTRESET;
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while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0) ;
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writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
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&mmc_base->sysconfig);
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while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0);
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OMAP_HSMMC_SYSCTL |= SOFTRESETALL;
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while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0) ;
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writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
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while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0);
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OMAP_HSMMC_HCTL = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0;
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OMAP_HSMMC_CAPA |= VS30_3V0SUP | VS18_1V8SUP;
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writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
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writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
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&mmc_base->capa);
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reg_val = OMAP_HSMMC_CON & RESERVED_MASK;
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reg_val = readl(&mmc_base->con) & RESERVED_MASK;
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OMAP_HSMMC_CON = CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH |
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CDP_ACTIVEHIGH | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC |
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STR_BLOCK | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN;
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writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
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MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
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HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
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mmc_clock_config(CLK_INITSEQ, 0);
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OMAP_HSMMC_HCTL |= SDBP_PWRON;
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writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
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OMAP_HSMMC_IE = 0x307f0033;
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writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
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IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
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&mmc_base->ie);
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mmc_init_stream();
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return 1;
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}
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unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg,
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unsigned int *response)
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unsigned int *response)
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{
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volatile unsigned int mmc_stat;
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unsigned int mmc_stat;
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while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) ;
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while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS);
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OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT;
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OMAP_HSMMC_STAT = 0xFFFFFFFF;
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OMAP_HSMMC_ARG = arg;
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OMAP_HSMMC_CMD = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK |
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CCCE_NOCHECK | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE |
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DE_DISABLE;
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writel(BLEN_512BYTESLEN | NBLK_STPCNT, &mmc_base->blk);
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writel(0xFFFFFFFF, &mmc_base->stat);
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writel(arg, &mmc_base->arg);
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writel(cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
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MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE,
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&mmc_base->cmd);
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while (1) {
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do {
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mmc_stat = OMAP_HSMMC_STAT;
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mmc_stat = readl(&mmc_base->stat);
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} while (mmc_stat == 0);
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if ((mmc_stat & ERRI_MASK) != 0)
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return (unsigned char) mmc_stat;
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if (mmc_stat & CC_MASK) {
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OMAP_HSMMC_STAT = CC_MASK;
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response[0] = OMAP_HSMMC_RSP10;
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writel(CC_MASK, &mmc_base->stat);
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response[0] = readl(&mmc_base->rsp10);
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if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) {
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response[1] = OMAP_HSMMC_RSP32;
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response[2] = OMAP_HSMMC_RSP54;
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response[3] = OMAP_HSMMC_RSP76;
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response[1] = readl(&mmc_base->rsp32);
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response[2] = readl(&mmc_base->rsp54);
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response[3] = readl(&mmc_base->rsp76);
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}
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break;
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}
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@ -200,7 +200,7 @@ unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg,
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unsigned char mmc_read_data(unsigned int *output_buf)
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{
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volatile unsigned int mmc_stat;
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unsigned int mmc_stat;
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unsigned int read_count = 0;
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/*
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@ -208,7 +208,7 @@ unsigned char mmc_read_data(unsigned int *output_buf)
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*/
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while (1) {
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do {
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mmc_stat = OMAP_HSMMC_STAT;
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mmc_stat = readl(&mmc_base->stat);
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} while (mmc_stat == 0);
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if ((mmc_stat & ERRI_MASK) != 0)
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@ -217,19 +217,22 @@ unsigned char mmc_read_data(unsigned int *output_buf)
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if (mmc_stat & BRR_MASK) {
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unsigned int k;
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OMAP_HSMMC_STAT |= BRR_MASK;
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writel(readl(&mmc_base->stat) | BRR_MASK,
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&mmc_base->stat);
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for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) {
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*output_buf = OMAP_HSMMC_DATA;
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*output_buf = readl(&mmc_base->data);
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output_buf++;
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read_count += 4;
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}
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}
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if (mmc_stat & BWR_MASK)
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OMAP_HSMMC_STAT |= BWR_MASK;
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writel(readl(&mmc_base->stat) | BWR_MASK,
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&mmc_base->stat);
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if (mmc_stat & TC_MASK) {
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OMAP_HSMMC_STAT |= TC_MASK;
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writel(readl(&mmc_base->stat) | TC_MASK,
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&mmc_base->stat);
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break;
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}
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}
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@ -273,8 +276,8 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur)
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mmc_card_cur->card_type = MMC_CARD;
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ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR;
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ret_cmd41 = MMC_CMD1;
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OMAP_HSMMC_CON &= ~OD;
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OMAP_HSMMC_CON |= OPENDRAIN;
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writel(readl(&mmc_base->con) & ~OD, &mmc_base->con);
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writel(readl(&mmc_base->con) | OPENDRAIN, &mmc_base->con);
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}
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argument = ocr_value;
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@ -342,8 +345,8 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur)
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mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca;
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}
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OMAP_HSMMC_CON &= ~OD;
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OMAP_HSMMC_CON |= NOOPENDRAIN;
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writel(readl(&mmc_base->con) & ~OD, &mmc_base->con);
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writel(readl(&mmc_base->con) | NOOPENDRAIN, &mmc_base->con);
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return 1;
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}
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@ -518,7 +521,7 @@ unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt,
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void *dst)
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{
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omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data,
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(unsigned long *) dst);
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(unsigned long *) dst);
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return 1;
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}
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@ -25,30 +25,50 @@
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#ifndef MMC_HOST_DEF_H
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#define MMC_HOST_DEF_H
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/* T2 Register definitions */
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#define T2_BASE 0x48002000
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typedef struct t2 {
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unsigned char res1[0x274];
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unsigned int devconf0; /* 0x274 */
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unsigned char res2[0x2A8];
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unsigned int pbias_lite; /* 0x520 */
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} t2_t;
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#define MMCSDIO1ADPCLKISEL (1 << 24)
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#define PBIASLITEPWRDNZ0 (1 << 1)
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#define PBIASSPEEDCTRL0 (1 << 2)
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#define PBIASLITEPWRDNZ1 (1 << 9)
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/*
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* OMAP HSMMC register definitions
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*/
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#define OMAP_HSMMC_SYSCONFIG (*(unsigned int *) 0x4809C010)
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#define OMAP_HSMMC_SYSSTATUS (*(unsigned int *) 0x4809C014)
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#define OMAP_HSMMC_CON (*(unsigned int *) 0x4809C02C)
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#define OMAP_HSMMC_BLK (*(unsigned int *) 0x4809C104)
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#define OMAP_HSMMC_ARG (*(unsigned int *) 0x4809C108)
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#define OMAP_HSMMC_CMD (*(unsigned int *) 0x4809C10C)
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#define OMAP_HSMMC_RSP10 (*(unsigned int *) 0x4809C110)
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#define OMAP_HSMMC_RSP32 (*(unsigned int *) 0x4809C114)
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#define OMAP_HSMMC_RSP54 (*(unsigned int *) 0x4809C118)
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#define OMAP_HSMMC_RSP76 (*(unsigned int *) 0x4809C11C)
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#define OMAP_HSMMC_DATA (*(unsigned int *) 0x4809C120)
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#define OMAP_HSMMC_PSTATE (*(unsigned int *) 0x4809C124)
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#define OMAP_HSMMC_HCTL (*(unsigned int *) 0x4809C128)
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#define OMAP_HSMMC_SYSCTL (*(unsigned int *) 0x4809C12C)
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#define OMAP_HSMMC_STAT (*(unsigned int *) 0x4809C130)
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#define OMAP_HSMMC_IE (*(unsigned int *) 0x4809C134)
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#define OMAP_HSMMC_CAPA (*(unsigned int *) 0x4809C140)
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#define OMAP_HSMMC_BASE 0x4809C000
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/* T2 Register definitions */
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#define CONTROL_DEV_CONF0 (*(unsigned int *) 0x48002274)
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#define CONTROL_PBIAS_LITE (*(unsigned int *) 0x48002520)
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typedef struct hsmmc {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned int sysstatus; /* 0x14 */
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unsigned char res2[0x14];
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unsigned int con; /* 0x2C */
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unsigned char res3[0xD4];
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unsigned int blk; /* 0x104 */
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unsigned int arg; /* 0x108 */
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unsigned int cmd; /* 0x10C */
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unsigned int rsp10; /* 0x110 */
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unsigned int rsp32; /* 0x114 */
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unsigned int rsp54; /* 0x118 */
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unsigned int rsp76; /* 0x11C */
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unsigned int data; /* 0x120 */
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unsigned int pstate; /* 0x124 */
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unsigned int hctl; /* 0x128 */
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unsigned int sysctl; /* 0x12C */
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unsigned int stat; /* 0x130 */
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unsigned int ie; /* 0x134 */
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unsigned char res4[0x8];
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unsigned int capa; /* 0x140 */
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} hsmmc_t;
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/*
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* OMAP HS MMC Bit definitions
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@ -159,8 +179,6 @@ typedef struct {
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} mmc_card_data;
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#define mmc_reg_out(addr, mask, val)\
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(addr) = (((addr)) & (~(mask))) | ((val) & (mask));
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#define mmc_reg_out(addr, mask, val)\
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(addr) = (((addr)) & (~(mask))) | ((val) & (mask));
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writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
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#endif /* MMC_HOST_DEF_H */
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@ -203,6 +203,8 @@ typedef struct gpio {
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#define VAUX2_DEDICATED 0x79
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#define VAUX3_DEV_GRP 0x7A
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#define VAUX3_DEDICATED 0x7D
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#define VMMC1_DEV_GRP 0x82
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#define VMMC1_DEDICATED 0x85
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#define VPLL2_DEV_GRP 0x8E
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#define VPLL2_DEDICATED 0x91
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#define VDAC_DEV_GRP 0x96
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@ -215,5 +217,6 @@ typedef struct gpio {
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#define VAUX3_VSEL_28 0x03
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#define VPLL2_VSEL_18 0x05
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#define VDAC_VSEL_18 0x03
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#define VMMC1_VSEL_30 0x02
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#endif
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