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at91: nand: switch atmel_nand to generic GPIO API

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Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de>
Tested-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de>
Acked-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Andreas Bießmann 2013-11-29 12:13:45 +01:00
parent 934e3b5240
commit ac45bb1646
18 changed files with 43 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

5
board/BuS/vl_ma2sc/vl_ma2sc.c
View file

@ -10,6 +10,7 @@
#include <common.h> #include <common.h>
#include <asm/sizes.h> #include <asm/sizes.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/hardware.h> #include <asm/arch/hardware.h>
#include <asm/arch/clk.h> #include <asm/arch/clk.h>
#include <asm/arch/at91_matrix.h> #include <asm/arch/at91_matrix.h>
@ -65,10 +66,10 @@ static void vl_ma2sc_nand_hw_init(void)
/* Configure RDY/BSY */ /* Configure RDY/BSY */
#ifdef CONFIG_SYS_NAND_READY_PIN #ifdef CONFIG_SYS_NAND_READY_PIN
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
#endif #endif
/* Enable NandFlash */ /* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
} }
#endif #endif

3
board/egnite/ethernut5/ethernut5.c
View file

@ -71,6 +71,7 @@
#include <asm/arch/at91_spi.h> #include <asm/arch/at91_spi.h>
#include <asm/arch/gpio.h> #include <asm/arch/gpio.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/gpio.h>
#include "ethernut5_pwrman.h" #include "ethernut5_pwrman.h"
@ -141,7 +142,7 @@ static void ethernut5_nand_hw_init(void)
/* Ready pin is optional. */ /* Ready pin is optional. */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
#endif #endif
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
} }
#endif #endif

5
board/esd/meesc/meesc.c
View file

@ -12,6 +12,7 @@
#include <common.h> #include <common.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h> #include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pmc.h>
@ -74,10 +75,10 @@ static void meesc_nand_hw_init(void)
&smc->cs[3].mode); &smc->cs[3].mode);
/* Configure RDY/BSY */ /* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */ /* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
} }
#endif /* CONFIG_CMD_NAND */ #endif /* CONFIG_CMD_NAND */

5
board/esd/otc570/otc570.c
View file

@ -12,6 +12,7 @@
#include <common.h> #include <common.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h> #include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pmc.h>
@ -82,10 +83,10 @@ static void otc570_nand_hw_init(void)
&smc->cs[3].mode); &smc->cs[3].mode);
/* Configure RDY/BSY */ /* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */ /* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
} }
#endif /* CONFIG_CMD_NAND */ #endif /* CONFIG_CMD_NAND */

5
board/eukrea/cpu9260/cpu9260.c
View file

@ -12,6 +12,7 @@
#include <common.h> #include <common.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9260.h> #include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h> #include <asm/arch/at91_common.h>
@ -78,10 +79,10 @@ static void cpu9260_nand_hw_init(void)
writel(1 << ATMEL_ID_PIOC, &pmc->pcer); writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
/* Configure RDY/BSY */ /* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */ /* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
} }
#endif #endif

5
board/ronetix/pm9261/pm9261.c
View file

@ -11,6 +11,7 @@
#include <common.h> #include <common.h>
#include <asm/sizes.h> #include <asm/sizes.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h> #include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pmc.h>
@ -73,10 +74,10 @@ static void pm9261_nand_hw_init(void)
&pmc->pcer); &pmc->pcer);
/* Configure RDY/BSY */ /* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */ /* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */

5
board/ronetix/pm9263/pm9263.c
View file

@ -11,6 +11,7 @@
#include <common.h> #include <common.h>
#include <asm/sizes.h> #include <asm/sizes.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h> #include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pmc.h>
@ -67,10 +68,10 @@ static void pm9263_nand_hw_init(void)
&smc->cs[3].mode); &smc->cs[3].mode);
/* Configure RDY/BSY */ /* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */ /* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
} }
#endif #endif

5
board/ronetix/pm9g45/pm9g45.c
View file

@ -14,6 +14,7 @@
#include <common.h> #include <common.h>
#include <asm/sizes.h> #include <asm/sizes.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h> #include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pmc.h>
@ -66,11 +67,11 @@ static void pm9g45_nand_hw_init(void)
#ifdef CONFIG_SYS_NAND_READY_PIN #ifdef CONFIG_SYS_NAND_READY_PIN
/* Configure RDY/BSY */ /* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
#endif #endif
/* Enable NandFlash */ /* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
} }
#endif #endif

8
drivers/mtd/nand/atmel_nand.c
View file

@ -12,9 +12,8 @@
*/ */
#include <common.h> #include <common.h>
#include <asm/arch/hardware.h> #include <asm/gpio.h>
#include <asm/arch/gpio.h> #include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <malloc.h> #include <malloc.h>
#include <nand.h> #include <nand.h>
@ -1146,8 +1145,7 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE; IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
#ifdef CONFIG_SYS_NAND_ENABLE_PIN #ifdef CONFIG_SYS_NAND_ENABLE_PIN
at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN, gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
!(ctrl & NAND_NCE));
#endif #endif
this->IO_ADDR_W = (void *) IO_ADDR_W; this->IO_ADDR_W = (void *) IO_ADDR_W;
} }
@ -1159,7 +1157,7 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
#ifdef CONFIG_SYS_NAND_READY_PIN #ifdef CONFIG_SYS_NAND_READY_PIN
static int at91_nand_ready(struct mtd_info *mtd) static int at91_nand_ready(struct mtd_info *mtd)
{ {
return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN); return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
} }
#endif #endif

4
include/configs/at91sam9n12ek.h
View file

@ -113,8 +113,8 @@
#define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 4 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 5 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
/* PMECC & PMERRLOC */ /* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC #define CONFIG_ATMEL_NAND_HWECC

4
include/configs/cpu9260.h
View file

@ -280,8 +280,8 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1 #define CONFIG_SYS_NAND_DBW_8 1
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)

2
include/configs/ethernut5.h
View file

@ -149,7 +149,7 @@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */ /* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
#endif #endif
/* JFFS2 */ /* JFFS2 */

4
include/configs/meesc.h
View file

@ -143,8 +143,8 @@
# define CONFIG_SYS_NAND_DBW_8 # define CONFIG_SYS_NAND_DBW_8
# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) # define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) # define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
# define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
# define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
#endif #endif
/* Ethernet */ /* Ethernet */

4
include/configs/otc570.h
View file

@ -193,8 +193,8 @@
# define CONFIG_SYS_NAND_DBW_8 # define CONFIG_SYS_NAND_DBW_8
# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) # define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) # define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
# define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
# define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
#endif #endif
/* Ethernet */ /* Ethernet */

4
include/configs/pm9261.h
View file

@ -219,8 +219,8 @@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22) #define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */ /* our CLE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
/* NOR flash */ /* NOR flash */
#define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_SYS_FLASH_CFI 1

4
include/configs/pm9263.h
View file

@ -241,8 +241,8 @@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */ /* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30)
#endif #endif

4
include/configs/pm9g45.h
View file

@ -106,8 +106,8 @@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */ /* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 3 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3)
#endif #endif

4
include/configs/vl_ma2sc.h
View file

@ -320,8 +320,8 @@
#define CONFIG_SYS_NAND_DBW_8 1 #define CONFIG_SYS_NAND_DBW_8 1
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0)
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif #endif