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ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3
This is kind of microseries-within-series indent cleanup. This patch just tweaks the indentation so it is visible what to do with the grp_calibrated variable. It is likely that this patch has checkpatch warnings, but for the sake of not breaking the code, these are ignored. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
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1 changed files with 19 additions and 19 deletions
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@ -2235,8 +2235,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
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/*
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/*
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* In RLDRAMX we may be messing the delay of pins in
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* In RLDRAMX we may be messing the delay of pins in
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* the same write group but outside of the current read
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* the same write group but outside of the current read
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* the group, but that's ok because we haven't
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* the group, but that's ok because we haven't calibrated
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* calibrated output side yet.
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* output side yet.
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*/
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*/
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if (d > 0) {
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if (d > 0) {
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scc_mgr_apply_group_all_out_delay_add_all_ranks(
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scc_mgr_apply_group_all_out_delay_add_all_ranks(
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@ -2276,27 +2276,27 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
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* per shadow register basis.
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* per shadow register basis.
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*/
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*/
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for (rank_bgn = 0, sr = 0;
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for (rank_bgn = 0, sr = 0;
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rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
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rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
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rank_bgn += NUM_RANKS_PER_SHADOW_REG,
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rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
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++sr) {
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/*
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/*
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* Determine if this set of ranks
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* Determine if this set of ranks
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* should be skipped entirely.
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* should be skipped entirely.
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*/
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*/
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if (!param->skip_shadow_regs[sr]) {
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if (param->skip_shadow_regs[sr])
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/*
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continue;
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* If doing read after write
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/*
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* calibration, do not update
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* If doing read after write
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* FOM, now - do it then.
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* calibration, do not update
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*/
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* FOM, now - do it then.
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if (!rw_mgr_mem_calibrate_vfifo_center
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*/
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(rank_bgn, write_group,
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if (rw_mgr_mem_calibrate_vfifo_center
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read_group, test_bgn,
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(rank_bgn, write_group,
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1, 0)) {
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read_group, test_bgn,
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grp_calibrated = 0;
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1, 0))
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failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
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continue;
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}
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}
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grp_calibrated = 0;
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failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
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}
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}
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} else {
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} else {
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grp_calibrated = 0;
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grp_calibrated = 0;
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