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powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
parent
db564bccef
commit
acf3f8da98
3 changed files with 37 additions and 9 deletions
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@ -392,6 +392,12 @@ int cpu_init_r(void)
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puts("enabled\n");
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puts("enabled\n");
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}
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}
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#elif defined(CONFIG_BACKSIDE_L2_CACHE)
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#elif defined(CONFIG_BACKSIDE_L2_CACHE)
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if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
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(SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
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puts("N/A\n");
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goto skip_l2;
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}
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u32 l2cfg0 = mfspr(SPRN_L2CFG0);
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u32 l2cfg0 = mfspr(SPRN_L2CFG0);
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/* invalidate the L2 cache */
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/* invalidate the L2 cache */
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@ -412,6 +418,8 @@ int cpu_init_r(void)
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;
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;
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printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
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printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
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}
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}
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skip_l2:
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#else
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#else
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puts("disabled\n");
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puts("disabled\n");
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#endif
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#endif
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@ -228,6 +228,12 @@ static inline void ft_fixup_l2cache(void *blob)
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u32 *ph;
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u32 *ph;
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u32 l2cfg0 = mfspr(SPRN_L2CFG0);
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u32 l2cfg0 = mfspr(SPRN_L2CFG0);
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u32 size, line_size, num_ways, num_sets;
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u32 size, line_size, num_ways, num_sets;
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int has_l2 = 1;
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/* P2040/P2040E has no L2, so dont set any L2 props */
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if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
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(SVR_SOC_VER(get_svr()) == SVR_P2040_E))
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has_l2 = 0;
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size = (l2cfg0 & 0x3fff) * 64 * 1024;
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size = (l2cfg0 & 0x3fff) * 64 * 1024;
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num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
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num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
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@ -250,21 +256,22 @@ static inline void ft_fixup_l2cache(void *blob)
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goto next;
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goto next;
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}
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}
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if (has_l2) {
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#ifdef CONFIG_SYS_CACHE_STASHING
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#ifdef CONFIG_SYS_CACHE_STASHING
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{
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u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
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u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
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if (reg)
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if (reg)
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fdt_setprop_cell(blob, l2_off, "cache-stash-id",
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fdt_setprop_cell(blob, l2_off, "cache-stash-id",
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(*reg * 2) + 32 + 1);
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(*reg * 2) + 32 + 1);
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}
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#endif
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#endif
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fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
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fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
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fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
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fdt_setprop_cell(blob, l2_off, "cache-block-size",
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fdt_setprop_cell(blob, l2_off, "cache-size", size);
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line_size);
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fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
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fdt_setprop_cell(blob, l2_off, "cache-size", size);
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fdt_setprop_cell(blob, l2_off, "cache-level", 2);
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fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
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fdt_setprop(blob, l2_off, "compatible", "cache", 6);
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fdt_setprop_cell(blob, l2_off, "cache-level", 2);
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fdt_setprop(blob, l2_off, "compatible", "cache", 6);
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}
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if (l3_off < 0) {
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if (l3_off < 0) {
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ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
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ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc.
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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* Kumar Gala <kumar.gala@freescale.com>
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* Kumar Gala <kumar.gala@freescale.com>
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*
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*
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* See file CREDITS for list of people who contributed to this
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* See file CREDITS for list of people who contributed to this
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@ -144,6 +144,18 @@ __secondary_start_page:
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#endif
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#endif
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#ifdef CONFIG_BACKSIDE_L2_CACHE
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#ifdef CONFIG_BACKSIDE_L2_CACHE
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/* skip L2 setup on P2040/P2040E as they have no L2 */
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mfspr r2,SPRN_SVR
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lis r3,SVR_P2040@h
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ori r3,r3,SVR_P2040@l
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cmpw r2,r3
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beq 3f
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lis r3,SVR_P2040_E@h
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ori r3,r3,SVR_P2040_E@l
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cmpw r2,r3
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beq 3f
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/* Enable/invalidate the L2 cache */
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/* Enable/invalidate the L2 cache */
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msync
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msync
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lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
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lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
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@ -169,6 +181,7 @@ __secondary_start_page:
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andis. r1,r3,L2CSR0_L2E@h
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andis. r1,r3,L2CSR0_L2E@h
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beq 2b
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beq 2b
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#endif
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#endif
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3:
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#define EPAPR_MAGIC (0x45504150)
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#define EPAPR_MAGIC (0x45504150)
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#define ENTRY_ADDR_UPPER 0
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#define ENTRY_ADDR_UPPER 0
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