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pci: rockchip: Drop legacy PHY driver
Drop the legacy PHY driver and it's associated code since the PHY handling driver now part of Generic PHY framework. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
parent
ce920e0e56
commit
ad415c80a5
4 changed files with 74 additions and 354 deletions
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@ -43,5 +43,5 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
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obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
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obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
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obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
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obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
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obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
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obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
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@ -15,6 +15,7 @@
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <generic-phy.h>
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#include <pci.h>
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#include <power-domain.h>
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#include <power/regulator.h>
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@ -25,10 +26,80 @@
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#include <asm/arch-rockchip/clock.h>
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#include <linux/iopoll.h>
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#include "pcie_rockchip.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
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#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
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#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
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#define PCIE_CLIENT_BASE 0x0
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#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
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#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
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#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
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#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
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#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
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#define PCIE_CLIENT_BASIC_STATUS1 0x0048
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#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
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#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
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#define PCIE_LINK_UP(x) \
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(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
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#define PCIE_RC_NORMAL_BASE 0x800000
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#define PCIE_LM_BASE 0x900000
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#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
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#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
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#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
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#define PCIE_LM_RCBARPIE BIT(19)
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#define PCIE_LM_RCBARPIS BIT(20)
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#define PCIE_RC_BASE 0xa00000
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#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
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#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
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#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
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#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
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#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
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#define PCIE_ATR_BASE 0xc00000
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#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
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#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
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#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
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#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
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#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
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#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
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#define PCIE_ATR_HDR_MEM 0x2
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#define PCIE_ATR_HDR_IO 0x6
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#define PCIE_ATR_HDR_CFG_TYPE0 0xa
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#define PCIE_ATR_HDR_CFG_TYPE1 0xb
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#define PCIE_ATR_HDR_RID BIT(23)
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#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
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#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
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struct rockchip_pcie {
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fdt_addr_t axi_base;
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fdt_addr_t apb_base;
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int first_busno;
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struct udevice *dev;
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/* resets */
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struct reset_ctl core_rst;
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struct reset_ctl mgmt_rst;
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struct reset_ctl mgmt_sticky_rst;
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struct reset_ctl pipe_rst;
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struct reset_ctl pm_rst;
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struct reset_ctl pclk_rst;
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struct reset_ctl aclk_rst;
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/* gpio */
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struct gpio_desc ep_gpio;
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/* vpcie regulators */
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struct udevice *vpcie12v;
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struct udevice *vpcie3v3;
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struct udevice *vpcie1v8;
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struct udevice *vpcie0v9;
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/* phy */
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struct phy pcie_phy;
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};
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static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
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{
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unsigned int bus = PCI_BUS(bdf);
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@ -1,146 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Rockchip PCIe Headers
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*
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* Copyright (c) 2016 Rockchip, Inc.
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* Copyright (c) 2020 Amarula Solutions(India)
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* Copyright (c) 2020 Jagan Teki <jagan@amarulasolutions.com>
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* Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
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*
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*/
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#include <generic-phy.h>
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#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
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#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
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#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
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#define PCIE_CLIENT_BASE 0x0
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#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
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#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
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#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
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#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
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#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
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#define PCIE_CLIENT_BASIC_STATUS1 0x0048
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#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
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#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
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#define PCIE_LINK_UP(x) \
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(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
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#define PCIE_RC_NORMAL_BASE 0x800000
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#define PCIE_LM_BASE 0x900000
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#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
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#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
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#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
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#define PCIE_LM_RCBARPIE BIT(19)
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#define PCIE_LM_RCBARPIS BIT(20)
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#define PCIE_RC_BASE 0xa00000
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#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
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#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
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#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
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#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
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#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
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#define PCIE_ATR_BASE 0xc00000
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#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
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#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
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#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
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#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
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#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
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#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
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#define PCIE_ATR_HDR_MEM 0x2
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#define PCIE_ATR_HDR_IO 0x6
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#define PCIE_ATR_HDR_CFG_TYPE0 0xa
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#define PCIE_ATR_HDR_CFG_TYPE1 0xb
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#define PCIE_ATR_HDR_RID BIT(23)
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#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
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#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
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/*
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* The higher 16-bit of this register is used for write protection
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* only if BIT(x + 16) set to 1 the BIT(x) can be written.
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*/
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#define HIWORD_UPDATE_MASK(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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#define PHY_CFG_DATA_SHIFT 7
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#define PHY_CFG_ADDR_SHIFT 1
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#define PHY_CFG_DATA_MASK 0xf
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#define PHY_CFG_ADDR_MASK 0x3f
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#define PHY_CFG_RD_MASK 0x3ff
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#define PHY_CFG_WR_ENABLE 1
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#define PHY_CFG_WR_DISABLE 1
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#define PHY_CFG_WR_SHIFT 0
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#define PHY_CFG_WR_MASK 1
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#define PHY_CFG_PLL_LOCK 0x10
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#define PHY_CFG_CLK_TEST 0x10
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#define PHY_CFG_CLK_SCC 0x12
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#define PHY_CFG_SEPE_RATE BIT(3)
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#define PHY_CFG_PLL_100M BIT(3)
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#define PHY_PLL_LOCKED BIT(9)
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#define PHY_PLL_OUTPUT BIT(10)
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#define PHY_LANE_IDLE_OFF 0x1
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#define PHY_LANE_IDLE_MASK 0x1
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#define PHY_LANE_IDLE_A_SHIFT 3
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#define PHY_LANE_IDLE_B_SHIFT 4
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#define PHY_LANE_IDLE_C_SHIFT 5
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#define PHY_LANE_IDLE_D_SHIFT 6
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#define PCIE_PHY_CONF 0xe220
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#define PCIE_PHY_STATUS 0xe2a4
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#define PCIE_PHY_LANEOFF 0xe214
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struct rockchip_pcie_phy {
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void *reg_base;
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struct clk refclk;
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struct reset_ctl phy_rst;
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struct rockchip_pcie_phy_ops *ops;
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};
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struct rockchip_pcie_phy_ops {
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int (*init)(struct rockchip_pcie_phy *phy);
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int (*exit)(struct rockchip_pcie_phy *phy);
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int (*power_on)(struct rockchip_pcie_phy *phy);
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int (*power_off)(struct rockchip_pcie_phy *phy);
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};
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struct rockchip_pcie {
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fdt_addr_t axi_base;
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fdt_addr_t apb_base;
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int first_busno;
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struct udevice *dev;
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struct rockchip_pcie_phy rk_phy;
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struct rockchip_pcie_phy *phy;
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/* resets */
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struct reset_ctl core_rst;
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struct reset_ctl mgmt_rst;
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struct reset_ctl mgmt_sticky_rst;
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struct reset_ctl pipe_rst;
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struct reset_ctl pm_rst;
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struct reset_ctl pclk_rst;
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struct reset_ctl aclk_rst;
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/* gpio */
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struct gpio_desc ep_gpio;
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/* vpcie regulators */
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struct udevice *vpcie12v;
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struct udevice *vpcie3v3;
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struct udevice *vpcie1v8;
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struct udevice *vpcie0v9;
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/* phy */
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struct phy pcie_phy;
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};
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int rockchip_pcie_phy_get(struct udevice *dev);
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static inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie)
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{
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return pcie->phy;
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}
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static inline struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy)
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{
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return (struct rockchip_pcie_phy_ops *)phy->ops;
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}
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@ -1,205 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Rockchip PCIe PHY driver
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*
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* Copyright (c) 2016 Rockchip, Inc.
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <reset.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <linux/iopoll.h>
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#include <asm/arch-rockchip/clock.h>
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#include "pcie_rockchip.h"
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DECLARE_GLOBAL_DATA_PTR;
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static void phy_wr_cfg(struct rockchip_pcie_phy *phy, u32 addr, u32 data)
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{
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u32 reg;
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reg = HIWORD_UPDATE_MASK(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
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reg |= HIWORD_UPDATE_MASK(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_CONF);
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udelay(1);
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reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_ENABLE,
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PHY_CFG_WR_MASK,
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PHY_CFG_WR_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_CONF);
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udelay(1);
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reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_DISABLE,
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PHY_CFG_WR_MASK,
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PHY_CFG_WR_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_CONF);
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}
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static int rockchip_pcie_phy_power_on(struct rockchip_pcie_phy *phy)
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{
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int ret = 0;
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u32 reg, status;
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ret = reset_deassert(&phy->phy_rst);
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if (ret) {
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dev_err(dev, "failed to assert phy reset\n");
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return ret;
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}
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reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
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PHY_CFG_ADDR_MASK,
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PHY_CFG_ADDR_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_CONF);
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reg = HIWORD_UPDATE_MASK(!PHY_LANE_IDLE_OFF,
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PHY_LANE_IDLE_MASK,
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PHY_LANE_IDLE_A_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
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ret = -EINVAL;
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ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
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status,
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status & PHY_PLL_LOCKED,
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20 * 1000,
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50);
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if (ret) {
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dev_err(&phy->dev, "pll lock timeout!\n");
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goto err_pll_lock;
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}
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phy_wr_cfg(phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
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phy_wr_cfg(phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
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ret = -ETIMEDOUT;
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ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
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status,
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!(status & PHY_PLL_OUTPUT),
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20 * 1000,
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50);
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if (ret) {
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dev_err(&phy->dev, "pll output enable timeout!\n");
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goto err_pll_lock;
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}
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reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
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PHY_CFG_ADDR_MASK,
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PHY_CFG_ADDR_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_CONF);
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ret = -EINVAL;
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ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
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status,
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status & PHY_PLL_LOCKED,
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20 * 1000,
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50);
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if (ret) {
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dev_err(&phy->dev, "pll relock timeout!\n");
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goto err_pll_lock;
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}
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return 0;
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err_pll_lock:
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reset_assert(&phy->phy_rst);
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return ret;
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}
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static int rockchip_pcie_phy_power_off(struct rockchip_pcie_phy *phy)
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{
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int ret;
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u32 reg;
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reg = HIWORD_UPDATE_MASK(PHY_LANE_IDLE_OFF,
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PHY_LANE_IDLE_MASK,
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PHY_LANE_IDLE_A_SHIFT);
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writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
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ret = reset_assert(&phy->phy_rst);
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if (ret) {
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dev_err(dev, "failed to assert phy reset\n");
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return ret;
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}
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return 0;
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}
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static int rockchip_pcie_phy_init(struct rockchip_pcie_phy *phy)
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{
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int ret;
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ret = clk_enable(&phy->refclk);
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if (ret) {
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dev_err(dev, "failed to enable refclk clock\n");
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return ret;
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}
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ret = reset_assert(&phy->phy_rst);
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if (ret) {
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dev_err(dev, "failed to assert phy reset\n");
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goto err_reset;
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}
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return 0;
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err_reset:
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clk_disable(&phy->refclk);
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return ret;
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}
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static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy)
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{
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clk_disable(&phy->refclk);
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return 0;
|
||||
}
|
||||
|
||||
static struct rockchip_pcie_phy_ops pcie_phy_ops = {
|
||||
.init = rockchip_pcie_phy_init,
|
||||
.power_on = rockchip_pcie_phy_power_on,
|
||||
.power_off = rockchip_pcie_phy_power_off,
|
||||
.exit = rockchip_pcie_phy_exit,
|
||||
};
|
||||
|
||||
int rockchip_pcie_phy_get(struct udevice *dev)
|
||||
{
|
||||
struct rockchip_pcie *priv = dev_get_priv(dev);
|
||||
struct rockchip_pcie_phy *phy_priv = &priv->rk_phy;
|
||||
ofnode phy_node;
|
||||
u32 phandle;
|
||||
int ret;
|
||||
|
||||
phandle = dev_read_u32_default(dev, "phys", 0);
|
||||
phy_node = ofnode_get_by_phandle(phandle);
|
||||
if (!ofnode_valid(phy_node)) {
|
||||
dev_err(dev, "failed to found pcie-phy\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
||||
|
||||
ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get refclk clock phandle\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get phy reset phandle\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
phy_priv->ops = &pcie_phy_ops;
|
||||
priv->phy = phy_priv;
|
||||
|
||||
return 0;
|
||||
}
|
Loading…
Add table
Reference in a new issue