GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-26 17:11:32 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdef

Browse source 
This can avoid build error:
The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only
defined on the platforms that select the CONFIG_FOO, while
it's not defined on platforms that do not select the
CONFIG_FOO.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Hou Zhiqiang 2019-08-27 10:13:48 +00:00 • committed by Prabhakar Kushwaha
parent e4b8dd9b34
commit adc983b4d6
1 changed files with 36 additions and 33 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

69
drivers/pci/pcie_fsl.c
View file

@ -299,8 +299,9 @@ static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
out_be32(&pi->piwbear, 0); out_be32(&pi->piwbear, 0);
#endif #endif
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434)) #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
flag = 0; flag = 0;
#endif
flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
if (pf) if (pf)
@ -401,47 +402,47 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
fsl_pcie_init_atmu(pcie); fsl_pcie_init_atmu(pcie);
if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) { #ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
val_32 = 0; val_32 = 0;
fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
val_32 &= ~0x03; val_32 &= ~0x03;
fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
udelay(1); udelay(1);
} #endif
if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) { #ifdef CONFIG_FSL_PCIE_RESET
u16 ltssm; u16 ltssm;
int i; int i;
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
/* assert PCIe reset */
setbits_be32(&regs->pdb_stat, 0x08000000);
(void)in_be32(&regs->pdb_stat);
udelay(1000);
/* clear PCIe reset */
clrbits_be32(&regs->pdb_stat, 0x08000000);
asm("sync;isync");
for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
udelay(1000);
} else {
fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
if (ltssm == 1) {
/* assert PCIe reset */ /* assert PCIe reset */
setbits_be32(&regs->pdb_stat, 0x08000000); setbits_be32(&regs->pdb_stat, 0x08000000);
(void)in_be32(&regs->pdb_stat); (void)in_be32(&regs->pdb_stat);
udelay(1000); udelay(100);
/* clear PCIe reset */ /* clear PCIe reset */
clrbits_be32(&regs->pdb_stat, 0x08000000); clrbits_be32(&regs->pdb_stat, 0x08000000);
asm("sync;isync"); asm("sync;isync");
for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) for (i = 0; i < 100 &&
!fsl_pcie_link_up(pcie); i++)
udelay(1000); udelay(1000);
} else {
fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
if (ltssm == 1) {
/* assert PCIe reset */
setbits_be32(&regs->pdb_stat, 0x08000000);
(void)in_be32(&regs->pdb_stat);
udelay(100);
/* clear PCIe reset */
clrbits_be32(&regs->pdb_stat, 0x08000000);
asm("sync;isync");
for (i = 0; i < 100 &&
!fsl_pcie_link_up(pcie); i++)
udelay(1000);
}
} }
} }
#endif
if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) && #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
!fsl_pcie_link_up(pcie)) { if (!fsl_pcie_link_up(pcie)) {
serdes_corenet_t *srds_regs; serdes_corenet_t *srds_regs;
srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
@ -460,13 +461,15 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
udelay(1000); udelay(1000);
} }
} }
#endif
/* /*
* The Read-Only Write Enable bit defaults to 1 instead of 0. * The Read-Only Write Enable bit defaults to 1 instead of 0.
* Set to 0 to protect the read-only registers. * Set to 0 to protect the read-only registers.
*/ */
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815)) #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
clrbits_be32(&regs->dbi_ro_wr_en, 0x01); clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
#endif
/* /*
* Enable All Error Interrupts except * Enable All Error Interrupts except