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riscv: cpu: check and append L1 cache to cpu features
All cpu cores within FU540-C000 having split I/D caches. Set the L1 cache feature bit using the i-cache-size or d-cache-size as one of the property from device tree indicating that L1 cache is present on the cpu core. => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
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@ -35,6 +35,8 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
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int ret;
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struct clk clk;
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const char *mmu;
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u32 i_cache_size;
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u32 d_cache_size;
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/* First try getting the frequency from the assigned clock */
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ret = clk_get_by_index(dev, 0, &clk);
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@ -52,6 +54,16 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
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if (mmu)
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info->features |= BIT(CPU_FEAT_MMU);
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/* check if I cache is present */
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ret = dev_read_u32(dev, "i-cache-size", &i_cache_size);
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if (ret)
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/* if not found check if d-cache is present */
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ret = dev_read_u32(dev, "d-cache-size", &d_cache_size);
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/* if either I or D cache is present set L1 cache feature */
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if (!ret)
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info->features |= BIT(CPU_FEAT_L1_CACHE);
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return 0;
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}
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