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synced 2025-03-18 13:11:31 +00:00
nand_spl: change out_be32 to raw_writel and depend on subsequent sync
This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync Done with: sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` Signed-off-by: Matthew McClintock <msm@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
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02ea538ce9
commit
ae6beb24d7
3 changed files with 71 additions and 73 deletions
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@ -39,39 +39,37 @@ void sdram_init(void)
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/* mask off E bit */
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u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
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out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
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out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
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__raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
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__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
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__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
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if (ddr_freq_mhz < 700) {
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667);
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667);
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667);
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out_be32(&ddr->ddr_wrlvl_cntl,
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CONFIG_SYS_DDR_WRLVL_CONTROL_667);
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__raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
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__raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
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__raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
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__raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
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__raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
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__raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
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__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
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__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
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} else {
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800);
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800);
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800);
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out_be32(&ddr->ddr_wrlvl_cntl,
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CONFIG_SYS_DDR_WRLVL_CONTROL_800);
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__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
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__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
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__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
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__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
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__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
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__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
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__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
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__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
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}
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out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
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out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
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out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
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__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
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__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
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__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
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/* P1014 and it's derivatives support max 16bit DDR width */
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if (svr == SVR_P1014) {
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@ -37,28 +37,28 @@ void sdram_init(void)
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set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
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out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
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out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
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out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
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out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
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out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
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out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
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out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
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out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
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out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
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out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
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__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
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__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
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__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
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__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
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__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
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__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
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__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
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__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
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__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
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__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
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__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
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__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
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__raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl);
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__raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl);
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__raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1);
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__raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2);
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/* Set, but do not enable the memory */
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
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__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
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asm volatile("sync;isync");
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udelay(500);
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@ -36,32 +36,32 @@ void sdram_init(void)
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{
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ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
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out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
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__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
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#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
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out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
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out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
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__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
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#endif
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
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__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
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__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
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__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
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__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
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__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
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out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
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__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
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__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
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__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
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out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
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out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
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out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
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out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL);
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__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
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__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
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__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
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__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
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/* Set, but do not enable the memory */
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
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__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
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asm volatile("sync;isync");
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udelay(500);
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@ -92,13 +92,13 @@ void board_init_f(ulong bootflag)
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#ifndef CONFIG_QE
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/* init DDR3 reset signal */
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out_be32(&pgpio->gpdir, 0x02000000);
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out_be32(&pgpio->gpodr, 0x00200000);
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out_be32(&pgpio->gpdat, 0x00000000);
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__raw_writel(0x02000000, &pgpio->gpdir);
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__raw_writel(0x00200000, &pgpio->gpodr);
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__raw_writel(0x00000000, &pgpio->gpdat);
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udelay(1000);
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out_be32(&pgpio->gpdat, 0x00200000);
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__raw_writel(0x00200000, &pgpio->gpdat);
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udelay(1000);
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out_be32(&pgpio->gpdir, 0x00000000);
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__raw_writel(0x00000000, &pgpio->gpdir);
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#endif
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/* Initialize the DDR3 */
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