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Merge ../custodians

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This commit is contained in:
Wolfgang Denk 2008-02-15 00:27:11 +01:00
commit ae91a8055c
24 changed files with 317 additions and 612 deletions
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2
board/freescale/common/sys_eeprom.c
View file

@ -79,7 +79,7 @@ int mac_show(void)
/* Show Build Date, /* Show Build Date,
* BCD date values, as YYMMDDhhmmss. * BCD date values, as YYMMDDhhmmss.
*/ */
printf("Date 20%02x\/%02x\/%02x %02x:%02x:%02x\n", printf("Date 20%02x/%02x/%02x %02x:%02x:%02x\n",
mac_data.date[0], mac_data.date[0],
mac_data.date[1], mac_data.date[1],
mac_data.date[2], mac_data.date[2],

4
board/freescale/mpc8610hpcd/Makefile
View file

@ -27,9 +27,7 @@ endif
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
SOBJS := init.o COBJS := $(BOARD).o law.o
COBJS := $(BOARD).o
COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o

147
board/freescale/mpc8610hpcd/init.S
View file

@ -1,147 +0,0 @@
/*
* Copyright 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <config.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <mpc86xx.h>
#define LAWAR_TRGT_PCI1 0x00000000
#define LAWAR_TRGT_PCIE1 0x00200000
#define LAWAR_TRGT_PCIE2 0x00100000
#define LAWAR_TRGT_LBC 0x00400000
#define LAWAR_TRGT_DDR 0x00f00000
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
#else
#define LAWBAR1 0
#define LAWAR1 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
#endif
#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff)
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
#define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff)
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
#define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff)
#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
#define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff)
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff)
#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
.section .bootpg, "ax"
.globl law_entry
law_entry:
lis r7,CFG_CCSRBAR@h
ori r7,r7,CFG_CCSRBAR@l
addi r4,r7,0
addi r5,r7,0
/* Skip LAWAR0, start at LAWAR1 */
lis r6,LAWBAR1@h
ori r6,r6,LAWBAR1@l
stwu r6, 0xc28(r4)
lis r6,LAWAR1@h
ori r6,r6,LAWAR1@l
stwu r6, 0xc30(r5)
/* LAWBAR2, LAWAR2 */
lis r6,LAWBAR2@h
ori r6,r6,LAWBAR2@l
stwu r6, 0x20(r4)
lis r6,LAWAR2@h
ori r6,r6,LAWAR2@l
stwu r6, 0x20(r5)
/* LAWBAR3, LAWAR3 */
lis r6,LAWBAR3@h
ori r6,r6,LAWBAR3@l
stwu r6, 0x20(r4)
lis r6,LAWAR3@h
ori r6,r6,LAWAR3@l
stwu r6, 0x20(r5)
/* LAWBAR4, LAWAR4 */
lis r6,LAWBAR4@h
ori r6,r6,LAWBAR4@l
stwu r6, 0x20(r4)
lis r6,LAWAR4@h
ori r6,r6,LAWAR4@l
stwu r6, 0x20(r5)
/* LAWBAR5, LAWAR5 */
lis r6,LAWBAR5@h
ori r6,r6,LAWBAR5@l
stwu r6, 0x20(r4)
lis r6,LAWAR5@h
ori r6,r6,LAWAR5@l
stwu r6, 0x20(r5)
/* LAWBAR6, LAWAR6 */
lis r6,LAWBAR6@h
ori r6,r6,LAWBAR6@l
stwu r6, 0x20(r4)
lis r6,LAWAR6@h
ori r6,r6,LAWAR6@l
stwu r6, 0x20(r5)
/* LAWBAR7, LAWAR7 */
lis r6,LAWBAR7@h
ori r6,r6,LAWBAR7@l
stwu r6, 0x20(r4)
lis r6,LAWAR7@h
ori r6,r6,LAWAR7@l
stwu r6, 0x20(r5)
/* LAWBAR8, LAWAR8 */
lis r6,LAWBAR8@h
ori r6,r6,LAWBAR8@l
stwu r6, 0x20(r4)
lis r6,LAWAR8@h
ori r6,r6,LAWAR8@l
stwu r6, 0x20(r5)
/* LAWBAR9, LAWAR9 */
lis r6,LAWBAR9@h
ori r6,r6,LAWBAR9@l
stwu r6, 0x20(r4)
lis r6,LAWAR9@h
ori r6,r6,LAWAR9@l
stwu r6, 0x20(r5)
blr

44
board/freescale/mpc8610hpcd/law.c Normal file
View file

@ -0,0 +1,44 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
#endif
SET_LAW_ENTRY(2, CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(3, CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(6, CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
SET_LAW_ENTRY(7, CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(8, CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(9, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1)
};
int num_law_entries = ARRAY_SIZE(law_table);

1
board/freescale/mpc8610hpcd/u-boot.lds
View file

@ -51,7 +51,6 @@ SECTIONS
.text : .text :
{ {
cpu/mpc86xx/start.o (.text) cpu/mpc86xx/start.o (.text)
board/freescale/mpc8610hpcd/init.o (.bootpg)
cpu/mpc86xx/traps.o (.text) cpu/mpc86xx/traps.o (.text)
cpu/mpc86xx/interrupts.o (.text) cpu/mpc86xx/interrupts.o (.text)
cpu/mpc86xx/cpu_init.o (.text) cpu/mpc86xx/cpu_init.o (.text)

4
board/freescale/mpc8641hpcn/Makefile
View file

@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o COBJS := $(BOARD).o law.o
SOBJS := init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))

179
board/freescale/mpc8641hpcn/init.S
View file

@ -1,179 +0,0 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc86xx.h>
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
* 0xf800_0000 0xf80f_ffff CCSRBAR 1M
* 0xf810_0000 0xf81f_ffff PIXIS 1M
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
*
* Notes:
* CCSRBAR don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
#else
#define LAWBAR1 0
#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
#endif
#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
/*
* This is not so much the SDRAM map as it is the whole localbus map.
*/
#define LAWBAR4 ((0xf8100000>>12) & 0xffffff)
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
#define LAWBAR5 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
#define LAWBAR6 ((CFG_PCI2_IO_PHYS>>12) & 0xffffff)
#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
#else
#define LAWBAR8 0
#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
#endif
#define LAWBAR9 ((CFG_RIO_MEM_PHYS>>12) & 0xfffff)
#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
.section .bootpg, "ax"
.globl law_entry
law_entry:
lis r7,CFG_CCSRBAR@h
ori r7,r7,CFG_CCSRBAR@l
addi r4,r7,0
addi r5,r7,0
/* Skip LAWAR0, start at LAWAR1 */
lis r6,LAWBAR1@h
ori r6,r6,LAWBAR1@l
stwu r6, 0xc28(r4)
lis r6,LAWAR1@h
ori r6,r6,LAWAR1@l
stwu r6, 0xc30(r5)
/* LAWBAR2, LAWAR2 */
lis r6,LAWBAR2@h
ori r6,r6,LAWBAR2@l
stwu r6, 0x20(r4)
lis r6,LAWAR2@h
ori r6,r6,LAWAR2@l
stwu r6, 0x20(r5)
/* LAWBAR3, LAWAR3 */
lis r6,LAWBAR3@h
ori r6,r6,LAWBAR3@l
stwu r6, 0x20(r4)
lis r6,LAWAR3@h
ori r6,r6,LAWAR3@l
stwu r6, 0x20(r5)
/* LAWBAR4, LAWAR4 */
lis r6,LAWBAR4@h
ori r6,r6,LAWBAR4@l
stwu r6, 0x20(r4)
lis r6,LAWAR4@h
ori r6,r6,LAWAR4@l
stwu r6, 0x20(r5)
/* LAWBAR5, LAWAR5 */
lis r6,LAWBAR5@h
ori r6,r6,LAWBAR5@l
stwu r6, 0x20(r4)
lis r6,LAWAR5@h
ori r6,r6,LAWAR5@l
stwu r6, 0x20(r5)
/* LAWBAR6, LAWAR6 */
lis r6,LAWBAR6@h
ori r6,r6,LAWBAR6@l
stwu r6, 0x20(r4)
lis r6,LAWAR6@h
ori r6,r6,LAWAR6@l
stwu r6, 0x20(r5)
/* LAWBAR7, LAWAR7 */
lis r6,LAWBAR7@h
ori r6,r6,LAWBAR7@l
stwu r6, 0x20(r4)
lis r6,LAWAR7@h
ori r6,r6,LAWAR7@l
stwu r6, 0x20(r5)
/* LAWBAR8, LAWAR8 */
lis r6,LAWBAR8@h
ori r6,r6,LAWBAR8@l
stwu r6, 0x20(r4)
lis r6,LAWAR8@h
ori r6,r6,LAWAR8@l
stwu r6, 0x20(r5)
/* LAWBAR9, LAWAR9 */
lis r6,LAWBAR9@h
ori r6,r6,LAWBAR9@l
stwu r6, 0x20(r4)
lis r6,LAWAR9@h
ori r6,r6,LAWAR9@l
stwu r6, 0x20(r5)
blr

64
board/freescale/mpc8641hpcn/law.c Normal file
View file

@ -0,0 +1,64 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
* 0xf800_0000 0xf80f_ffff CCSRBAR 1M
* 0xf810_0000 0xf81f_ffff PIXIS 1M
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
*
* Notes:
* CCSRBAR don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
#endif
SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(5, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(6, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(7, (CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
#endif
SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
int num_law_entries = ARRAY_SIZE(law_table);

1
board/freescale/mpc8641hpcn/u-boot.lds
View file

@ -51,7 +51,6 @@ SECTIONS
.text : .text :
{ {
cpu/mpc86xx/start.o (.text) cpu/mpc86xx/start.o (.text)
board/freescale/mpc8641hpcn/init.o (.bootpg)
cpu/mpc86xx/traps.o (.text) cpu/mpc86xx/traps.o (.text)
cpu/mpc86xx/interrupts.o (.text) cpu/mpc86xx/interrupts.o (.text)
cpu/mpc86xx/cpu_init.o (.text) cpu/mpc86xx/cpu_init.o (.text)

3
board/sbc8641d/Makefile
View file

@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o COBJS := $(BOARD).o law.o
SOBJS := init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))

192
board/sbc8641d/init.S
View file

@ -1,192 +0,0 @@
/*
* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
* Copyright 2007 Embedded Specialties, Inc.
* Joe Hamman joe.hamman@embeddedspecialties.com
*
* Copyright 2004 Freescale Semiconductor.
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc86xx.h>
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x0fff_ffff DDR1 256M
* 0x1000_0000 0x1fff_ffff DDR2 256M
* 0xe000_0000 0xffff_ffff LBC 512M
*
* Notes:
* CCSRBAR doesn't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
# DDR Bank 1
# #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
# #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
# DDR Bank 2
# #define LAWBAR2 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
# #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
# LBC
# #define LAWBAR3 ((0xe0000000>>12) & 0xffffff)
# #define LAWAR3 (LAWAR_EN & (LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)))
/*
* LAW (Local Access Window) configuration:
*
* 0x0000_0000 DDR 256M
* 0x1000_0000 DDR2 256M
* 0x8000_0000 PCI1 MEM 512M
* 0xa000_0000 PCI2 MEM 512M
* 0xc000_0000 RapidIO 512M
* 0xe200_0000 PCI1 IO 16M
* 0xe300_0000 PCI2 IO 16M
* 0xf800_0000 CCSRBAR 2M
* 0xfe00_0000 FLASH (boot bank) 32M
*
*/
#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
#define LAWBAR4 ((0xf8000000>>12) & 0xffffff)
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff)
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
#define LAWBAR8 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
.section .bootpg, "ax"
.globl law_entry
law_entry:
lis r7,CFG_CCSRBAR@h
ori r7,r7,CFG_CCSRBAR@l
addi r4,r7,0
addi r5,r7,0
/* Skip LAWAR0, start at LAWAR1 */
lis r6,LAWBAR1@h
ori r6,r6,LAWBAR1@l
stwu r6, 0xc28(r4)
lis r6,LAWAR1@h
ori r6,r6,LAWAR1@l
stwu r6, 0xc30(r5)
/* LAWBAR2, LAWAR2 */
lis r6,LAWBAR2@h
ori r6,r6,LAWBAR2@l
stwu r6, 0x20(r4)
lis r6,LAWAR2@h
ori r6,r6,LAWAR2@l
stwu r6, 0x20(r5)
/* LAWBAR3, LAWAR3 */
lis r6,LAWBAR3@h
ori r6,r6,LAWBAR3@l
stwu r6, 0x20(r4)
lis r6,LAWAR3@h
ori r6,r6,LAWAR3@l
stwu r6, 0x20(r5)
/* LAWBAR4, LAWAR4 */
lis r6,LAWBAR4@h
ori r6,r6,LAWBAR4@l
stwu r6, 0x20(r4)
lis r6,LAWAR4@h
ori r6,r6,LAWAR4@l
stwu r6, 0x20(r5)
/* LAWBAR5, LAWAR5 */
lis r6,LAWBAR5@h
ori r6,r6,LAWBAR5@l
stwu r6, 0x20(r4)
lis r6,LAWAR5@h
ori r6,r6,LAWAR5@l
stwu r6, 0x20(r5)
/* LAWBAR6, LAWAR6 */
lis r6,LAWBAR6@h
ori r6,r6,LAWBAR6@l
stwu r6, 0x20(r4)
lis r6,LAWAR6@h
ori r6,r6,LAWAR6@l
stwu r6, 0x20(r5)
/* LAWBAR7, LAWAR7 */
lis r6,LAWBAR7@h
ori r6,r6,LAWBAR7@l
stwu r6, 0x20(r4)
lis r6,LAWAR7@h
ori r6,r6,LAWAR7@l
stwu r6, 0x20(r5)
/* LAWBAR8, LAWAR8 */
lis r6,LAWBAR8@h
ori r6,r6,LAWBAR8@l
stwu r6, 0x20(r4)
lis r6,LAWAR8@h
ori r6,r6,LAWAR8@l
stwu r6, 0x20(r5)
/* LAWBAR9, LAWAR9 */
lis r6,LAWBAR9@h
ori r6,r6,LAWBAR9@l
stwu r6, 0x20(r4)
lis r6,LAWAR9@h
ori r6,r6,LAWAR9@l
stwu r6, 0x20(r5)
blr

58
board/sbc8641d/law.c Normal file
View file

@ -0,0 +1,58 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* LAW (Local Access Window) configuration:
*
* 0x0000_0000 DDR 256M
* 0x1000_0000 DDR2 256M
* 0x8000_0000 PCI1 MEM 512M
* 0xa000_0000 PCI2 MEM 512M
* 0xc000_0000 RapidIO 512M
* 0xe200_0000 PCI1 IO 16M
* 0xe300_0000 PCI2 IO 16M
* 0xf800_0000 CCSRBAR 2M
* 0xfe00_0000 FLASH (boot bank) 32M
*
*/
struct law_entry law_table[] = {
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(4, 0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(5, CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(6, CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(7, 0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
SET_LAW_ENTRY(9, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
int num_law_entries = ARRAY_SIZE(law_table);

1
board/sbc8641d/u-boot.lds
View file

@ -51,7 +51,6 @@ SECTIONS
.text : .text :
{ {
cpu/mpc86xx/start.o (.text) cpu/mpc86xx/start.o (.text)
board/sbc8641d/init.o (.bootpg)
cpu/mpc86xx/traps.o (.text) cpu/mpc86xx/traps.o (.text)
cpu/mpc86xx/interrupts.o (.text) cpu/mpc86xx/interrupts.o (.text)
cpu/mpc86xx/cpu_init.o (.text) cpu/mpc86xx/cpu_init.o (.text)

7
common/cmd_reginfo.c
View file

@ -31,6 +31,8 @@
#include <mpc5xx.h> #include <mpc5xx.h>
#elif defined (CONFIG_MPC5200) #elif defined (CONFIG_MPC5200)
#include <mpc5xxx.h> #include <mpc5xxx.h>
#elif defined (CONFIG_MPC86xx)
extern void mpc86xx_reginfo(void);
#endif #endif
int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@ -329,6 +331,8 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG); *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
printf ("\tSDRAMCS1: %08X\n", printf ("\tSDRAMCS1: %08X\n",
*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG); *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
#elif defined(CONFIG_MPC86xx)
mpc86xx_reginfo();
#elif defined(CONFIG_BLACKFIN) #elif defined(CONFIG_BLACKFIN)
puts("\nSystem Configuration registers\n"); puts("\nSystem Configuration registers\n");
@ -369,7 +373,8 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL()); bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
# endif # endif
#endif /* CONFIG_MPC5200 */ #endif /* CONFIG_BLACKFIN */
return 0; return 0;
} }

24
cpu/mpc86xx/cpu.c
View file

@ -27,6 +27,7 @@
#include <command.h> #include <command.h>
#include <asm/cache.h> #include <asm/cache.h>
#include <mpc86xx.h> #include <mpc86xx.h>
#include <asm/fsl_law.h>
#if defined(CONFIG_OF_FLAT_TREE) #if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h> #include <ft_build.h>
@ -324,6 +325,27 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL) if (p != NULL)
memcpy(p, bd->bi_enet3addr, 6); memcpy(p, bd->bi_enet3addr, 6);
#endif #endif
#endif /* CONFIG_OF_FLAT_TREE */
/*
* Print out the state of various machine registers.
* Currently prints out LAWs and BR0/OR0
*/
void mpc86xx_reginfo(void)
{
immap_t *immap = (immap_t *)CFG_IMMR;
ccsr_lbc_t *lbc = &immap->im_lbc;
print_laws();
printf ("Local Bus Controller Registers\n"
"\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
} }
#endif

7
cpu/mpc86xx/cpu_init.c
View file

@ -49,6 +49,10 @@ void cpu_init_f(void)
/* Clear initial global data */ /* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t)); memset ((void *) gd, 0, sizeof (gd_t));
#ifdef CONFIG_FSL_LAW
init_laws();
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size * addresses - these have to be modified later when FLASH size
* has been determined * has been determined
@ -114,5 +118,8 @@ void cpu_init_f(void)
*/ */
int cpu_init_r(void) int cpu_init_r(void)
{ {
#ifdef CONFIG_FSL_LAW
disable_law(0);
#endif
return 0; return 0;
} }

37
cpu/mpc86xx/spd_sdram.c
View file

@ -27,7 +27,7 @@
#include <i2c.h> #include <i2c.h>
#include <spd.h> #include <spd.h>
#include <asm/mmu.h> #include <asm/mmu.h>
#include <asm/fsl_law.h>
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void dma_init(void); extern void dma_init(void);
@ -1123,7 +1123,6 @@ spd_sdram(void)
int memsize_ddr1 = 0; int memsize_ddr1 = 0;
unsigned int law_size_ddr1; unsigned int law_size_ddr1;
volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
#ifdef CONFIG_DDR_INTERLEAVE #ifdef CONFIG_DDR_INTERLEAVE
volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
#endif #endif
@ -1179,12 +1178,9 @@ spd_sdram(void)
/* /*
* Set up LAWBAR for DDR 1 space. * Set up LAWBAR for DDR 1 space.
*/ */
mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); #ifdef CONFIG_FSL_LAW
mcm->lawar1 = (LAWAR_EN set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
| LAWAR_TRGT_IF_DDR_INTERLEAVED #endif
| (LAWAR_SIZE & law_size_interleaved));
debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
debug("Interleaved memory size is 0x%08lx\n", memsize_total); debug("Interleaved memory size is 0x%08lx\n", memsize_total);
#ifdef CONFIG_DDR_INTERLEAVE #ifdef CONFIG_DDR_INTERLEAVE
@ -1239,12 +1235,9 @@ spd_sdram(void)
/* /*
* Set up LAWBAR for DDR 1 space. * Set up LAWBAR for DDR 1 space.
*/ */
mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); #ifdef CONFIG_FSL_LAW
mcm->lawar1 = (LAWAR_EN set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
| LAWAR_TRGT_IF_DDR1 #endif
| (LAWAR_SIZE & law_size_ddr1));
debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
} }
#if (CONFIG_NUM_DDR_CONTROLLERS > 1) #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
@ -1269,17 +1262,11 @@ spd_sdram(void)
/* /*
* Set up LAWBAR for DDR 2 space. * Set up LAWBAR for DDR 2 space.
*/ */
if (ddr1_enabled) #ifdef CONFIG_FSL_LAW
mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12) set_law(8,
& 0xfffff); (ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
else law_size_ddr2, LAW_TRGT_IF_DDR_2);
mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); #endif
mcm->lawar8 = (LAWAR_EN
| LAWAR_TRGT_IF_DDR2
| (LAWAR_SIZE & law_size_ddr2));
debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
} }
debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2); debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);

113
cpu/mpc86xx/start.S
View file

@ -235,17 +235,8 @@ in_flash:
bl enable_ext_addr bl enable_ext_addr
/* setup the bats */ /* setup the bats */
bl setup_bats bl early_bats
sync
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
/* setup ccsrbar */
bl setup_ccsrbar
#endif
/* setup the law entries */
bl law_entry
sync
/* /*
* Cache must be enabled here for stack-in-cache trick. * Cache must be enabled here for stack-in-cache trick.
* This means we need to enable the BATS. * This means we need to enable the BATS.
@ -282,6 +273,16 @@ in_flash:
GET_GOT /* initialize GOT access */ GET_GOT /* initialize GOT access */
/* setup the rest of the bats */
bl setup_bats
bl clear_tlbs
sync
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
/* setup ccsrbar */
bl setup_ccsrbar
#endif
/* run low-level CPU init code (from Flash) */ /* run low-level CPU init code (from Flash) */
bl cpu_init_f bl cpu_init_f
sync sync
@ -359,6 +360,7 @@ invalidate_bats:
/* setup_bats - set them up to some initial state */ /* setup_bats - set them up to some initial state */
/* Skip any BATS setup in early_bats */
.globl setup_bats .globl setup_bats
setup_bats: setup_bats:
@ -454,42 +456,6 @@ setup_bats:
mtspr DBAT4U, r3 mtspr DBAT4U, r3
isync isync
/* IBAT 5 */
addis r4, r0, CFG_IBAT5L@h
ori r4, r4, CFG_IBAT5L@l
addis r3, r0, CFG_IBAT5U@h
ori r3, r3, CFG_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
isync
/* DBAT 5 */
addis r4, r0, CFG_DBAT5L@h
ori r4, r4, CFG_DBAT5L@l
addis r3, r0, CFG_DBAT5U@h
ori r3, r3, CFG_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
isync
/* IBAT 6 */
addis r4, r0, CFG_IBAT6L@h
ori r4, r4, CFG_IBAT6L@l
addis r3, r0, CFG_IBAT6U@h
ori r3, r3, CFG_IBAT6U@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
isync
/* DBAT 6 */
addis r4, r0, CFG_DBAT6L@h
ori r4, r4, CFG_DBAT6L@l
addis r3, r0, CFG_DBAT6U@h
ori r3, r3, CFG_DBAT6U@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
isync
/* IBAT 7 */ /* IBAT 7 */
addis r4, r0, CFG_IBAT7L@h addis r4, r0, CFG_IBAT7L@h
ori r4, r4, CFG_IBAT7L@l ori r4, r4, CFG_IBAT7L@l
@ -508,18 +474,65 @@ setup_bats:
mtspr DBAT7U, r3 mtspr DBAT7U, r3
isync isync
1: sync
addis r3, 0, 0x0000 blr
addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
/*
* early_bats:
*
* Set up bats needed early on - this is usually the BAT for the
* stack-in-cache and the Flash
*/
.globl early_bats
early_bats:
/* IBAT 5 */
lis r4, CFG_IBAT5L@h
ori r4, r4, CFG_IBAT5L@l
lis r3, CFG_IBAT5U@h
ori r3, r3, CFG_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
isync isync
/* DBAT 5 */
lis r4, CFG_DBAT5L@h
ori r4, r4, CFG_DBAT5L@l
lis r3, CFG_DBAT5U@h
ori r3, r3, CFG_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
isync
/* IBAT 6 */
lis r4, CFG_IBAT6L@h
ori r4, r4, CFG_IBAT6L@l
lis r3, CFG_IBAT6U@h
ori r3, r3, CFG_IBAT6U@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
isync
/* DBAT 6 */
lis r4, CFG_DBAT6L@h
ori r4, r4, CFG_DBAT6L@l
lis r3, CFG_DBAT6U@h
ori r3, r3, CFG_DBAT6U@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
isync
blr
.globl clear_tlbs
clear_tlbs:
addis r3, 0, 0x0000
addis r5, 0, 0x4
isync
tlblp: tlblp:
tlbie r3 tlbie r3
sync sync
addi r3, r3, 0x1000 addi r3, r3, 0x1000
cmp 0, 0, r3, r5 cmp 0, 0, r3, r5
blt tlblp blt tlblp
blr blr
.globl enable_addr_trans .globl enable_addr_trans

19
drivers/misc/fsl_law.c
View file

@ -28,6 +28,7 @@
#include <asm/io.h> #include <asm/io.h>
#define LAWAR_EN 0x80000000 #define LAWAR_EN 0x80000000
#define FSL_HW_NUM_LAWS 10 /* number of LAWs in the hw implementation */
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{ {
@ -53,6 +54,24 @@ void disable_law(u8 idx)
return; return;
} }
void print_laws(void)
{
volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08);
volatile u32 *lawbar = base;
volatile u32 *lawar = base + 2;
int i;
printf("\nLocal Access Window Configuration\n");
for(i = 0; i < FSL_HW_NUM_LAWS; i++) {
printf("\tLAWBAR%d : 0x%08x, LAWAR%d : 0x%08x\n",
i, in_be32(lawbar), i, in_be32(lawar));
lawbar += 8;
lawar += 8;
}
return;
}
void init_laws(void) void init_laws(void)
{ {
int i; int i;

1
include/asm-ppc/fsl_law.h
View file

@ -73,6 +73,7 @@ struct law_entry {
extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id); extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern void disable_law(u8 idx); extern void disable_law(u8 idx);
extern void init_laws(void); extern void init_laws(void);
extern void print_laws(void);
/* define in board code */ /* define in board code */
extern struct law_entry law_table[]; extern struct law_entry law_table[];

5
include/asm-ppc/immap_86xx.h
View file

@ -1330,4 +1330,9 @@ typedef struct immap {
extern immap_t *immr; extern immap_t *immr;
#define CFG_MPC86xx_DDR_OFFSET (0x2000)
#define CFG_MPC86xx_DDR_ADDR (CFG_IMMR + CFG_MPC86xx_DDR_OFFSET)
#define CFG_MPC86xx_DDR2_OFFSET (0x6000)
#define CFG_MPC86xx_DDR2_ADDR (CFG_IMMR + CFG_MPC86xx_DDR2_OFFSET)
#endif /*__IMMAP_86xx__*/ #endif /*__IMMAP_86xx__*/

2
include/configs/MPC8610HPCD.h
View file

@ -42,6 +42,7 @@
#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
@ -314,6 +315,7 @@
#define CONFIG_NET_MULTI #define CONFIG_NET_MULTI
#define CONFIG_CMD_NET #define CONFIG_CMD_NET
#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_CMD_REGINFO
#define CONFIG_ULI526X #define CONFIG_ULI526X
#ifdef CONFIG_ULI526X #ifdef CONFIG_ULI526X

2
include/configs/MPC8641HPCN.h
View file

@ -49,6 +49,7 @@
#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
@ -536,6 +537,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CMD_PING #define CONFIG_CMD_PING
#define CONFIG_CMD_I2C #define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO
#if defined(CFG_RAMBOOT) #if defined(CFG_RAMBOOT)
#undef CONFIG_CMD_ENV #undef CONFIG_CMD_ENV

2
include/configs/sbc8641d.h
View file

@ -53,6 +53,7 @@
#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
@ -479,6 +480,7 @@
#include <config_cmd_default.h> #include <config_cmd_default.h>
#define CONFIG_CMD_PING #define CONFIG_CMD_PING
#define CONFIG_CMD_I2C #define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI #define CONFIG_CMD_PCI