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Merge git://git.denx.de/u-boot-rockchip

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This commit is contained in:
Tom Rini 2017-04-16 22:08:13 -04:00
commit af8ef2ed21
24 changed files with 439 additions and 15 deletions
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2
arch/arm/dts/Makefile
View file

@ -29,12 +29,12 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-sdk.dtb \
rk3188-radxarock.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
rk3288-firefly.dtb \
rk3288-miqi.dtb \
rk3288-popmetal.dtb \
rk3188-radxarock.dtb \
rk3288-rock2-square.dtb \
rk3288-tinker.dtb \
rk3288-veyron-jerry.dtb \

39
arch/arm/dts/rk3399-evb.dts
View file

@ -30,6 +30,13 @@
status = "okay";
};
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vccsys";
regulator-boot-on;
regulator-always-on;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
@ -51,6 +58,7 @@
regulator-name = "vcc5v0_host";
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
};
};
&emmc_phy {
@ -112,6 +120,37 @@
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <50>;
i2c-scl-rising-time-ns = <100>;
u-boot,dm-pre-reloc;
rk808: pmic@1b {
compatible = "rockchip,rk808";
clock-output-names = "xin32k", "wifibt_32kin";
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
reg = <0x1b>;
rockchip,system-power-controller;
#clock-cells = <1>;
u-boot,dm-pre-reloc;
status = "okay";
vcc12-supply = <&vcc3v3_sys>;
regulators {
vcc33_lcd: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc33_lcd";
};
};
};
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {

3
arch/arm/dts/rk3399-puma.dts
View file

@ -1,7 +1,7 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
@ -91,7 +91,6 @@
&sdmmc {
u-boot,dm-pre-reloc;
bus-width = <4>;
fifo-mode; /* until we fix DMA in SPL */
status = "okay";
};

16
arch/arm/dts/rk3399.dtsi
View file

@ -26,6 +26,7 @@
serial4 = &uart4;
mmc0 = &sdhci;
mmc1 = &sdmmc;
i2c0 = &i2c0;
};
cpus {
@ -668,6 +669,21 @@
status = "disabled";
};
i2c0: i2c@ff3c0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3c0000 0x0 0x1000>;
assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pinctrl: pinctrl {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-pinctrl";

8
arch/arm/include/asm/arch-rockchip/grf_rk3399.h
View file

@ -337,6 +337,14 @@ enum {
GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT,
GRF_SPI2TPM_CSN0 = 1,
/* GRF_GPIO2C_IOMUX */
GRF_GPIO2C0_SEL_SHIFT = 0,
GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT,
GRF_UART0BT_SIN = 1,
GRF_GPIO2C1_SEL_SHIFT = 2,
GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT,
GRF_UART0BT_SOUT = 1,
/* GRF_GPIO3A_IOMUX */
GRF_GPIO3A0_SEL_SHIFT = 0,
GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT,

2
arch/arm/mach-rockchip/Kconfig
View file

@ -18,6 +18,7 @@ config ROCKCHIP_RK3188
select SUPPORT_TPL
select SPL
select TPL
select BOARD_LATE_INIT
select ROCKCHIP_BROM_HELPER
help
The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
@ -55,6 +56,7 @@ config ROCKCHIP_RK3399
select SPL
select SPL_SEPARATE_BSS
select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.

18
arch/arm/mach-rockchip/rk3188-board.c
View file

@ -11,6 +11,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/grf_rk3188.h>
#include <asm/arch/periph.h>
#include <asm/arch/pmu_rk3288.h>
#include <asm/arch/boot_mode.h>
@ -19,6 +20,23 @@
DECLARE_GLOBAL_DATA_PTR;
int board_late_init(void)
{
struct rk3188_grf *grf;
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (IS_ERR(grf)) {
error("grf syscon returned %ld\n", PTR_ERR(grf));
} else {
/* enable noc remap to mimic legacy loaders */
rk_clrsetreg(&grf->soc_con0,
NOC_REMAP_MASK << NOC_REMAP_SHIFT,
NOC_REMAP_MASK << NOC_REMAP_SHIFT);
}
return 0;
}
int board_init(void)
{
#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)

43
arch/arm/mach-rockchip/rk3399-board-spl.c
View file

@ -156,19 +156,24 @@ void secure_timer_init(void)
writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
}
#define GRF_EMMCCORE_CON11 0xff77f02c
void board_init_f(ulong dummy)
{
struct udevice *pinctrl;
struct udevice *dev;
int ret;
#define SGRF_DDR_RGN_CON16 0xff330040
/* Example code showing how to enable the debug UART on RK3288 */
void board_debug_uart_init(void)
{
#include <asm/arch/grf_rk3399.h>
/* Enable early UART2 channel C on the RK3399 */
#define GRF_BASE 0xff770000
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
/* Enable early UART0 on the RK3399 */
rk_clrsetreg(&grf->gpio2c_iomux,
GRF_GPIO2C0_SEL_MASK,
GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
rk_clrsetreg(&grf->gpio2c_iomux,
GRF_GPIO2C1_SEL_MASK,
GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
#else
/* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C3_SEL_MASK,
GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
@ -179,6 +184,16 @@ void board_init_f(ulong dummy)
rk_clrsetreg(&grf->soc_con7,
GRF_UART_DBG_SEL_MASK,
GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
#endif
}
#define GRF_EMMCCORE_CON11 0xff77f02c
void board_init_f(ulong dummy)
{
struct udevice *pinctrl;
struct udevice *dev;
int ret;
#define EARLY_UART
#ifdef EARLY_UART
/*
@ -201,6 +216,17 @@ void board_init_f(ulong dummy)
hang();
}
/*
* Disable DDR security regions.
*
* As we are entered from the BootROM, the region from
* 0x0 through 0xfffff (i.e. the first MB of memory) will
* be protected. This will cause issues with the DW_MMC
* driver, which tries to DMA from/to the stack (likely)
* located in this range.
*/
rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0);
secure_timer_init();
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
@ -238,6 +264,7 @@ void spl_board_init(void)
#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
back_to_bootrom();
#endif
return;
err:
printf("spl_board_init: Error %d\n", ret);

19
arch/arm/mach-rockchip/rk3399/Kconfig
View file

@ -10,6 +10,24 @@ config TARGET_EVB_RK3399
with full function and phisical connectors support like type-C ports,
usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
config TARGET_PUMA_RK3399
bool "Theobroma Systems RK3399-Q7 (Puma)"
help
The RK3399-Q7 (Puma) is a system-on-module (designed and
marketed by Theobroma Systems) featuring the Rockchip RK3399
in a Qseven-compatible form-factor (running of a single 5V
supply and exposing its external interfaces on a MXM-230
connector).
Key features of the RK3399-Q7 include:
* on-module USB 3.0 hub (2x USB 3.0 host + 1x USB 2.0 host)
* USB 3.0 dual-role
* on-module Micrel KSZ9031 GbE PHY
* on-module eMMC (up to 256GB configurations available)
* on-module DDR3 (1GB, 2GB and 4GB configurations available)
* HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI
* SPI, I2C, I2S, UART, GPIO, ...
endchoice
config SYS_SOC
@ -19,5 +37,6 @@ config SYS_MALLOC_F_LEN
default 0x0800
source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"
endif

1
arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
View file

@ -14,6 +14,7 @@ static const struct udevice_id rk3399_syscon_ids[] = {
{ .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF },
{ .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC },
{ }
};
U_BOOT_DRIVER(syscon_rk3399) = {

15
board/theobroma-systems/puma_rk3399/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_PUMA_RK3399
config SYS_BOARD
default "puma_rk3399"
config SYS_VENDOR
default "theobroma-systems"
config SYS_CONFIG_NAME
default "puma_rk3399"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

10
board/theobroma-systems/puma_rk3399/MAINTAINERS Normal file
View file

@ -0,0 +1,10 @@
PUMA-RK3399
M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
M: Klaus Goger <klaus.goger@theobroma-systems.com>
S: Maintained
F: board/theobroma-systems/puma_rk3399
F: include/configs/puma_rk3399.h
F: arch/arm/dts/rk3399-puma.dts
F: configs/puma-rk3399_defconfig
W: https://www.theobroma-systems.com/rk3399-q7/tech-specs
T: git git://git.theobroma-systems.com/puma-u-boot.git

7
board/theobroma-systems/puma_rk3399/Makefile Normal file
View file

@ -0,0 +1,7 @@
#
# (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += puma-rk3399.o

73
board/theobroma-systems/puma_rk3399/README Normal file
View file

@ -0,0 +1,73 @@
Introduction
============
The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip
RK3399 in a Qseven-compatible form-factor.
RK3399-Q7 features:
* CPU: ARMv8 64bit Big-Little architecture,
* Big: dual-core Cortex-A72
* Little: quad-core Cortex-A53
* IRAM: 200KB
* DRAM: 4GB-128MB dual-channel
* eMMC: onboard eMMC
* SD/MMC
* GbE (onboard Micrel KSZ9031) Gigabit ethernet PHY
* USB:
* USB3.0 dual role port
* 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub
* Display: HDMI/eDP/MIPI
* Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF)
* NOR Flash: onboard SPI NOR
* Companion Controller: onboard additional Cortex-M0 microcontroller
* RTC
* fan controller
* CAN
Here is the step-by-step to boot to U-Boot on rk3399.
Get the Source and build ATF/Cortex-M0 binaries
===============================================
> git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
> git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
Compile the ATF
===============
> cd arm-trusted-firmware
> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
> cp build/rk3399/release/bl31.bin ../u-boot
Compile the M0 firmware
=======================
> cd ../rk3399-cortex-m0
> make CROSS_COMPILE=arm-cortex_m0-eabi-
> cp rk3399m0.bin ../u-boot
Compile the U-Boot
==================
> cd ../u-boot
> make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all
Package the image
=================
> tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl.img
> tools/mkimage -f board/theobroma/puma_rk3399/fit_spl_atf.its \
-E rk3399_bl3x.itb
Flash the image
===============
Copy the SPL to offset 32k and the FIT image containing the payloads
(U-Boot proper, ATF, M0 Firmware, devicetree) to offset 256k on a SD
card.
> dd if=spl.img of=/dev/sdb seek=64
> dd if=rk3399_bl3x.itb of=/dev/sdb seek=512
After powering up the board (with the inserted SD card), you should see
a U-Boot console on UART0 (115200n8).

57
board/theobroma-systems/puma_rk3399/fit_spl_atf.its Normal file
View file

@ -0,0 +1,57 @@
/*
* Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
*
* Minimal dts for a SPL FIT image payload.
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
/ {
description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB";
#address-cells = <1>;
images {
uboot@1 {
description = "U-Boot (64-bit)";
data = /incbin/("../../../u-boot-nodtb.bin");
type = "standalone";
arch = "arm64";
compression = "none";
load = <0x00200000>;
};
atf@1 {
description = "ARM Trusted Firmware";
data = /incbin/("../../../bl31.bin");
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x00001000>;
entry = <0x00001000>;
};
pmu@1 {
description = "Cortex-M0 firmware";
data = /incbin/("../../../rk3399m0.bin");
type = "pmu-firmware";
compression = "none";
load = <0xff8c0000>;
};
fdt@1 {
description = "RK3399-Q7 (Puma) flat device-tree";
data = /incbin/("../../../u-boot.dtb");
type = "flat_dt";
compression = "none";
};
};
configurations {
default = "conf@1";
conf@1 {
description = "Theobroma Systems RK3399-Q7 (Puma) SoM";
firmware = "uboot@1";
loadables = "atf@1";
fdt = "fdt@1";
};
};
};

71
board/theobroma-systems/puma_rk3399/puma-rk3399.c Normal file
View file

@ -0,0 +1,71 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
#include <asm/arch/periph.h>
#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
struct udevice *pinctrl, *regulator;
int ret;
/*
* The PWM does not have decicated interrupt number in dts and can
* not get periph_id by pinctrl framework, so let's init them here.
* The PWM2 and PWM3 are for pwm regulators.
*/
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("%s: Cannot find pinctrl device\n", __func__);
goto out;
}
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2);
if (ret) {
debug("%s PWM2 pinctrl init fail!\n", __func__);
goto out;
}
/* rk3399 need to init vdd_center to get the correct output voltage */
ret = regulator_get_by_platname("vdd_center", &regulator);
if (ret)
debug("%s: Cannot get vdd_center regulator\n", __func__);
ret = regulator_get_by_platname("vcc5v0_host", &regulator);
if (ret) {
debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
goto out;
}
ret = regulator_set_enable(regulator, true);
if (ret) {
debug("%s vcc5v0-host-en set fail!\n", __func__);
goto out;
}
out:
return 0;
}
int dram_init(void)
{
gd->ram_size = 0x80000000;
return 0;
}
int dram_init_banksize(void)
{
/* Reserve 0x200000 for ATF bl31 */
gd->bd->bi_dram[0].start = 0x200000;
gd->bd->bi_dram[0].size = 0x7e000000;
return 0;
}

6
configs/evb-rk3399_defconfig
View file

@ -60,3 +60,9 @@ CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_ERRNO_STR=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_CHILDREN=y
CONFIG_SPL_PMIC_CHILDREN=y
CONFIG_PMIC_RK808=y
CONFIG_REGULATOR_RK808=y

3
configs/puma-rk3399_defconfig
View file

@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TARGET_PUMA_RK3399=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
@ -11,7 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma"
CONFIG_FIT=y
CONFIG_SPL_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="board/rockchip/evb_rk3399/fit_spl_atf.its"
CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set

1
drivers/i2c/rk_i2c.c
View file

@ -383,6 +383,7 @@ static const struct udevice_id rockchip_i2c_ids[] = {
{ .compatible = "rockchip,rk3066-i2c" },
{ .compatible = "rockchip,rk3188-i2c" },
{ .compatible = "rockchip,rk3288-i2c" },
{ .compatible = "rockchip,rk3399-i2c" },
{ }
};

15
drivers/sysreset/sysreset_rk3188.c
View file

@ -7,21 +7,36 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <syscon.h>
#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3188.h>
#include <asm/arch/grf_rk3188.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk3188_cru *cru = rockchip_get_cru();
struct rk3188_grf *grf;
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
case SYSRESET_WARM:
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (IS_ERR(grf))
return -EPROTONOSUPPORT;
/*
* warm-reset keeps the remap value,
* so make sure it's disabled.
*/
rk_clrsetreg(&grf->soc_con0,
NOC_REMAP_MASK << NOC_REMAP_SHIFT,
0 << NOC_REMAP_SHIFT);
rk_clrreg(&cru->cru_mode_con, 0xffff);
writel(0xeca8, &cru->cru_glb_srst_snd_value);
break;

27
include/configs/puma_rk3399.h Normal file
View file

@ -0,0 +1,27 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PUMA_RK3399_H
#define __PUMA_RK3399_H
#include <configs/rk3399_common.h>
/*
* SPL @ 32kB for ~130kB
* ENV @ 240KB for 8kB
* FIT payload (ATF, U-Boot, FDT) @ 256kB
*/
#undef CONFIG_ENV_OFFSET
#define CONFIG_ENV_OFFSET (240 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
#define SDRAM_BANK_SIZE (2UL << 30)
#define CONFIG_SYS_WHITE_ON_BLACK
#endif

4
include/configs/rk3399_common.h
View file

@ -57,8 +57,8 @@
#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00000000\0" \
"pxefile_addr_r=0x00100000\0" \
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
"fdt_addr_r=0x01f00000\0" \
"kernel_addr_r=0x02000000\0" \
"ramdisk_addr_r=0x04000000\0"

9
include/configs/rockchip-common.h
View file

@ -12,11 +12,20 @@
#include <config_distro_defaults.h>
/* First try to boot from SD (index 0), then eMMC (index 1 */
#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(USB, usb, 0) \
func(PXE, pxe, na) \
func(DHCP, dchp, na)
#else
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(PXE, pxe, na) \
func(DHCP, dchp, na)
#endif
#define CONFIG_RANDOM_UUID
#define PARTS_DEFAULT \

5
include/configs/tinker_rk3288.h
View file

@ -13,7 +13,10 @@
#undef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1)
func(MMC, mmc, 1) \
func(USB, usb, 0) \
func(PXE, pxe, na) \
func(DHCP, dchp, na)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1