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ARM: dts: k3-am642-sk: Disable cpsw_port1 in SPL

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ROM supports cpsw_port2 for Ethernet boot and SPL stages continue to
download images on the same port, therefore there is no need to enable
cpsw_port1. Disable the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Vignesh Raghavendra 2022-01-21 12:47:52 +05:30 • committed by Tom Rini
parent 5022a2ef1b
commit afe5163449
2 changed files with 0 additions and 19 deletions
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11
arch/arm/dts/k3-am642-r5-sk.dts
View file

@ -231,23 +231,12 @@
&rgmii2_pins_default>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

8
arch/arm/dts/k3-am642-sk-u-boot.dtsi
View file

@ -117,10 +117,6 @@
u-boot,dm-spl;
};
&cpsw_port1 {
u-boot,dm-spl;
};
&main_bcdma {
u-boot,dm-spl;
};
@ -141,10 +137,6 @@
u-boot,dm-spl;
};
&cpsw3g_phy0 {
u-boot,dm-spl;
};
&cpsw3g_phy1 {
u-boot,dm-spl;
};