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arm: armada-xp: Add SPL support used to include the DDR training code
This patch adds SPL support to the Marvell Armada-XP. With this addition the bin_hdr integration is not needed any more. The SPL will first initialize the serdes/PHY and the call the DDR setup and training code now integrated into mainline U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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5 changed files with 172 additions and 0 deletions
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@ -5,3 +5,5 @@
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#
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obj-y = cpu.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
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62
arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
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62
arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
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@ -0,0 +1,62 @@
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/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <version.h>
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#include <linux/linkage.h>
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ENTRY(save_boot_params)
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bx lr
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ENDPROC(save_boot_params)
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/*
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* cache_inv - invalidate Cache line
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* r0 - dest
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*/
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.global cache_inv
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.type cache_inv, %function
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cache_inv:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c6, 1
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v6 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v6
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.type flush_l1_v6, %function
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flush_l1_v6:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v7 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v7
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.type flush_l1_v7, %function
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flush_l1_v7:
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stmfd sp!, {r1-r12}
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dmb /* @data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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dsb /* @data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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38
arch/arm/cpu/armv7/armada-xp/spl.c
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38
arch/arm/cpu/armv7/armada-xp/spl.c
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@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 spl_boot_device(void)
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{
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/* Right now only booting via SPI NOR flash is supported */
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return BOOT_DEVICE_SPI;
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}
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void board_init_f(ulong dummy)
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{
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/* Set global data pointer */
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gd = &gdata;
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/* Linux expects the internal registers to be at 0xf1000000 */
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arch_cpu_init();
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preloader_console_init();
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/* First init the serdes PHY's */
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serdes_phy_config();
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/* Setup DDR */
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ddr3_init();
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board_init_r(NULL, 0);
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}
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@ -106,5 +106,18 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank);
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unsigned int mvebu_sdram_bs(enum memory_bank bank);
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void mvebu_sdram_size_adjust(enum memory_bank bank);
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int mvebu_mbus_probe(struct mbus_win windows[], int count);
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/*
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* Highspeed SERDES PHY config init, ported from bin_hdr
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* to mainline U-Boot
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*/
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int serdes_phy_config(void);
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/*
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* DDR3 init / training code ported from Marvell bin_hdr. Now
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* available in mainline U-Boot in:
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* drivers/ddr/mvebu/
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*/
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int ddr3_init(void);
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#endif /* __ASSEMBLY__ */
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#endif /* _ARMADA_XP_CPU_H */
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57
arch/arm/mvebu-common/u-boot-spl.lds
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57
arch/arm/mvebu-common/u-boot-spl.lds
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/*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Aneesh V <aneesh@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
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LENGTH = CONFIG_SPL_MAX_SIZE }
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MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
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LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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.text :
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{
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__start = .;
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arch/arm/cpu/armv7/start.o (.text*)
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*(.text*)
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*(.vectors)
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} >.sram
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. = ALIGN(4);
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.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
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. = ALIGN(4);
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.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
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. = ALIGN(4);
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.u_boot_list : {
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KEEP(*(SORT(.u_boot_list*_i2c_*)));
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} >.sram
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. = ALIGN(4);
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__image_copy_end = .;
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.end :
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{
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*(.__end)
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}
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.bss :
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{
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. = ALIGN(4);
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__bss_start = .;
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*(.bss*)
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. = ALIGN(4);
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__bss_end = .;
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} >.sdram
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}
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