mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
commit
b18815752f
134 changed files with 4919 additions and 3222 deletions
13
MAINTAINERS
13
MAINTAINERS
|
@ -572,6 +572,10 @@ Rishi Bhattacharya <rishi@ti.com>
|
|||
|
||||
omap5912osk ARM926EJS
|
||||
|
||||
Andreas Bießmann <andreas.devel@gmail.com>
|
||||
|
||||
at91rm9200ek at91rm9200
|
||||
|
||||
Cliff Brake <cliff.brake@gmail.com>
|
||||
|
||||
pxa255_idp xscale
|
||||
|
@ -808,6 +812,15 @@ Greg Ungerer <greg.ungerer@opengear.com>
|
|||
cm4116 ks8695p
|
||||
cm4148 ks8695p
|
||||
|
||||
Marek Vasut <marek.vasut@gmail.com>
|
||||
|
||||
balloon3 xscale
|
||||
colibri_pxa270 xscale
|
||||
palmld xscale
|
||||
palmtc xscale
|
||||
vpac270 xscale
|
||||
zipitz2 xscale
|
||||
|
||||
Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
|
||||
|
||||
SFFSDR ARM926EJS
|
||||
|
|
7
MAKEALL
7
MAKEALL
|
@ -468,12 +468,7 @@ LIST_at91=" \
|
|||
## Xscale Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_pxa="$(boards_by_cpu pxa)
|
||||
polaris \
|
||||
trizepsiv \
|
||||
vpac270_nor \
|
||||
vpac270_onenand \
|
||||
"
|
||||
LIST_pxa="$(boards_by_cpu pxa)"
|
||||
|
||||
LIST_ixp="$(boards_by_cpu ixp)
|
||||
pdnb3 \
|
||||
|
|
19
Makefile
19
Makefile
|
@ -358,7 +358,7 @@ $(obj)u-boot.imx: $(obj)u-boot.bin
|
|||
|
||||
$(obj)u-boot.kwb: $(obj)u-boot.bin
|
||||
$(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \
|
||||
-a $(CONFIG_SYS_TEXT_BASE) -e $(TEXT_BASE) -d $< $@
|
||||
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
|
||||
|
||||
$(obj)u-boot.sha1: $(obj)u-boot.bin
|
||||
$(obj)tools/ubsha1 $(obj)u-boot.bin
|
||||
|
@ -1027,23 +1027,6 @@ scpu_config: unconfig
|
|||
fi
|
||||
@$(MKCONFIG) -n $@ -a pdnb3 arm ixp pdnb3 prodrive
|
||||
|
||||
polaris_config \
|
||||
trizepsiv_config : unconfig
|
||||
@mkdir -p $(obj)include
|
||||
@if [ "$(findstring polaris,$@)" ] ; then \
|
||||
echo "#define CONFIG_POLARIS 1" >>$(obj)include/config.h ; \
|
||||
fi;
|
||||
@$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv
|
||||
|
||||
vpac270_nor_config \
|
||||
vpac270_onenand_config : unconfig
|
||||
@mkdir -p $(obj)include
|
||||
@if [ "$(findstring onenand,$@)" ] ; then \
|
||||
echo "#define CONFIG_ONENAND_U_BOOT" \
|
||||
>>$(obj)include/config.h ; \
|
||||
fi;
|
||||
@$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270
|
||||
|
||||
#########################################################################
|
||||
## ARM1136 Systems
|
||||
#########################################################################
|
||||
|
|
13
README
13
README
|
@ -2275,6 +2275,19 @@ Configuration Settings:
|
|||
all data for the Linux kernel must be between "bootm_low"
|
||||
and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.
|
||||
|
||||
- CONFIG_SYS_BOOT_RAMDISK_HIGH:
|
||||
Enable initrd_high functionality. If defined then the
|
||||
initrd_high feature is enabled and the bootm ramdisk subcommand
|
||||
is enabled.
|
||||
|
||||
- CONFIG_SYS_BOOT_GET_CMDLINE:
|
||||
Enables allocating and saving kernel cmdline in space between
|
||||
"bootm_low" and "bootm_low" + BOOTMAPSZ.
|
||||
|
||||
- CONFIG_SYS_BOOT_GET_KBD:
|
||||
Enables allocating and saving a kernel copy of the bd_info in
|
||||
space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
|
||||
|
||||
- CONFIG_SYS_MAX_FLASH_BANKS:
|
||||
Max number of Flash memory banks
|
||||
|
||||
|
|
|
@ -33,11 +33,6 @@ STANDALONE_LOAD_ADDR = 0xc100000
|
|||
endif
|
||||
endif
|
||||
|
||||
ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
|
||||
# needed for relocation
|
||||
PLATFORM_RELFLAGS += -fPIC
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_SYS_ARM_WITHOUT_RELOC
|
||||
endif
|
||||
|
@ -72,3 +67,10 @@ PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
|
|||
endif
|
||||
endif
|
||||
LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
|
||||
|
||||
ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
|
||||
# needed for relocation
|
||||
ifndef CONFIG_NAND_SPL
|
||||
PLATFORM_LDFLAGS += -pie
|
||||
endif
|
||||
endif
|
||||
|
|
|
@ -89,48 +89,35 @@ _end_vect:
|
|||
_TEXT_BASE:
|
||||
.word CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
.globl _armboot_start
|
||||
_armboot_start:
|
||||
.word _start
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These are defined in the board-specific linker script.
|
||||
* Subtracting _start from them lets the linker put their
|
||||
* relative position in the executable instead of leaving
|
||||
* them null.
|
||||
*/
|
||||
.globl _bss_start
|
||||
_bss_start:
|
||||
.word __bss_start
|
||||
.globl _bss_start_ofs
|
||||
_bss_start_ofs:
|
||||
.word __bss_start - _start
|
||||
|
||||
.globl _bss_end
|
||||
_bss_end:
|
||||
.word _end
|
||||
.globl _bss_end_ofs
|
||||
_bss_end_ofs:
|
||||
.word _end - _start
|
||||
|
||||
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
.globl _datarel_start
|
||||
_datarel_start:
|
||||
.word __datarel_start
|
||||
.globl _datarel_start_ofs
|
||||
_datarel_start_ofs:
|
||||
.word __datarel_start - _start
|
||||
|
||||
.globl _datarelrolocal_start
|
||||
_datarelrolocal_start:
|
||||
.word __datarelrolocal_start
|
||||
.globl _datarelrolocal_start_ofs
|
||||
_datarelrolocal_start_ofs:
|
||||
.word __datarelrolocal_start - _start
|
||||
|
||||
.globl _datarellocal_start
|
||||
_datarellocal_start:
|
||||
.word __datarellocal_start
|
||||
.globl _datarellocal_start_ofs
|
||||
_datarellocal_start_ofs:
|
||||
.word __datarellocal_start - _start
|
||||
|
||||
.globl _datarelro_start
|
||||
_datarelro_start:
|
||||
.word __datarelro_start
|
||||
|
||||
.globl _got_start
|
||||
_got_start:
|
||||
.word __got_start
|
||||
|
||||
.globl _got_end
|
||||
_got_end:
|
||||
.word __got_end
|
||||
#endif
|
||||
.globl _datarelro_start_ofs
|
||||
_datarelro_start_ofs:
|
||||
.word __datarelro_start - _start
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* IRQ stack memory (calculated at run-time) */
|
||||
|
@ -225,9 +212,8 @@ stack_setup:
|
|||
|
||||
adr r0, _start
|
||||
ldr r2, _TEXT_BASE
|
||||
ldr r3, _bss_start
|
||||
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||
add r2, r0, r2 /* r2 <- source end address */
|
||||
ldr r3, _bss_start_ofs
|
||||
add r2, r0, r3 /* r2 <- source end address */
|
||||
cmp r0, r6
|
||||
beq clear_bss
|
||||
|
||||
|
@ -239,36 +225,54 @@ copy_loop:
|
|||
blo copy_loop
|
||||
|
||||
#ifndef CONFIG_PRELOADER
|
||||
/* fix got entries */
|
||||
ldr r1, _TEXT_BASE
|
||||
mov r0, r7 /* reloc addr */
|
||||
ldr r2, _got_start /* addr in Flash */
|
||||
ldr r3, _got_end /* addr in Flash */
|
||||
sub r3, r3, r1
|
||||
add r3, r3, r0
|
||||
sub r2, r2, r1
|
||||
add r2, r2, r0
|
||||
|
||||
/*
|
||||
* fix .rel.dyn relocations
|
||||
*/
|
||||
ldr r0, _TEXT_BASE /* r0 <- Text base */
|
||||
sub r9, r7, r0 /* r9 <- relocation offset */
|
||||
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
|
||||
add r10, r10, r0 /* r10 <- sym table in FLASH */
|
||||
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
|
||||
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
|
||||
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
|
||||
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
|
||||
fixloop:
|
||||
ldr r4, [r2]
|
||||
sub r4, r4, r1
|
||||
add r4, r4, r0
|
||||
str r4, [r2]
|
||||
add r2, r2, #4
|
||||
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
|
||||
add r0, r9 /* r0 <- location to fix up in RAM */
|
||||
ldr r1, [r2, #4]
|
||||
and r8, r1, #0xff
|
||||
cmp r8, #23 /* relative fixup? */
|
||||
beq fixrel
|
||||
cmp r8, #2 /* absolute fixup? */
|
||||
beq fixabs
|
||||
/* ignore unknown type of fixup */
|
||||
b fixnext
|
||||
fixabs:
|
||||
/* absolute fix: set location to (offset) symbol value */
|
||||
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
|
||||
add r1, r10, r1 /* r1 <- address of symbol in table */
|
||||
ldr r1, [r1, #4] /* r1 <- symbol value */
|
||||
add r1, r9 /* r1 <- relocated sym addr */
|
||||
b fixnext
|
||||
fixrel:
|
||||
/* relative fix: increase location by offset */
|
||||
ldr r1, [r0]
|
||||
add r1, r1, r9
|
||||
fixnext:
|
||||
str r1, [r0]
|
||||
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
|
||||
cmp r2, r3
|
||||
bne fixloop
|
||||
ble fixloop
|
||||
#endif
|
||||
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||
|
||||
clear_bss:
|
||||
#ifndef CONFIG_PRELOADER
|
||||
ldr r0, _bss_start
|
||||
ldr r1, _bss_end
|
||||
ldr r0, _bss_start_ofs
|
||||
ldr r1, _bss_end_ofs
|
||||
ldr r3, _TEXT_BASE /* Text base */
|
||||
mov r4, r7 /* reloc addr */
|
||||
sub r0, r0, r3
|
||||
add r0, r0, r4
|
||||
sub r1, r1, r3
|
||||
add r1, r1, r4
|
||||
mov r2, #0x00000000 /* clear */
|
||||
|
||||
|
@ -283,24 +287,34 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||
* initialization, now running from RAM.
|
||||
*/
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
ldr pc, _nand_boot
|
||||
|
||||
_nand_boot: .word nand_boot
|
||||
ldr r0, _nand_boot_ofs
|
||||
adr r1, _start
|
||||
add pc, r0, r1
|
||||
_nand_boot_ofs
|
||||
: .word nand_boot - _start
|
||||
#else
|
||||
jump_2_ram:
|
||||
ldr r0, _TEXT_BASE
|
||||
ldr r2, _board_init_r
|
||||
sub r2, r2, r0
|
||||
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||
ldr r0, _board_init_r_ofs
|
||||
adr r1, _start
|
||||
add r0, r0, r1
|
||||
add lr, r0, r9
|
||||
/* setup parameters for board_init_r */
|
||||
mov r0, r5 /* gd_t */
|
||||
mov r1, r7 /* dest_addr */
|
||||
/* jump to it ... */
|
||||
mov lr, r2
|
||||
mov pc, lr
|
||||
|
||||
_board_init_r: .word board_init_r
|
||||
_board_init_r_ofs:
|
||||
.word board_init_r - _start
|
||||
#endif
|
||||
|
||||
_rel_dyn_start_ofs:
|
||||
.word __rel_dyn_start - _start
|
||||
_rel_dyn_end_ofs:
|
||||
.word __rel_dyn_end - _start
|
||||
_dynsym_start_ofs:
|
||||
.word __dynsym_start - _start
|
||||
|
||||
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||
/*
|
||||
* the actual reset code
|
||||
|
@ -375,8 +389,11 @@ stack_setup:
|
|||
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
|
||||
|
||||
clear_bss:
|
||||
ldr r0, _bss_start /* find start of bss segment */
|
||||
ldr r1, _bss_end /* stop here */
|
||||
adr r2, _start
|
||||
ldr r0, _bss_start_ofs /* find start of bss segment */
|
||||
add r0, r0, r2
|
||||
ldr r1, _bss_end_ofs /* stop here */
|
||||
add r1, r1, r2
|
||||
mov r2, #0x00000000 /* clear */
|
||||
|
||||
#ifndef CONFIG_PRELOADER
|
||||
|
@ -386,15 +403,19 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||
bne clbss_l
|
||||
#endif
|
||||
|
||||
ldr pc, _start_armboot
|
||||
ldr r0, _start_armboot_ofs
|
||||
adr r1, _start
|
||||
add r0, r0, r1
|
||||
ldr pc, r0
|
||||
|
||||
_start_armboot_ofs:
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
_start_armboot: .word nand_boot
|
||||
.word nand_boot - _start
|
||||
#else
|
||||
#ifdef CONFIG_ONENAND_IPL
|
||||
_start_armboot: .word start_oneboot
|
||||
.word start_oneboot - _start
|
||||
#else
|
||||
_start_armboot: .word start_armboot
|
||||
.word start_armboot - _start
|
||||
#endif /* CONFIG_ONENAND_IPL */
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
|
@ -487,7 +508,7 @@ cpu_init_crit:
|
|||
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
|
||||
#else
|
||||
ldr r2, _armboot_start
|
||||
adr r2, _start
|
||||
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||
#endif
|
||||
|
@ -524,8 +545,8 @@ cpu_init_crit:
|
|||
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
|
||||
#else
|
||||
ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
|
||||
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
||||
adr r13, _start @ setup our mode stack (enter in banked mode)
|
||||
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
|
||||
#endif
|
||||
|
||||
|
|
|
@ -59,11 +59,14 @@ SECTIONS
|
|||
*(.data.rel.ro)
|
||||
}
|
||||
|
||||
__got_start = .;
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
__rel_dyn_start = .;
|
||||
.rel.dyn : { *(.rel.dyn) }
|
||||
__rel_dyn_end = .;
|
||||
|
||||
__dynsym_start = .;
|
||||
.dynsym : { *(.dynsym) }
|
||||
|
||||
__got_end = .;
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
|
@ -73,4 +76,10 @@ SECTIONS
|
|||
__bss_start = .;
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
_end = .;
|
||||
|
||||
/DISCARD/ : { *(.dynstr*) }
|
||||
/DISCARD/ : { *(.dynamic*) }
|
||||
/DISCARD/ : { *(.plt*) }
|
||||
/DISCARD/ : { *(.interp*) }
|
||||
/DISCARD/ : { *(.gnu*) }
|
||||
}
|
||||
|
|
|
@ -11,47 +11,46 @@
|
|||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/io.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/clk.h>
|
||||
|
||||
static unsigned long cpu_clk_rate_hz;
|
||||
static unsigned long main_clk_rate_hz;
|
||||
static unsigned long mck_rate_hz;
|
||||
static unsigned long plla_rate_hz;
|
||||
static unsigned long pllb_rate_hz;
|
||||
static u32 at91_pllb_usb_init;
|
||||
#if !defined(CONFIG_AT91FAMILY)
|
||||
# error You need to define CONFIG_AT91FAMILY in your board config!
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
unsigned long get_cpu_clk_rate(void)
|
||||
{
|
||||
return cpu_clk_rate_hz;
|
||||
return gd->cpu_clk_rate_hz;
|
||||
}
|
||||
|
||||
unsigned long get_main_clk_rate(void)
|
||||
{
|
||||
return main_clk_rate_hz;
|
||||
return gd->main_clk_rate_hz;
|
||||
}
|
||||
|
||||
unsigned long get_mck_clk_rate(void)
|
||||
{
|
||||
return mck_rate_hz;
|
||||
return gd->mck_rate_hz;
|
||||
}
|
||||
|
||||
unsigned long get_plla_clk_rate(void)
|
||||
{
|
||||
return plla_rate_hz;
|
||||
return gd->plla_rate_hz;
|
||||
}
|
||||
|
||||
unsigned long get_pllb_clk_rate(void)
|
||||
{
|
||||
return pllb_rate_hz;
|
||||
return gd->pllb_rate_hz;
|
||||
}
|
||||
|
||||
u32 get_pllb_init(void)
|
||||
{
|
||||
return at91_pllb_usb_init;
|
||||
return gd->at91_pllb_usb_init;
|
||||
}
|
||||
|
||||
static unsigned long at91_css_to_rate(unsigned long css)
|
||||
|
@ -60,11 +59,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
|
|||
case AT91_PMC_MCKR_CSS_SLOW:
|
||||
return AT91_SLOW_CLOCK;
|
||||
case AT91_PMC_MCKR_CSS_MAIN:
|
||||
return main_clk_rate_hz;
|
||||
return gd->main_clk_rate_hz;
|
||||
case AT91_PMC_MCKR_CSS_PLLA:
|
||||
return plla_rate_hz;
|
||||
return gd->plla_rate_hz;
|
||||
case AT91_PMC_MCKR_CSS_PLLB:
|
||||
return pllb_rate_hz;
|
||||
return gd->pllb_rate_hz;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -163,10 +162,10 @@ int at91_clock_init(unsigned long main_clock)
|
|||
main_clock = tmp * (AT91_SLOW_CLOCK / 16);
|
||||
}
|
||||
#endif
|
||||
main_clk_rate_hz = main_clock;
|
||||
gd->main_clk_rate_hz = main_clock;
|
||||
|
||||
/* report if PLLA is more than mildly overclocked */
|
||||
plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
|
||||
gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
|
||||
|
||||
#ifdef CONFIG_USB_ATMEL
|
||||
/*
|
||||
|
@ -175,9 +174,9 @@ int at91_clock_init(unsigned long main_clock)
|
|||
*
|
||||
* REVISIT: assumes MCK doesn't derive from PLLB!
|
||||
*/
|
||||
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
|
||||
gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
|
||||
AT91_PMC_PLLBR_USBDIV_2;
|
||||
pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
|
||||
gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
@ -187,30 +186,30 @@ int at91_clock_init(unsigned long main_clock)
|
|||
mckr = readl(&pmc->mckr);
|
||||
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
|
||||
/* plla divisor by 2 */
|
||||
plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
|
||||
gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
|
||||
#endif
|
||||
mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
|
||||
freq = mck_rate_hz;
|
||||
gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
|
||||
freq = gd->mck_rate_hz;
|
||||
|
||||
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
|
||||
#if defined(CONFIG_AT91RM9200)
|
||||
/* mdiv */
|
||||
mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
|
||||
gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
|
||||
#elif defined(CONFIG_AT91SAM9G20)
|
||||
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
|
||||
mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
|
||||
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
|
||||
freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
|
||||
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
|
||||
freq /= 2; /* processor clock division */
|
||||
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
|
||||
mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
|
||||
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
|
||||
(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
|
||||
? freq / 3
|
||||
: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
|
||||
#else
|
||||
mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
|
||||
gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
|
||||
#endif
|
||||
cpu_clk_rate_hz = freq;
|
||||
gd->cpu_clk_rate_hz = freq;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -30,55 +30,63 @@
|
|||
#include <asm/arch/io.h>
|
||||
#include <div64.h>
|
||||
|
||||
#if !defined(CONFIG_AT91FAMILY)
|
||||
# error You need to define CONFIG_AT91FAMILY in your board config!
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
|
||||
* setting the 20 bit counter period to its maximum (0xfffff).
|
||||
* (See the relevant data sheets to understand that this really works)
|
||||
*
|
||||
* We do also mimic the typical powerpc way of incrementing
|
||||
* two 32 bit registers called tbl and tbu.
|
||||
*
|
||||
* Those registers increment at 1/16 the main clock rate.
|
||||
*/
|
||||
#define TIMER_LOAD_VAL 0xfffff
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong lastinc;
|
||||
static ulong timer_freq;
|
||||
#define TIMER_LOAD_VAL 0xfffff
|
||||
|
||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||
{
|
||||
tick *= CONFIG_SYS_HZ;
|
||||
do_div(tick, timer_freq);
|
||||
do_div(tick, gd->timer_rate_hz);
|
||||
|
||||
return tick;
|
||||
}
|
||||
|
||||
static inline unsigned long long usec_to_tick(unsigned long long usec)
|
||||
{
|
||||
usec *= timer_freq;
|
||||
usec *= gd->timer_rate_hz;
|
||||
do_div(usec, 1000000);
|
||||
|
||||
return usec;
|
||||
}
|
||||
|
||||
/* nothing really to do with interrupts, just starts up a counter. */
|
||||
/*
|
||||
* Use the PITC in full 32 bit incrementing mode
|
||||
*/
|
||||
int timer_init(void)
|
||||
{
|
||||
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
|
||||
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
|
||||
/*
|
||||
* Enable PITC Clock
|
||||
* The clock is already enabled for system controller in boot
|
||||
*/
|
||||
|
||||
/* Enable PITC Clock */
|
||||
writel(1 << AT91_ID_SYS, &pmc->pcer);
|
||||
|
||||
/* Enable PITC */
|
||||
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
|
||||
|
||||
reset_timer_masked();
|
||||
|
||||
timer_freq = get_mck_clk_rate() >> 4;
|
||||
gd->timer_rate_hz = gd->mck_rate_hz / 16;
|
||||
gd->tbu = gd->tbl = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* timer without interrupts
|
||||
* Get the current 64 bit timer tick count
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
|
@ -86,28 +94,11 @@ unsigned long long get_ticks(void)
|
|||
|
||||
ulong now = readl(&pit->piir);
|
||||
|
||||
if (now >= lastinc) /* normal mode (non roll) */
|
||||
/* move stamp forward with absolut diff ticks */
|
||||
timestamp += (now - lastinc);
|
||||
else /* we have rollover of incrementer */
|
||||
timestamp += (0xFFFFFFFF - lastinc) + now;
|
||||
lastinc = now;
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
void reset_timer_masked(void)
|
||||
{
|
||||
/* reset time */
|
||||
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
|
||||
|
||||
/* capture current incrementer value time */
|
||||
lastinc = readl(&pit->piir);
|
||||
timestamp = 0; /* start "advancing" time stamp from 0 */
|
||||
}
|
||||
|
||||
ulong get_timer_masked(void)
|
||||
{
|
||||
return tick_to_time(get_ticks());
|
||||
/* increment tbu if tbl has rolled over */
|
||||
if (now < gd->tbl)
|
||||
gd->tbu++;
|
||||
gd->tbl = now;
|
||||
return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
|
||||
}
|
||||
|
||||
void __udelay(unsigned long usec)
|
||||
|
@ -119,24 +110,32 @@ void __udelay(unsigned long usec)
|
|||
tmp = get_ticks() + tmo; /* get current timestamp */
|
||||
|
||||
while (get_ticks() < tmp) /* loop till event */
|
||||
/*NOP*/;
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* reset_timer() and get_timer(base) are a pair of functions that are used by
|
||||
* some timeout/sleep mechanisms in u-boot.
|
||||
*
|
||||
* reset_timer() marks the current time as epoch and
|
||||
* get_timer(base) works relative to that epoch.
|
||||
*
|
||||
* The time is used in CONFIG_SYS_HZ units!
|
||||
*/
|
||||
void reset_timer(void)
|
||||
{
|
||||
reset_timer_masked();
|
||||
gd->timer_reset_value = get_ticks();
|
||||
}
|
||||
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked () - base;
|
||||
return tick_to_time(get_ticks() - gd->timer_reset_value) - base;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
* Return the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk(void)
|
||||
{
|
||||
return timer_freq;
|
||||
return gd->timer_rate_hz;
|
||||
}
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
|
||||
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
|
||||
* Copyright (c) 2010 Albert Aribaud <albert.aribaud@free.fr>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -118,22 +119,19 @@ _fiq:
|
|||
_TEXT_BASE:
|
||||
.word CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
.globl _armboot_start
|
||||
_armboot_start:
|
||||
.word _start
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These are defined in the board-specific linker script.
|
||||
* Subtracting _start from them lets the linker put their
|
||||
* relative position in the executable instead of leaving
|
||||
* them null.
|
||||
*/
|
||||
.globl _bss_start
|
||||
_bss_start:
|
||||
.word __bss_start
|
||||
.globl _bss_start_ofs
|
||||
_bss_start_ofs:
|
||||
.word __bss_start - _start
|
||||
|
||||
.globl _bss_end
|
||||
_bss_end:
|
||||
.word _end
|
||||
.globl _bss_end_ofs
|
||||
_bss_end_ofs:
|
||||
.word _end - _start
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* IRQ stack memory (calculated at run-time) */
|
||||
|
@ -153,30 +151,6 @@ FIQ_STACK_START:
|
|||
IRQ_STACK_START_IN:
|
||||
.word 0x0badc0de
|
||||
|
||||
.globl _datarel_start
|
||||
_datarel_start:
|
||||
.word __datarel_start
|
||||
|
||||
.globl _datarelrolocal_start
|
||||
_datarelrolocal_start:
|
||||
.word __datarelrolocal_start
|
||||
|
||||
.globl _datarellocal_start
|
||||
_datarellocal_start:
|
||||
.word __datarellocal_start
|
||||
|
||||
.globl _datarelro_start
|
||||
_datarelro_start:
|
||||
.word __datarelro_start
|
||||
|
||||
.globl _got_start
|
||||
_got_start:
|
||||
.word __got_start
|
||||
|
||||
.globl _got_end
|
||||
_got_end:
|
||||
.word __got_end
|
||||
|
||||
/*
|
||||
* the actual reset code
|
||||
*/
|
||||
|
@ -226,9 +200,8 @@ stack_setup:
|
|||
|
||||
adr r0, _start
|
||||
ldr r2, _TEXT_BASE
|
||||
ldr r3, _bss_start
|
||||
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||
add r2, r0, r2 /* r2 <- source end address */
|
||||
ldr r3, _bss_start_ofs
|
||||
add r2, r0, r3 /* r2 <- source end address */
|
||||
cmp r0, r6
|
||||
beq clear_bss
|
||||
|
||||
|
@ -240,36 +213,54 @@ copy_loop:
|
|||
blo copy_loop
|
||||
|
||||
#ifndef CONFIG_PRELOADER
|
||||
/* fix got entries */
|
||||
ldr r1, _TEXT_BASE /* Text base */
|
||||
mov r0, r7 /* reloc addr */
|
||||
ldr r2, _got_start /* addr in Flash */
|
||||
ldr r3, _got_end /* addr in Flash */
|
||||
sub r3, r3, r1
|
||||
add r3, r3, r0
|
||||
sub r2, r2, r1
|
||||
add r2, r2, r0
|
||||
|
||||
/*
|
||||
* fix .rel.dyn relocations
|
||||
*/
|
||||
ldr r0, _TEXT_BASE /* r0 <- Text base */
|
||||
sub r9, r7, r0 /* r9 <- relocation offset */
|
||||
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
|
||||
add r10, r10, r0 /* r10 <- sym table in FLASH */
|
||||
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
|
||||
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
|
||||
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
|
||||
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
|
||||
fixloop:
|
||||
ldr r4, [r2]
|
||||
sub r4, r4, r1
|
||||
add r4, r4, r0
|
||||
str r4, [r2]
|
||||
add r2, r2, #4
|
||||
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
|
||||
add r0, r9 /* r0 <- location to fix up in RAM */
|
||||
ldr r1, [r2, #4]
|
||||
and r8, r1, #0xff
|
||||
cmp r8, #23 /* relative fixup? */
|
||||
beq fixrel
|
||||
cmp r8, #2 /* absolute fixup? */
|
||||
beq fixabs
|
||||
/* ignore unknown type of fixup */
|
||||
b fixnext
|
||||
fixabs:
|
||||
/* absolute fix: set location to (offset) symbol value */
|
||||
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
|
||||
add r1, r10, r1 /* r1 <- address of symbol in table */
|
||||
ldr r1, [r1, #4] /* r1 <- symbol value */
|
||||
add r1, r9 /* r1 <- relocated sym addr */
|
||||
b fixnext
|
||||
fixrel:
|
||||
/* relative fix: increase location by offset */
|
||||
ldr r1, [r0]
|
||||
add r1, r1, r9
|
||||
fixnext:
|
||||
str r1, [r0]
|
||||
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
|
||||
cmp r2, r3
|
||||
bne fixloop
|
||||
blo fixloop
|
||||
#endif
|
||||
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||
|
||||
clear_bss:
|
||||
#ifndef CONFIG_PRELOADER
|
||||
ldr r0, _bss_start
|
||||
ldr r1, _bss_end
|
||||
ldr r0, _bss_start_ofs
|
||||
ldr r1, _bss_end_ofs
|
||||
ldr r3, _TEXT_BASE /* Text base */
|
||||
mov r4, r7 /* reloc addr */
|
||||
sub r0, r0, r3
|
||||
add r0, r0, r4
|
||||
sub r1, r1, r3
|
||||
add r1, r1, r4
|
||||
mov r2, #0x00000000 /* clear */
|
||||
|
||||
|
@ -287,24 +278,33 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||
* initialization, now running from RAM.
|
||||
*/
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
ldr pc, _nand_boot
|
||||
ldr r0, _nand_boot_ofs
|
||||
mov pc, r0
|
||||
|
||||
_nand_boot: .word nand_boot
|
||||
_nand_boot_ofs:
|
||||
.word nand_boot
|
||||
#else
|
||||
ldr r0, _TEXT_BASE
|
||||
ldr r2, _board_init_r
|
||||
sub r2, r2, r0
|
||||
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||
ldr r0, _board_init_r_ofs
|
||||
adr r1, _start
|
||||
add r0, r0, r1
|
||||
add lr, r0, r9
|
||||
/* setup parameters for board_init_r */
|
||||
mov r0, r5 /* gd_t */
|
||||
mov r1, r7 /* dest_addr */
|
||||
/* jump to it ... */
|
||||
mov lr, r2
|
||||
mov pc, lr
|
||||
|
||||
_board_init_r: .word board_init_r
|
||||
_board_init_r_ofs:
|
||||
.word board_init_r - _start
|
||||
#endif
|
||||
|
||||
_rel_dyn_start_ofs:
|
||||
.word __rel_dyn_start - _start
|
||||
_rel_dyn_end_ofs:
|
||||
.word __rel_dyn_end - _start
|
||||
_dynsym_start_ofs:
|
||||
.word __dynsym_start - _start
|
||||
|
||||
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||
/*
|
||||
* the actual reset code
|
||||
|
@ -333,10 +333,8 @@ relocate: /* relocate U-Boot to RAM */
|
|||
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
|
||||
cmp r0, r1 /* don't reloc during debug */
|
||||
beq stack_setup
|
||||
ldr r2, _armboot_start
|
||||
ldr r3, _bss_start
|
||||
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||
add r2, r0, r2 /* r2 <- source end address */
|
||||
ldr r3, _bss_start_ofs /* r3 <- _bss_start - _start */
|
||||
add r2, r0, r3 /* r2 <- source end address */
|
||||
|
||||
copy_loop:
|
||||
ldmia r0!, {r3-r10} /* copy from source address [r0] */
|
||||
|
@ -360,8 +358,11 @@ stack_setup:
|
|||
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
|
||||
|
||||
clear_bss:
|
||||
ldr r0, _bss_start /* find start of bss segment */
|
||||
ldr r1, _bss_end /* stop here */
|
||||
adr r2, _start
|
||||
ldr r0, _bss_start_ofs /* find start of bss segment */
|
||||
add r0, r0, r2
|
||||
ldr r1, _bss_end_ofs /* stop here */
|
||||
add r1, r1, r2
|
||||
mov r2, #0x00000000 /* clear */
|
||||
|
||||
#ifndef CONFIG_PRELOADER
|
||||
|
@ -374,13 +375,16 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||
bl red_LED_on
|
||||
#endif /* CONFIG_PRELOADER */
|
||||
|
||||
ldr pc, _start_armboot
|
||||
ldr r0, _start_armboot_ofs
|
||||
adr r1, _start
|
||||
add r0, r0, r1
|
||||
ldr pc, r0
|
||||
|
||||
_start_armboot:
|
||||
_start_armboot_ofs:
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
.word nand_boot
|
||||
.word nand_boot - _start
|
||||
#else
|
||||
.word start_armboot
|
||||
.word start_armboot - _start
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||
|
||||
|
@ -469,7 +473,7 @@ cpu_init_crit:
|
|||
sub sp, sp, #S_FRAME_SIZE
|
||||
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
||||
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
ldr r2, _armboot_start
|
||||
adr r2, _start
|
||||
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||
#else
|
||||
|
@ -507,7 +511,7 @@ cpu_init_crit:
|
|||
|
||||
.macro get_bad_stack
|
||||
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
ldr r13, _armboot_start @ setup our mode stack
|
||||
adr r13, _start @ setup our mode stack
|
||||
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||
#else
|
||||
|
|
|
@ -41,21 +41,19 @@ SECTIONS
|
|||
. = ALIGN(4);
|
||||
.data : {
|
||||
*(.data)
|
||||
__datarel_start = .;
|
||||
*(.data.rel)
|
||||
__datarelrolocal_start = .;
|
||||
*(.data.rel.ro.local)
|
||||
__datarellocal_start = .;
|
||||
*(.data.rel.local)
|
||||
__datarelro_start = .;
|
||||
*(.data.rel.ro)
|
||||
}
|
||||
|
||||
__got_start = .;
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__got_end = .;
|
||||
__rel_dyn_start = .;
|
||||
.rel.dyn : { *(.rel.dyn) }
|
||||
__rel_dyn_end = .;
|
||||
|
||||
__dynsym_start = .;
|
||||
.dynsym : { *(.dynsym) }
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
|
@ -65,4 +63,10 @@ SECTIONS
|
|||
__bss_start = .;
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
_end = .;
|
||||
|
||||
/DISCARD/ : { *(.dynstr*) }
|
||||
/DISCARD/ : { *(.dynamic*) }
|
||||
/DISCARD/ : { *(.plt*) }
|
||||
/DISCARD/ : { *(.interp*) }
|
||||
/DISCARD/ : { *(.gnu*) }
|
||||
}
|
||||
|
|
|
@ -71,7 +71,7 @@ u32 get_mcu_main_clk(void)
|
|||
|
||||
reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
|
||||
MXC_CCM_CACRR_ARM_PODF_OFFSET;
|
||||
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
|
||||
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
|
||||
return freq / (reg + 1);
|
||||
}
|
||||
|
||||
|
@ -84,14 +84,14 @@ static u32 get_periph_clk(void)
|
|||
|
||||
reg = __raw_readl(&mxc_ccm->cbcdr);
|
||||
if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
|
||||
return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
|
||||
return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
|
||||
reg = __raw_readl(&mxc_ccm->cbcmr);
|
||||
switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
|
||||
MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
|
||||
case 0:
|
||||
return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
|
||||
return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
|
||||
case 1:
|
||||
return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
|
||||
return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
@ -146,15 +146,15 @@ static u32 get_uart_clk(void)
|
|||
MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
|
||||
case 0x0:
|
||||
freq = decode_pll(mxc_plls[PLL1_CLOCK],
|
||||
CONFIG_MX51_HCLK_FREQ);
|
||||
CONFIG_SYS_MX5_HCLK);
|
||||
break;
|
||||
case 0x1:
|
||||
freq = decode_pll(mxc_plls[PLL2_CLOCK],
|
||||
CONFIG_MX51_HCLK_FREQ);
|
||||
CONFIG_SYS_MX5_HCLK);
|
||||
break;
|
||||
case 0x2:
|
||||
freq = decode_pll(mxc_plls[PLL3_CLOCK],
|
||||
CONFIG_MX51_HCLK_FREQ);
|
||||
CONFIG_SYS_MX5_HCLK);
|
||||
break;
|
||||
default:
|
||||
return 66500000;
|
||||
|
@ -181,7 +181,7 @@ u32 get_lp_apm(void)
|
|||
u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
|
||||
|
||||
if (((ccsr >> 9) & 1) == 0)
|
||||
ret_val = CONFIG_MX51_HCLK_FREQ;
|
||||
ret_val = CONFIG_SYS_MX5_HCLK;
|
||||
else
|
||||
ret_val = ((32768 * 1024));
|
||||
|
||||
|
@ -207,17 +207,17 @@ u32 imx_get_cspiclk(void)
|
|||
switch (clk_sel) {
|
||||
case 0:
|
||||
ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
|
||||
CONFIG_MX51_HCLK_FREQ) /
|
||||
CONFIG_SYS_MX5_HCLK) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
break;
|
||||
case 1:
|
||||
ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
|
||||
CONFIG_MX51_HCLK_FREQ) /
|
||||
CONFIG_SYS_MX5_HCLK) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
break;
|
||||
case 2:
|
||||
ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
|
||||
CONFIG_MX51_HCLK_FREQ) /
|
||||
CONFIG_SYS_MX5_HCLK) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
break;
|
||||
default:
|
||||
|
@ -248,7 +248,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
|
|||
return imx_get_cspiclk();
|
||||
case MXC_FEC_CLK:
|
||||
return decode_pll(mxc_plls[PLL1_CLOCK],
|
||||
CONFIG_MX51_HCLK_FREQ);
|
||||
CONFIG_SYS_MX5_HCLK);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
@ -269,16 +269,16 @@ u32 imx_get_fecclk(void)
|
|||
/*
|
||||
* Dump some core clockes.
|
||||
*/
|
||||
int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
u32 freq;
|
||||
|
||||
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
|
||||
printf("mx51 pll1: %dMHz\n", freq / 1000000);
|
||||
freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
|
||||
printf("mx51 pll2: %dMHz\n", freq / 1000000);
|
||||
freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
|
||||
printf("mx51 pll3: %dMHz\n", freq / 1000000);
|
||||
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
|
||||
printf("pll1: %dMHz\n", freq / 1000000);
|
||||
freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
|
||||
printf("pll2: %dMHz\n", freq / 1000000);
|
||||
freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
|
||||
printf("pll3: %dMHz\n", freq / 1000000);
|
||||
printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
|
||||
printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
|
||||
|
||||
|
@ -288,7 +288,7 @@ int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
|
|||
/***************************************************/
|
||||
|
||||
U_BOOT_CMD(
|
||||
clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks,
|
||||
"display mx51 clocks\n",
|
||||
clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
|
||||
"display clocks\n",
|
||||
""
|
||||
);
|
|
@ -23,7 +23,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx51_pins.h>
|
||||
#include <asm/arch/mx5x_pins.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
|
@ -257,20 +257,6 @@ lowlevel_init:
|
|||
orr r1, r1, #(1 << 23)
|
||||
str r1, [r0, #0x4]
|
||||
|
||||
#ifdef ENABLE_IMPRECISE_ABORT
|
||||
mrs r1, spsr /* save old spsr */
|
||||
mrs r0, cpsr /* read out the cpsr */
|
||||
bic r0, r0, #0x100 /* clear the A bit */
|
||||
msr spsr, r0 /* update spsr */
|
||||
add lr, pc, #0x8 /* update lr */
|
||||
movs pc, lr /* update cpsr */
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
msr spsr, r1 /* restore old spsr */
|
||||
#endif
|
||||
|
||||
init_l2cc
|
||||
|
||||
init_aips
|
|
@ -33,28 +33,33 @@
|
|||
#include <fsl_esdhc.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX51)
|
||||
#define CPU_TYPE 0x51000
|
||||
#else
|
||||
#error "CPU_TYPE not defined"
|
||||
#endif
|
||||
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
int reg;
|
||||
int system_rev;
|
||||
int system_rev = CPU_TYPE;
|
||||
int reg = __raw_readl(ROM_SI_REV);
|
||||
|
||||
reg = __raw_readl(ROM_SI_REV);
|
||||
switch (reg) {
|
||||
case 0x02:
|
||||
system_rev = 0x51000 | CHIP_REV_1_1;
|
||||
system_rev |= CHIP_REV_1_1;
|
||||
break;
|
||||
case 0x10:
|
||||
if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
|
||||
system_rev = 0x51000 | CHIP_REV_2_5;
|
||||
system_rev |= CHIP_REV_2_5;
|
||||
else
|
||||
system_rev = 0x51000 | CHIP_REV_2_0;
|
||||
system_rev |= CHIP_REV_2_0;
|
||||
break;
|
||||
case 0x20:
|
||||
system_rev = 0x51000 | CHIP_REV_3_0;
|
||||
system_rev |= CHIP_REV_3_0;
|
||||
break;
|
||||
return system_rev;
|
||||
default:
|
||||
system_rev = 0x51000 | CHIP_REV_1_0;
|
||||
system_rev |= CHIP_REV_1_0;
|
||||
break;
|
||||
}
|
||||
return system_rev;
|
||||
|
@ -67,9 +72,10 @@ int print_cpuinfo(void)
|
|||
u32 cpurev;
|
||||
|
||||
cpurev = get_cpu_rev();
|
||||
printf("CPU: Freescale i.MX51 family rev%d.%d at %d MHz\n",
|
||||
(cpurev & 0xF0) >> 4,
|
||||
(cpurev & 0x0F) >> 4,
|
||||
printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
|
||||
(cpurev & 0xFF000) >> 12,
|
||||
(cpurev & 0x000F0) >> 4,
|
||||
(cpurev & 0x0000F) >> 0,
|
||||
mxc_get_clock(MXC_ARM_CLK) / 1000000);
|
||||
return 0;
|
||||
}
|
|
@ -75,18 +75,18 @@ void reset_timer(void)
|
|||
void reset_timer_masked(void)
|
||||
{
|
||||
ulong val = __raw_readl(&cur_gpt->counter);
|
||||
lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
|
||||
lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
|
||||
timestamp = 0;
|
||||
}
|
||||
|
||||
ulong get_timer_masked(void)
|
||||
{
|
||||
ulong val = __raw_readl(&cur_gpt->counter);
|
||||
val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
|
||||
val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
|
||||
if (val >= lastinc)
|
||||
timestamp += (val - lastinc);
|
||||
else
|
||||
timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
|
||||
timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
|
||||
- lastinc) + val;
|
||||
lastinc = val;
|
||||
return timestamp;
|
||||
|
@ -106,7 +106,7 @@ void set_timer(ulong t)
|
|||
void __udelay(unsigned long usec)
|
||||
{
|
||||
unsigned long now, start, tmo;
|
||||
tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000;
|
||||
tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
|
||||
|
||||
if (!tmo)
|
||||
tmo = 1;
|
|
@ -78,13 +78,13 @@ _armboot_start:
|
|||
/*
|
||||
* These are defined in the board-specific linker script.
|
||||
*/
|
||||
.globl _bss_start
|
||||
_bss_start:
|
||||
.word __bss_start
|
||||
.globl _bss_start_ofs
|
||||
_bss_start_ofs:
|
||||
.word __bss_start - _start
|
||||
|
||||
.globl _bss_end
|
||||
_bss_end:
|
||||
.word _end
|
||||
.globl _bss_end_ofs
|
||||
_bss_end_ofs:
|
||||
.word _end - _start
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* IRQ stack memory (calculated at run-time) */
|
||||
|
@ -104,29 +104,29 @@ FIQ_STACK_START:
|
|||
IRQ_STACK_START_IN:
|
||||
.word 0x0badc0de
|
||||
|
||||
.globl _datarel_start
|
||||
_datarel_start:
|
||||
.word __datarel_start
|
||||
.globl _datarel_start_ofs
|
||||
_datarel_start_ofs:
|
||||
.word __datarel_start - _start
|
||||
|
||||
.globl _datarelrolocal_start
|
||||
_datarelrolocal_start:
|
||||
.word __datarelrolocal_start
|
||||
.globl _datarelrolocal_start_ofs
|
||||
_datarelrolocal_start_ofs:
|
||||
.word __datarelrolocal_start - _start
|
||||
|
||||
.globl _datarellocal_start
|
||||
_datarellocal_start:
|
||||
.word __datarellocal_start
|
||||
.globl _datarellocal_start_ofs
|
||||
_datarellocal_start_ofs:
|
||||
.word __datarellocal_start - _start
|
||||
|
||||
.globl _datarelro_start
|
||||
_datarelro_start:
|
||||
.word __datarelro_start
|
||||
.globl _datarelro_start_ofs
|
||||
_datarelro_start_ofs:
|
||||
.word __datarelro_start - _start
|
||||
|
||||
.globl _got_start
|
||||
_got_start:
|
||||
.word __got_start
|
||||
.globl _got_start_ofs
|
||||
_got_start_ofs:
|
||||
.word __got_start - _start
|
||||
|
||||
.globl _got_end
|
||||
_got_end:
|
||||
.word __got_end
|
||||
.globl _got_end_Ofs
|
||||
_got_end_ofs:
|
||||
.word __got_end - _start
|
||||
|
||||
/*
|
||||
* the actual reset code
|
||||
|
@ -198,9 +198,8 @@ stack_setup:
|
|||
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||
adr r0, _start
|
||||
ldr r2, _TEXT_BASE
|
||||
ldr r3, _bss_start
|
||||
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||
add r2, r0, r2 /* r2 <- source end address */
|
||||
ldr r3, _bss_start_ofs
|
||||
add r2, r0, r3 /* r2 <- source end address */
|
||||
cmp r0, r6
|
||||
#ifndef CONFIG_PRELOADER
|
||||
beq jump_2_ram
|
||||
|
@ -213,33 +212,51 @@ copy_loop:
|
|||
blo copy_loop
|
||||
|
||||
#ifndef CONFIG_PRELOADER
|
||||
/* fix got entries */
|
||||
ldr r1, _TEXT_BASE
|
||||
mov r0, r7 /* reloc addr */
|
||||
ldr r2, _got_start /* addr in Flash */
|
||||
ldr r3, _got_end /* addr in Flash */
|
||||
sub r3, r3, r1
|
||||
add r3, r3, r0
|
||||
sub r2, r2, r1
|
||||
add r2, r2, r0
|
||||
|
||||
/*
|
||||
* fix .rel.dyn relocations
|
||||
*/
|
||||
ldr r0, _TEXT_BASE /* r0 <- Text base */
|
||||
sub r9, r7, r0 /* r9 <- relocation offset */
|
||||
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
|
||||
add r10, r10, r0 /* r10 <- sym table in FLASH */
|
||||
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
|
||||
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
|
||||
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
|
||||
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
|
||||
fixloop:
|
||||
ldr r4, [r2]
|
||||
sub r4, r4, r1
|
||||
add r4, r4, r0
|
||||
str r4, [r2]
|
||||
add r2, r2, #4
|
||||
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
|
||||
add r0, r9 /* r0 <- location to fix up in RAM */
|
||||
ldr r1, [r2, #4]
|
||||
and r8, r1, #0xff
|
||||
cmp r8, #23 /* relative fixup? */
|
||||
beq fixrel
|
||||
cmp r8, #2 /* absolute fixup? */
|
||||
beq fixabs
|
||||
/* ignore unknown type of fixup */
|
||||
b fixnext
|
||||
fixabs:
|
||||
/* absolute fix: set location to (offset) symbol value */
|
||||
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
|
||||
add r1, r10, r1 /* r1 <- address of symbol in table */
|
||||
ldr r1, [r1, #4] /* r1 <- symbol value */
|
||||
add r1, r9 /* r1 <- relocated sym addr */
|
||||
b fixnext
|
||||
fixrel:
|
||||
/* relative fix: increase location by offset */
|
||||
ldr r1, [r0]
|
||||
add r1, r1, r9
|
||||
fixnext:
|
||||
str r1, [r0]
|
||||
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
|
||||
cmp r2, r3
|
||||
bne fixloop
|
||||
blo fixloop
|
||||
|
||||
clear_bss:
|
||||
ldr r0, _bss_start
|
||||
ldr r1, _bss_end
|
||||
ldr r0, _bss_start_ofs
|
||||
ldr r1, _bss_end_ofs
|
||||
ldr r3, _TEXT_BASE /* Text base */
|
||||
mov r4, r7 /* reloc addr */
|
||||
sub r0, r0, r3
|
||||
add r0, r0, r4
|
||||
sub r1, r1, r3
|
||||
add r1, r1, r4
|
||||
mov r2, #0x00000000 /* clear */
|
||||
|
||||
|
@ -255,18 +272,26 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||
* initialization, now running from RAM.
|
||||
*/
|
||||
jump_2_ram:
|
||||
ldr r0, _TEXT_BASE
|
||||
ldr r2, _board_init_r
|
||||
sub r2, r2, r0
|
||||
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||
ldr r0, _board_init_r_ofs
|
||||
adr r1, _start
|
||||
add r0, r0, r1
|
||||
add lr, r0, r9
|
||||
/* setup parameters for board_init_r */
|
||||
mov r0, r5 /* gd_t */
|
||||
mov r1, r7 /* dest_addr */
|
||||
/* jump to it ... */
|
||||
mov lr, r2
|
||||
mov pc, lr
|
||||
|
||||
_board_init_r: .word board_init_r
|
||||
_board_init_r_ofs:
|
||||
.word board_init_r - _start
|
||||
|
||||
_rel_dyn_start_ofs:
|
||||
.word __rel_dyn_start - _start
|
||||
_rel_dyn_end_ofs:
|
||||
.word __rel_dyn_end - _start
|
||||
_dynsym_start_ofs:
|
||||
.word __dynsym_start - _start
|
||||
|
||||
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||
/*
|
||||
* the actual reset code
|
||||
|
|
|
@ -53,6 +53,13 @@ SECTIONS
|
|||
__datarelro_start = .;
|
||||
*(.data.rel.ro)
|
||||
}
|
||||
. = ALIGN(4);
|
||||
__rel_dyn_start = .;
|
||||
.rel.dyn : { *(.rel.dyn) }
|
||||
__rel_dyn_end = .;
|
||||
|
||||
__dynsym_start = .;
|
||||
.dynsym : { *(.dynsym) }
|
||||
|
||||
__got_start = .;
|
||||
. = ALIGN(4);
|
||||
|
|
|
@ -30,10 +30,11 @@
|
|||
* CPU specific code
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/system.h>
|
||||
#include <command.h>
|
||||
#include <common.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
|
||||
static void cache_flush(void);
|
||||
|
||||
|
@ -71,17 +72,249 @@ void set_GPIO_mode(int gpio_mode)
|
|||
{
|
||||
int gpio = gpio_mode & GPIO_MD_MASK_NR;
|
||||
int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
|
||||
int gafr;
|
||||
int val;
|
||||
|
||||
/* This below changes direction setting of GPIO "gpio" */
|
||||
val = readl(GPDR(gpio));
|
||||
|
||||
if (gpio_mode & GPIO_MD_MASK_DIR)
|
||||
{
|
||||
GPDR(gpio) |= GPIO_bit(gpio);
|
||||
}
|
||||
val |= GPIO_bit(gpio);
|
||||
else
|
||||
{
|
||||
GPDR(gpio) &= ~GPIO_bit(gpio);
|
||||
}
|
||||
gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
|
||||
GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
|
||||
val &= ~GPIO_bit(gpio);
|
||||
|
||||
writel(val, GPDR(gpio));
|
||||
|
||||
/* This below updates only AF of GPIO "gpio" */
|
||||
val = readl(GAFR(gpio));
|
||||
val &= ~(0x3 << (((gpio) & 0xf) * 2));
|
||||
val |= fn << (((gpio) & 0xf) * 2);
|
||||
writel(val, GAFR(gpio));
|
||||
}
|
||||
#endif /* CONFIG_CPU_MONAHANS */
|
||||
|
||||
void pxa_wait_ticks(int ticks)
|
||||
{
|
||||
writel(0, OSCR);
|
||||
while (readl(OSCR) < ticks)
|
||||
asm volatile("":::"memory");
|
||||
}
|
||||
|
||||
inline void writelrb(uint32_t val, uint32_t addr)
|
||||
{
|
||||
writel(val, addr);
|
||||
asm volatile("":::"memory");
|
||||
readl(addr);
|
||||
asm volatile("":::"memory");
|
||||
}
|
||||
|
||||
void pxa_dram_init(void)
|
||||
{
|
||||
uint32_t tmp;
|
||||
int i;
|
||||
/*
|
||||
* 1) Initialize Asynchronous static memory controller
|
||||
*/
|
||||
|
||||
writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
|
||||
writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
|
||||
writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
|
||||
/*
|
||||
* 2) Initialize Card Interface
|
||||
*/
|
||||
|
||||
/* MECR: Memory Expansion Card Register */
|
||||
writelrb(CONFIG_SYS_MECR_VAL, MECR);
|
||||
/* MCMEM0: Card Interface slot 0 timing */
|
||||
writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
|
||||
/* MCMEM1: Card Interface slot 1 timing */
|
||||
writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
|
||||
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
|
||||
writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
|
||||
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
|
||||
writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
|
||||
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
|
||||
writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
|
||||
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
|
||||
writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
|
||||
|
||||
/*
|
||||
* 3) Configure Fly-By DMA register
|
||||
*/
|
||||
|
||||
writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
|
||||
|
||||
/*
|
||||
* 4) Initialize Timing for Sync Memory (SDCLK0)
|
||||
*/
|
||||
|
||||
/*
|
||||
* Before accessing MDREFR we need a valid DRI field, so we set
|
||||
* this to power on defaults + DRI field.
|
||||
*/
|
||||
|
||||
/* Read current MDREFR config and zero out DRI */
|
||||
tmp = readl(MDREFR) & ~0xfff;
|
||||
/* Add user-specified DRI */
|
||||
tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
|
||||
/* Configure important bits */
|
||||
tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
|
||||
tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
|
||||
|
||||
/* Write MDREFR back */
|
||||
writelrb(tmp, MDREFR);
|
||||
|
||||
/*
|
||||
* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
|
||||
*/
|
||||
|
||||
/* Initialize SXCNFG register. Assert the enable bits.
|
||||
*
|
||||
* Write SXMRS to cause an MRS command to all enabled banks of
|
||||
* synchronous static memory. Note that SXLCR need not be written
|
||||
* at this time.
|
||||
*/
|
||||
writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
|
||||
|
||||
/*
|
||||
* 6) Initialize SDRAM
|
||||
*/
|
||||
|
||||
writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
|
||||
writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
|
||||
|
||||
/*
|
||||
* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
|
||||
* but not enable each SDRAM partition pair.
|
||||
*/
|
||||
|
||||
writelrb(CONFIG_SYS_MDCNFG_VAL &
|
||||
~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
|
||||
/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
|
||||
pxa_wait_ticks(0x300);
|
||||
|
||||
/*
|
||||
* 8) Trigger a number (usually 8) refresh cycles by attempting
|
||||
* non-burst read or write accesses to disabled SDRAM, as commonly
|
||||
* specified in the power up sequence documented in SDRAM data
|
||||
* sheets. The address(es) used for this purpose must not be
|
||||
* cacheable.
|
||||
*/
|
||||
for (i = 9; i >= 0; i--) {
|
||||
writel(i, 0xa0000000);
|
||||
asm volatile("":::"memory");
|
||||
}
|
||||
/*
|
||||
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
|
||||
*/
|
||||
|
||||
tmp = CONFIG_SYS_MDCNFG_VAL &
|
||||
(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
|
||||
tmp |= readl(MDCNFG);
|
||||
writelrb(tmp, MDCNFG);
|
||||
|
||||
/*
|
||||
* 10) Write MDMRS.
|
||||
*/
|
||||
|
||||
writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
|
||||
|
||||
/*
|
||||
* 11) Enable APD
|
||||
*/
|
||||
|
||||
if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
|
||||
tmp = readl(MDREFR);
|
||||
tmp |= MDREFR_APD;
|
||||
writelrb(tmp, MDREFR);
|
||||
}
|
||||
}
|
||||
|
||||
void pxa_gpio_setup(void)
|
||||
{
|
||||
writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
|
||||
writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
|
||||
writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
|
||||
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
|
||||
writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
|
||||
#endif
|
||||
|
||||
writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
|
||||
writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
|
||||
writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
|
||||
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
|
||||
writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
|
||||
#endif
|
||||
|
||||
writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
|
||||
writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
|
||||
writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
|
||||
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
|
||||
writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
|
||||
#endif
|
||||
|
||||
writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
|
||||
writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
|
||||
writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
|
||||
writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
|
||||
writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
|
||||
writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
|
||||
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
|
||||
writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
|
||||
writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
|
||||
#endif
|
||||
|
||||
writel(CONFIG_SYS_PSSR_VAL, PSSR);
|
||||
}
|
||||
|
||||
void pxa_interrupt_setup(void)
|
||||
{
|
||||
writel(0, ICLR);
|
||||
writel(0, ICMR);
|
||||
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
|
||||
writel(0, ICLR2);
|
||||
writel(0, ICMR2);
|
||||
#endif
|
||||
}
|
||||
|
||||
void pxa_clock_setup(void)
|
||||
{
|
||||
#ifndef CONFIG_CPU_MONAHANS
|
||||
writel(CONFIG_SYS_CKEN, CKEN);
|
||||
writel(CONFIG_SYS_CCCR, CCCR);
|
||||
asm volatile("mcr p14, 0, %0, c6, c0, 0"::"r"(2));
|
||||
#else
|
||||
/* Set CKENA/CKENB/ACCR for MH */
|
||||
#endif
|
||||
|
||||
/* enable the 32Khz oscillator for RTC and PowerManager */
|
||||
writel(OSCC_OON, OSCC);
|
||||
while(!(readl(OSCC) & OSCC_OOK))
|
||||
asm volatile("":::"memory");
|
||||
}
|
||||
|
||||
void pxa_wakeup(void)
|
||||
{
|
||||
uint32_t rcsr;
|
||||
|
||||
rcsr = readl(RCSR);
|
||||
writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
|
||||
|
||||
/* Wakeup */
|
||||
if (rcsr & RCSR_SMR) {
|
||||
writel(PSSR_PH, PSSR);
|
||||
pxa_dram_init();
|
||||
icache_disable();
|
||||
dcache_disable();
|
||||
asm volatile("mov pc, %0"::"r"(readl(PSSR)));
|
||||
}
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
pxa_gpio_setup();
|
||||
// pxa_wait_ticks(0x8000);
|
||||
pxa_wakeup();
|
||||
pxa_interrupt_setup();
|
||||
pxa_clock_setup();
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
/* FIXME: this file is PXA255 specific! What about other XScales? */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
|
||||
|
@ -93,19 +94,21 @@ struct i2c_msg {
|
|||
|
||||
static void i2c_reset( void )
|
||||
{
|
||||
ICR &= ~ICR_IUE; /* disable unit */
|
||||
ICR |= ICR_UR; /* reset the unit */
|
||||
writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
|
||||
writel(readl(ICR) | ICR_UR, ICR); /* reset the unit */
|
||||
udelay(100);
|
||||
ICR &= ~ICR_IUE; /* disable unit */
|
||||
writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
|
||||
#ifdef CONFIG_CPU_MONAHANS
|
||||
CKENB |= (CKENB_4_I2C); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
|
||||
/* | CKENB_1_PWM1 | CKENB_0_PWM0); */
|
||||
writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
|
||||
#else /* CONFIG_CPU_MONAHANS */
|
||||
CKEN |= CKEN14_I2C; /* set the global I2C clock on */
|
||||
/* set the global I2C clock on */
|
||||
writel(readl(CKEN) | CKEN14_I2C, CKEN);
|
||||
#endif
|
||||
ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */
|
||||
ICR = I2C_ICR_INIT; /* set control register values */
|
||||
ISR = I2C_ISR_INIT; /* set clear interrupt bits */
|
||||
ICR |= ICR_IUE; /* enable unit */
|
||||
writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */
|
||||
writel(I2C_ICR_INIT, ICR); /* set control reg values */
|
||||
writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */
|
||||
writel(readl(ICR) | ICR_IUE, ICR); /* enable unit */
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
|
@ -159,22 +162,26 @@ int i2c_transfer(struct i2c_msg *msg)
|
|||
goto transfer_error_bus_busy;
|
||||
|
||||
/* start transmission */
|
||||
ICR &= ~ICR_START;
|
||||
ICR &= ~ICR_STOP;
|
||||
IDBR = msg->data;
|
||||
if (msg->condition == I2C_COND_START) ICR |= ICR_START;
|
||||
if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
|
||||
if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK;
|
||||
if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
|
||||
ICR &= ~ICR_ALDIE;
|
||||
ICR |= ICR_TB;
|
||||
writel(readl(ICR) & ~ICR_START, ICR);
|
||||
writel(readl(ICR) & ~ICR_STOP, ICR);
|
||||
writel(msg->data, IDBR);
|
||||
if (msg->condition == I2C_COND_START)
|
||||
writel(readl(ICR) | ICR_START, ICR);
|
||||
if (msg->condition == I2C_COND_STOP)
|
||||
writel(readl(ICR) | ICR_STOP, ICR);
|
||||
if (msg->acknack == I2C_ACKNAK_SENDNAK)
|
||||
writel(readl(ICR) | ICR_ACKNAK, ICR);
|
||||
if (msg->acknack == I2C_ACKNAK_SENDACK)
|
||||
writel(readl(ICR) & ~ICR_ACKNAK, ICR);
|
||||
writel(readl(ICR) & ~ICR_ALDIE, ICR);
|
||||
writel(readl(ICR) | ICR_TB, ICR);
|
||||
|
||||
/* transmit register empty? */
|
||||
if (!i2c_isr_set_cleared(ISR_ITE,0))
|
||||
goto transfer_error_transmit_timeout;
|
||||
|
||||
/* clear 'transmit empty' state */
|
||||
ISR |= ISR_ITE;
|
||||
writel(readl(ISR) | ISR_ITE, ISR);
|
||||
|
||||
/* wait for ACK from slave */
|
||||
if (msg->acknack == I2C_ACKNAK_WAITACK)
|
||||
|
@ -189,23 +196,27 @@ int i2c_transfer(struct i2c_msg *msg)
|
|||
goto transfer_error_bus_busy;
|
||||
|
||||
/* start receive */
|
||||
ICR &= ~ICR_START;
|
||||
ICR &= ~ICR_STOP;
|
||||
if (msg->condition == I2C_COND_START) ICR |= ICR_START;
|
||||
if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
|
||||
if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK;
|
||||
if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
|
||||
ICR &= ~ICR_ALDIE;
|
||||
ICR |= ICR_TB;
|
||||
writel(readl(ICR) & ~ICR_START, ICR);
|
||||
writel(readl(ICR) & ~ICR_STOP, ICR);
|
||||
if (msg->condition == I2C_COND_START)
|
||||
writel(readl(ICR) | ICR_START, ICR);
|
||||
if (msg->condition == I2C_COND_STOP)
|
||||
writel(readl(ICR) | ICR_STOP, ICR);
|
||||
if (msg->acknack == I2C_ACKNAK_SENDNAK)
|
||||
writel(readl(ICR) | ICR_ACKNAK, ICR);
|
||||
if (msg->acknack == I2C_ACKNAK_SENDACK)
|
||||
writel(readl(ICR) & ~ICR_ACKNAK, ICR);
|
||||
writel(readl(ICR) & ~ICR_ALDIE, ICR);
|
||||
writel(readl(ICR) | ICR_TB, ICR);
|
||||
|
||||
/* receive register full? */
|
||||
if (!i2c_isr_set_cleared(ISR_IRF,0))
|
||||
goto transfer_error_receive_timeout;
|
||||
|
||||
msg->data = IDBR;
|
||||
msg->data = readl(IDBR);
|
||||
|
||||
/* clear 'receive empty' state */
|
||||
ISR |= ISR_IRF;
|
||||
writel(readl(ISR) | ISR_IRF, ISR);
|
||||
|
||||
break;
|
||||
|
||||
|
|
|
@ -35,6 +35,7 @@
|
|||
#include <stdio_dev.h>
|
||||
#include <lcd.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
/* #define DEBUG */
|
||||
|
||||
|
@ -56,26 +57,26 @@
|
|||
|
||||
/* 640x480x16 @ 61 Hz */
|
||||
vidinfo_t panel_info = {
|
||||
vl_col: 640,
|
||||
vl_row: 480,
|
||||
vl_width: 640,
|
||||
vl_height: 480,
|
||||
vl_clkp: CONFIG_SYS_HIGH,
|
||||
vl_oep: CONFIG_SYS_HIGH,
|
||||
vl_hsp: CONFIG_SYS_HIGH,
|
||||
vl_vsp: CONFIG_SYS_HIGH,
|
||||
vl_dp: CONFIG_SYS_HIGH,
|
||||
vl_bpix: LCD_BPP,
|
||||
vl_lbw: 0,
|
||||
vl_splt: 0,
|
||||
vl_clor: 0,
|
||||
vl_tft: 1,
|
||||
vl_hpw: 40,
|
||||
vl_blw: 56,
|
||||
vl_elw: 56,
|
||||
vl_vpw: 20,
|
||||
vl_bfw: 8,
|
||||
vl_efw: 8,
|
||||
.vl_col = 640,
|
||||
.vl_row = 480,
|
||||
.vl_width = 640,
|
||||
.vl_height = 480,
|
||||
.vl_clkp = CONFIG_SYS_HIGH,
|
||||
.vl_oep = CONFIG_SYS_HIGH,
|
||||
.vl_hsp = CONFIG_SYS_HIGH,
|
||||
.vl_vsp = CONFIG_SYS_HIGH,
|
||||
.vl_dp = CONFIG_SYS_HIGH,
|
||||
.vl_bpix = LCD_BPP,
|
||||
.vl_lbw = 0,
|
||||
.vl_splt = 0,
|
||||
.vl_clor = 0,
|
||||
.vl_tft = 1,
|
||||
.vl_hpw = 40,
|
||||
.vl_blw = 56,
|
||||
.vl_elw = 56,
|
||||
.vl_vpw = 20,
|
||||
.vl_bfw = 8,
|
||||
.vl_efw = 8,
|
||||
};
|
||||
#endif /* CONFIG_PXA_VIDEO */
|
||||
|
||||
|
@ -90,26 +91,26 @@ vidinfo_t panel_info = {
|
|||
# define REG_LCCR3 0x0340FF08
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
vl_col: 640,
|
||||
vl_row: 480,
|
||||
vl_width: 157,
|
||||
vl_height: 118,
|
||||
vl_clkp: CONFIG_SYS_HIGH,
|
||||
vl_oep: CONFIG_SYS_HIGH,
|
||||
vl_hsp: CONFIG_SYS_HIGH,
|
||||
vl_vsp: CONFIG_SYS_HIGH,
|
||||
vl_dp: CONFIG_SYS_HIGH,
|
||||
vl_bpix: LCD_BPP,
|
||||
vl_lbw: 0,
|
||||
vl_splt: 1,
|
||||
vl_clor: 1,
|
||||
vl_tft: 0,
|
||||
vl_hpw: 1,
|
||||
vl_blw: 3,
|
||||
vl_elw: 3,
|
||||
vl_vpw: 1,
|
||||
vl_bfw: 0,
|
||||
vl_efw: 0,
|
||||
.vl_col = 640,
|
||||
.vl_row = 480,
|
||||
.vl_width = 157,
|
||||
.vl_height = 118,
|
||||
.vl_clkp = CONFIG_SYS_HIGH,
|
||||
.vl_oep = CONFIG_SYS_HIGH,
|
||||
.vl_hsp = CONFIG_SYS_HIGH,
|
||||
.vl_vsp = CONFIG_SYS_HIGH,
|
||||
.vl_dp = CONFIG_SYS_HIGH,
|
||||
.vl_bpix = LCD_BPP,
|
||||
.vl_lbw = 0,
|
||||
.vl_splt = 1,
|
||||
.vl_clor = 1,
|
||||
.vl_tft = 0,
|
||||
.vl_hpw = 1,
|
||||
.vl_blw = 3,
|
||||
.vl_elw = 3,
|
||||
.vl_vpw = 1,
|
||||
.vl_bfw = 0,
|
||||
.vl_efw = 0,
|
||||
};
|
||||
#endif /* CONFIG_SHARP_LM8V31 */
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
@ -123,26 +124,26 @@ vidinfo_t panel_info = {
|
|||
# define REG_LCCR3 0x0340FF08
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
vl_col: 640,
|
||||
vl_row: 480,
|
||||
vl_width: 157,
|
||||
vl_height: 118,
|
||||
vl_clkp: CONFIG_SYS_HIGH,
|
||||
vl_oep: CONFIG_SYS_HIGH,
|
||||
vl_hsp: CONFIG_SYS_HIGH,
|
||||
vl_vsp: CONFIG_SYS_HIGH,
|
||||
vl_dp: CONFIG_SYS_HIGH,
|
||||
vl_bpix: LCD_BPP,
|
||||
vl_lbw: 0,
|
||||
vl_splt: 1,
|
||||
vl_clor: 1,
|
||||
vl_tft: 1,
|
||||
vl_hpw: 32,
|
||||
vl_blw: 144,
|
||||
vl_elw: 32,
|
||||
vl_vpw: 2,
|
||||
vl_bfw: 13,
|
||||
vl_efw: 30,
|
||||
.vl_col = 640,
|
||||
.vl_row = 480,
|
||||
.vl_width = 157,
|
||||
.vl_height = 118,
|
||||
.vl_clkp = CONFIG_SYS_HIGH,
|
||||
.vl_oep = CONFIG_SYS_HIGH,
|
||||
.vl_hsp = CONFIG_SYS_HIGH,
|
||||
.vl_vsp = CONFIG_SYS_HIGH,
|
||||
.vl_dp = CONFIG_SYS_HIGH,
|
||||
.vl_bpix = LCD_BPP,
|
||||
.vl_lbw = 0,
|
||||
.vl_splt = 1,
|
||||
.vl_clor = 1,
|
||||
.vl_tft = 1,
|
||||
.vl_hpw = 32,
|
||||
.vl_blw = 144,
|
||||
.vl_elw = 32,
|
||||
.vl_vpw = 2,
|
||||
.vl_bfw = 13,
|
||||
.vl_efw = 30,
|
||||
};
|
||||
#endif /* CONFIG_VOIPAC_LCD */
|
||||
|
||||
|
@ -156,26 +157,26 @@ vidinfo_t panel_info = {
|
|||
#define REG_LCCR3 0x0340FF20
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
vl_col: 320,
|
||||
vl_row: 240,
|
||||
vl_width: 167,
|
||||
vl_height: 109,
|
||||
vl_clkp: CONFIG_SYS_HIGH,
|
||||
vl_oep: CONFIG_SYS_HIGH,
|
||||
vl_hsp: CONFIG_SYS_HIGH,
|
||||
vl_vsp: CONFIG_SYS_HIGH,
|
||||
vl_dp: CONFIG_SYS_HIGH,
|
||||
vl_bpix: LCD_BPP,
|
||||
vl_lbw: 1,
|
||||
vl_splt: 0,
|
||||
vl_clor: 1,
|
||||
vl_tft: 0,
|
||||
vl_hpw: 1,
|
||||
vl_blw: 1,
|
||||
vl_elw: 1,
|
||||
vl_vpw: 7,
|
||||
vl_bfw: 0,
|
||||
vl_efw: 0,
|
||||
.vl_col = 320,
|
||||
.vl_row = 240,
|
||||
.vl_width = 167,
|
||||
.vl_height = 109,
|
||||
.vl_clkp = CONFIG_SYS_HIGH,
|
||||
.vl_oep = CONFIG_SYS_HIGH,
|
||||
.vl_hsp = CONFIG_SYS_HIGH,
|
||||
.vl_vsp = CONFIG_SYS_HIGH,
|
||||
.vl_dp = CONFIG_SYS_HIGH,
|
||||
.vl_bpix = LCD_BPP,
|
||||
.vl_lbw = 1,
|
||||
.vl_splt = 0,
|
||||
.vl_clor = 1,
|
||||
.vl_tft = 0,
|
||||
.vl_hpw = 1,
|
||||
.vl_blw = 1,
|
||||
.vl_elw = 1,
|
||||
.vl_vpw = 7,
|
||||
.vl_bfw = 0,
|
||||
.vl_efw = 0,
|
||||
};
|
||||
#endif /* CONFIG_HITACHI_SX14 */
|
||||
|
||||
|
@ -190,31 +191,132 @@ vidinfo_t panel_info = {
|
|||
# define REG_LCCR3 0x03b00009
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
vl_col: 240,
|
||||
vl_row: 320,
|
||||
vl_width: 240,
|
||||
vl_height: 320,
|
||||
vl_clkp: CONFIG_SYS_HIGH,
|
||||
vl_oep: CONFIG_SYS_LOW,
|
||||
vl_hsp: CONFIG_SYS_LOW,
|
||||
vl_vsp: CONFIG_SYS_LOW,
|
||||
vl_dp: CONFIG_SYS_HIGH,
|
||||
vl_bpix: LCD_BPP,
|
||||
vl_lbw: 0,
|
||||
vl_splt: 1,
|
||||
vl_clor: 1,
|
||||
vl_tft: 1,
|
||||
vl_hpw: 4,
|
||||
vl_blw: 4,
|
||||
vl_elw: 8,
|
||||
vl_vpw: 4,
|
||||
vl_bfw: 4,
|
||||
vl_efw: 8,
|
||||
.vl_col = 240,
|
||||
.vl_row = 320,
|
||||
.vl_width = 240,
|
||||
.vl_height = 320,
|
||||
.vl_clkp = CONFIG_SYS_HIGH,
|
||||
.vl_oep = CONFIG_SYS_LOW,
|
||||
.vl_hsp = CONFIG_SYS_LOW,
|
||||
.vl_vsp = CONFIG_SYS_LOW,
|
||||
.vl_dp = CONFIG_SYS_HIGH,
|
||||
.vl_bpix = LCD_BPP,
|
||||
.vl_lbw = 0,
|
||||
.vl_splt = 1,
|
||||
.vl_clor = 1,
|
||||
.vl_tft = 1,
|
||||
.vl_hpw = 4,
|
||||
.vl_blw = 4,
|
||||
.vl_elw = 8,
|
||||
.vl_vpw = 4,
|
||||
.vl_bfw = 4,
|
||||
.vl_efw = 8,
|
||||
};
|
||||
#endif /* CONFIG_LMS283GF05 */
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
#ifdef CONFIG_ACX517AKN
|
||||
|
||||
# define LCD_BPP LCD_COLOR8
|
||||
|
||||
/* you have to set lccr0 and lccr3 (including pcd) */
|
||||
# define REG_LCCR0 0x003008f9
|
||||
# define REG_LCCR3 0x03700006
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
.vl_col = 320,
|
||||
.vl_row = 320,
|
||||
.vl_width = 320,
|
||||
.vl_height = 320,
|
||||
.vl_clkp = CONFIG_SYS_HIGH,
|
||||
.vl_oep = CONFIG_SYS_LOW,
|
||||
.vl_hsp = CONFIG_SYS_LOW,
|
||||
.vl_vsp = CONFIG_SYS_LOW,
|
||||
.vl_dp = CONFIG_SYS_HIGH,
|
||||
.vl_bpix = LCD_BPP,
|
||||
.vl_lbw = 0,
|
||||
.vl_splt = 1,
|
||||
.vl_clor = 1,
|
||||
.vl_tft = 1,
|
||||
.vl_hpw = 0x04,
|
||||
.vl_blw = 0x1c,
|
||||
.vl_elw = 0x08,
|
||||
.vl_vpw = 0x01,
|
||||
.vl_bfw = 0x07,
|
||||
.vl_efw = 0x08,
|
||||
};
|
||||
#endif /* CONFIG_ACX517AKN */
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
#ifdef CONFIG_LQ038J7DH53
|
||||
|
||||
# define LCD_BPP LCD_COLOR8
|
||||
|
||||
/* you have to set lccr0 and lccr3 (including pcd) */
|
||||
# define REG_LCCR0 0x003008f9
|
||||
# define REG_LCCR3 0x03700004
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
.vl_col = 320,
|
||||
.vl_row = 480,
|
||||
.vl_width = 320,
|
||||
.vl_height = 480,
|
||||
.vl_clkp = CONFIG_SYS_HIGH,
|
||||
.vl_oep = CONFIG_SYS_LOW,
|
||||
.vl_hsp = CONFIG_SYS_LOW,
|
||||
.vl_vsp = CONFIG_SYS_LOW,
|
||||
.vl_dp = CONFIG_SYS_HIGH,
|
||||
.vl_bpix = LCD_BPP,
|
||||
.vl_lbw = 0,
|
||||
.vl_splt = 1,
|
||||
.vl_clor = 1,
|
||||
.vl_tft = 1,
|
||||
.vl_hpw = 0x04,
|
||||
.vl_blw = 0x20,
|
||||
.vl_elw = 0x01,
|
||||
.vl_vpw = 0x01,
|
||||
.vl_bfw = 0x04,
|
||||
.vl_efw = 0x01,
|
||||
};
|
||||
#endif /* CONFIG_ACX517AKN */
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
#ifdef CONFIG_LITTLETON_LCD
|
||||
# define LCD_BPP LCD_COLOR8
|
||||
|
||||
/* you have to set lccr0 and lccr3 (including pcd) */
|
||||
# define REG_LCCR0 0x003008f8
|
||||
# define REG_LCCR3 0x0300FF04
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
.vl_col = 480,
|
||||
.vl_row = 640,
|
||||
.vl_width = 480,
|
||||
.vl_height = 640,
|
||||
.vl_clkp = CONFIG_SYS_HIGH,
|
||||
.vl_oep = CONFIG_SYS_HIGH,
|
||||
.vl_hsp = CONFIG_SYS_HIGH,
|
||||
.vl_vsp = CONFIG_SYS_HIGH,
|
||||
.vl_dp = CONFIG_SYS_HIGH,
|
||||
.vl_bpix = LCD_BPP,
|
||||
.vl_lbw = 0,
|
||||
.vl_splt = 0,
|
||||
.vl_clor = 0,
|
||||
.vl_tft = 1,
|
||||
.vl_hpw = 9,
|
||||
.vl_blw = 8,
|
||||
.vl_elw = 24,
|
||||
.vl_vpw = 2,
|
||||
.vl_bfw = 2,
|
||||
.vl_efw = 4,
|
||||
};
|
||||
#endif /* CONFIG_LITTLETON_LCD */
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
#if LCD_BPP == LCD_COLOR8
|
||||
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
|
||||
#endif
|
||||
|
@ -377,12 +479,14 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
|
|||
{
|
||||
debug("Setting GPIO for 4 bit data\n");
|
||||
/* bits 58-61 */
|
||||
GPDR1 |= (0xf << 26);
|
||||
GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
|
||||
writel(readl(GPDR1) | (0xf << 26), GPDR1);
|
||||
writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
|
||||
GAFR1_U);
|
||||
|
||||
/* bits 74-77 */
|
||||
GPDR2 |= (0xf << 10);
|
||||
GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
|
||||
writel(readl(GPDR2) | (0xf << 10), GPDR2);
|
||||
writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
|
||||
GAFR2_L);
|
||||
}
|
||||
|
||||
/* 8 bit interface */
|
||||
|
@ -391,15 +495,17 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
|
|||
{
|
||||
debug("Setting GPIO for 8 bit data\n");
|
||||
/* bits 58-65 */
|
||||
GPDR1 |= (0x3f << 26);
|
||||
GPDR2 |= (0x3);
|
||||
writel(readl(GPDR1) | (0x3f << 26), GPDR1);
|
||||
writel(readl(GPDR2) | (0x3), GPDR2);
|
||||
|
||||
GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
|
||||
GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
|
||||
writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
|
||||
GAFR1_U);
|
||||
writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
|
||||
|
||||
/* bits 74-77 */
|
||||
GPDR2 |= (0xf << 10);
|
||||
GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
|
||||
writel(readl(GPDR2) | (0xf << 10), GPDR2);
|
||||
writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
|
||||
GAFR2_L);
|
||||
}
|
||||
|
||||
/* 16 bit interface */
|
||||
|
@ -407,11 +513,12 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
|
|||
{
|
||||
debug("Setting GPIO for 16 bit data\n");
|
||||
/* bits 58-77 */
|
||||
GPDR1 |= (0x3f << 26);
|
||||
GPDR2 |= 0x00003fff;
|
||||
writel(readl(GPDR1) | (0x3f << 26), GPDR1);
|
||||
writel(readl(GPDR2) | 0x00003fff, GPDR2);
|
||||
|
||||
GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
|
||||
GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
|
||||
writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
|
||||
GAFR1_U);
|
||||
writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -425,26 +532,26 @@ static void pxafb_enable_controller (vidinfo_t *vid)
|
|||
debug("Enabling LCD controller\n");
|
||||
|
||||
/* Sequence from 11.7.10 */
|
||||
LCCR3 = vid->pxa.reg_lccr3;
|
||||
LCCR2 = vid->pxa.reg_lccr2;
|
||||
LCCR1 = vid->pxa.reg_lccr1;
|
||||
LCCR0 = vid->pxa.reg_lccr0 & ~LCCR0_ENB;
|
||||
FDADR0 = vid->pxa.fdadr0;
|
||||
FDADR1 = vid->pxa.fdadr1;
|
||||
LCCR0 |= LCCR0_ENB;
|
||||
writel(vid->pxa.reg_lccr3, LCCR3);
|
||||
writel(vid->pxa.reg_lccr2, LCCR2);
|
||||
writel(vid->pxa.reg_lccr1, LCCR1);
|
||||
writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
|
||||
writel(vid->pxa.fdadr0, FDADR0);
|
||||
writel(vid->pxa.fdadr1, FDADR1);
|
||||
writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
|
||||
|
||||
#ifdef CONFIG_CPU_MONAHANS
|
||||
CKENA |= CKENA_1_LCD;
|
||||
writel(readl(CKENA) | CKENA_1_LCD, CKENA);
|
||||
#else
|
||||
CKEN |= CKEN16_LCD;
|
||||
writel(readl(CKEN) | CKEN16_LCD, CKEN);
|
||||
#endif
|
||||
|
||||
debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
|
||||
debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
|
||||
debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
|
||||
debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
|
||||
debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
|
||||
debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
|
||||
debug("FDADR0 = 0x%08x\n", readl(FDADR0));
|
||||
debug("FDADR1 = 0x%08x\n", readl(FDADR1));
|
||||
debug("LCCR0 = 0x%08x\n", readl(LCCR0));
|
||||
debug("LCCR1 = 0x%08x\n", readl(LCCR1));
|
||||
debug("LCCR2 = 0x%08x\n", readl(LCCR2));
|
||||
debug("LCCR3 = 0x%08x\n", readl(LCCR3));
|
||||
}
|
||||
|
||||
static int pxafb_init (vidinfo_t *vid)
|
||||
|
|
|
@ -31,6 +31,14 @@
|
|||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/arch/macro.h>
|
||||
|
||||
/* takes care the CP15 update has taken place */
|
||||
.macro CPWAIT reg
|
||||
mrc p15,0,\reg,c2,c0,0
|
||||
mov \reg,\reg
|
||||
sub pc,pc,#4
|
||||
.endm
|
||||
|
||||
.globl _start
|
||||
_start: b reset
|
||||
|
@ -86,11 +94,9 @@ _fiq: .word fiq
|
|||
_TEXT_BASE:
|
||||
.word CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
.globl _armboot_start
|
||||
_armboot_start:
|
||||
.word _start
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These are defined in the board-specific linker script.
|
||||
|
@ -115,7 +121,7 @@ FIQ_STACK_START:
|
|||
.word 0x0badc0de
|
||||
#endif /* CONFIG_USE_IRQ */
|
||||
|
||||
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
#ifndef CONFIG_PRELOADER
|
||||
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||
.globl IRQ_STACK_START_IN
|
||||
IRQ_STACK_START_IN:
|
||||
|
@ -159,12 +165,84 @@ reset:
|
|||
msr cpsr,r0
|
||||
|
||||
/*
|
||||
* we do sys-critical inits only at reboot,
|
||||
* not when booting from ram!
|
||||
* Enable MMU to use DCache as DRAM
|
||||
*/
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
/* Domain access -- enable for all CPs */
|
||||
ldr r0, =0x0000ffff
|
||||
mcr p15, 0, r0, c3, c0, 0
|
||||
|
||||
/* Point TTBR to MMU table */
|
||||
ldr r0, =mmu_table
|
||||
adr r2, _start
|
||||
orr r0, r2
|
||||
mcr p15, 0, r0, c2, c0, 0
|
||||
|
||||
/* !!! Hereby, check if the code is running from SRAM !!! */
|
||||
/* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code
|
||||
* is linked to 0x0 too, so this makes things easier. */
|
||||
cmp r2, #0x5c000000
|
||||
|
||||
ldreq r1, [r0]
|
||||
orreq r1, r2
|
||||
streq r1, [r0]
|
||||
|
||||
/* Kick in MMU, ICache, DCache, BTB */
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, #0x1b00
|
||||
bic r0, #0x0087
|
||||
orr r0, #0x1800
|
||||
orr r0, #0x0005
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
CPWAIT r0
|
||||
|
||||
/* Unlock Icache, Dcache */
|
||||
mcr p15, 0, r0, c9, c1, 1
|
||||
mcr p15, 0, r0, c9, c2, 1
|
||||
|
||||
/* Flush Icache, Dcache, BTB */
|
||||
mcr p15, 0, r0, c7, c7, 0
|
||||
|
||||
/* Unlock I-TLB, D-TLB */
|
||||
mcr p15, 0, r0, c10, c4, 1
|
||||
mcr p15, 0, r0, c10, c8, 1
|
||||
|
||||
/* Flush TLB */
|
||||
mcr p15, 0, r0, c8, c7, 0
|
||||
/* Allocate 4096 bytes of Dcache as RAM */
|
||||
|
||||
/* Drain pending loads and stores */
|
||||
mcr p15, 0, r0, c7, c10, 4
|
||||
|
||||
mov r4, #0x00
|
||||
mov r5, #0x00
|
||||
mov r2, #0x01
|
||||
mcr p15, 0, r0, c9, c2, 0
|
||||
CPWAIT r0
|
||||
|
||||
/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
|
||||
mov r0, #128
|
||||
mov r1, #0xa0000000
|
||||
alloc:
|
||||
mcr p15, 0, r1, c7, c2, 5
|
||||
/* Drain pending loads and stores */
|
||||
mcr p15, 0, r0, c7, c10, 4
|
||||
strd r4, [r1], #8
|
||||
strd r4, [r1], #8
|
||||
strd r4, [r1], #8
|
||||
strd r4, [r1], #8
|
||||
subs r0, #0x01
|
||||
bne alloc
|
||||
/* Drain pending loads and stores */
|
||||
mcr p15, 0, r0, c7, c10, 4
|
||||
mov r2, #0x00
|
||||
mcr p15, 0, r2, c9, c2, 0
|
||||
CPWAIT r0
|
||||
|
||||
/* Jump to 0x0 ( + offset) if running from SRAM */
|
||||
adr r0, zerojmp
|
||||
bic r0, #0x5c000000
|
||||
mov pc, r0
|
||||
zerojmp:
|
||||
|
||||
/* Set stackpointer in internal RAM to call board_init_f */
|
||||
call_board_init_f:
|
||||
|
@ -201,11 +279,13 @@ stack_setup:
|
|||
beq clear_bss
|
||||
|
||||
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||
stmfd sp!, {r0-r12}
|
||||
copy_loop:
|
||||
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||
ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */
|
||||
stmia r6!, {r3-r5, r7-r11} /* copy to target address [r1] */
|
||||
cmp r0, r2 /* until source end address [r2] */
|
||||
blo copy_loop
|
||||
ldmfd sp!, {r0-r12}
|
||||
|
||||
#ifndef CONFIG_PRELOADER
|
||||
/* fix got entries */
|
||||
|
@ -274,218 +354,28 @@ _board_init_r: .word board_init_r
|
|||
|
||||
/****************************************************************************/
|
||||
/* */
|
||||
/* the actual reset code */
|
||||
/* the actual reset code for OneNAND IPL */
|
||||
/* */
|
||||
/****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_PXA27X
|
||||
#error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM
|
||||
#endif
|
||||
|
||||
reset:
|
||||
mrs r0,cpsr /* set the CPU to SVC32 mode */
|
||||
bic r0,r0,#0x1f /* (superviser mode, M=10011) */
|
||||
/* Set CPU to SVC32 mode */
|
||||
mrs r0,cpsr
|
||||
bic r0,r0,#0x1f
|
||||
orr r0,r0,#0x13
|
||||
msr cpsr,r0
|
||||
|
||||
/*
|
||||
* we do sys-critical inits only at reboot,
|
||||
* not when booting from RAM!
|
||||
*/
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
bl cpu_init_crit /* we do sys-critical inits */
|
||||
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
/* Point stack at the end of SRAM and leave 32 words for abort-stack */
|
||||
ldr sp, =0x5c03ff80
|
||||
|
||||
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||
relocate: /* relocate U-Boot to RAM */
|
||||
adr r0, _start /* r0 <- current position of code */
|
||||
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
|
||||
#ifndef CONFIG_PRELOADER
|
||||
cmp r0, r1 /* don't reloc during debug */
|
||||
beq stack_setup
|
||||
#endif
|
||||
/* Start OneNAND IPL */
|
||||
ldr pc, =start_oneboot
|
||||
|
||||
ldr r2, _armboot_start
|
||||
ldr r3, _bss_start
|
||||
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||
add r2, r0, r2 /* r2 <- source end address */
|
||||
|
||||
copy_loop:
|
||||
ldmia r0!, {r3-r10} /* copy from source address [r0] */
|
||||
stmia r1!, {r3-r10} /* copy to target address [r1] */
|
||||
cmp r0, r2 /* until source end address [r2] */
|
||||
blo copy_loop
|
||||
#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
|
||||
|
||||
/* Set up the stack */
|
||||
stack_setup:
|
||||
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
|
||||
#ifdef CONFIG_PRELOADER
|
||||
sub sp, r0, #128 /* leave 32 words for abort-stack */
|
||||
#else
|
||||
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
|
||||
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
|
||||
#endif /* CONFIG_USE_IRQ */
|
||||
sub sp, r0, #12 /* leave 3 words for abort-stack */
|
||||
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
|
||||
#endif
|
||||
|
||||
clear_bss:
|
||||
ldr r0, _bss_start /* find start of bss segment */
|
||||
ldr r1, _bss_end /* stop here */
|
||||
mov r2, #0x00000000 /* clear */
|
||||
|
||||
#ifndef CONFIG_PRELOADER
|
||||
clbss_l:str r2, [r0] /* clear loop... */
|
||||
add r0, r0, #4
|
||||
cmp r0, r1
|
||||
blo clbss_l
|
||||
#endif
|
||||
|
||||
ldr pc, _start_armboot
|
||||
|
||||
#ifdef CONFIG_ONENAND_IPL
|
||||
_start_armboot: .word start_oneboot
|
||||
#else
|
||||
_start_armboot: .word start_armboot
|
||||
#endif
|
||||
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||
|
||||
/****************************************************************************/
|
||||
/* */
|
||||
/* CPU_init_critical registers */
|
||||
/* */
|
||||
/* - setup important registers */
|
||||
/* - setup memory timing */
|
||||
/* */
|
||||
/****************************************************************************/
|
||||
/* mk@tbd: Fix this! */
|
||||
#undef RCSR
|
||||
#undef ICMR
|
||||
#undef OSMR3
|
||||
#undef OSCR
|
||||
#undef OWER
|
||||
#undef OIER
|
||||
#undef CCCR
|
||||
|
||||
/* Interrupt-Controller base address */
|
||||
IC_BASE: .word 0x40d00000
|
||||
#define ICMR 0x04
|
||||
|
||||
/* Reset-Controller */
|
||||
RST_BASE: .word 0x40f00030
|
||||
#define RCSR 0x00
|
||||
|
||||
/* Operating System Timer */
|
||||
OSTIMER_BASE: .word 0x40a00000
|
||||
#define OSMR3 0x0C
|
||||
#define OSCR 0x10
|
||||
#define OWER 0x18
|
||||
#define OIER 0x1C
|
||||
|
||||
/* Clock Manager Registers */
|
||||
#ifdef CONFIG_CPU_MONAHANS
|
||||
# ifndef CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
|
||||
# error "You have to define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO!!"
|
||||
# endif /* !CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO */
|
||||
# ifndef CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
|
||||
# define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
|
||||
# endif /* !CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO */
|
||||
#else /* !CONFIG_CPU_MONAHANS */
|
||||
#ifdef CONFIG_SYS_CPUSPEED
|
||||
CC_BASE: .word 0x41300000
|
||||
#define CCCR 0x00
|
||||
cpuspeed: .word CONFIG_SYS_CPUSPEED
|
||||
#else /* !CONFIG_SYS_CPUSPEED */
|
||||
#error "You have to define CONFIG_SYS_CPUSPEED!!"
|
||||
#endif /* CONFIG_SYS_CPUSPEED */
|
||||
#endif /* CONFIG_CPU_MONAHANS */
|
||||
|
||||
/* takes care the CP15 update has taken place */
|
||||
.macro CPWAIT reg
|
||||
mrc p15,0,\reg,c2,c0,0
|
||||
mov \reg,\reg
|
||||
sub pc,pc,#4
|
||||
.endm
|
||||
|
||||
cpu_init_crit:
|
||||
|
||||
/* mask all IRQs */
|
||||
#ifndef CONFIG_CPU_MONAHANS
|
||||
ldr r0, IC_BASE
|
||||
mov r1, #0x00
|
||||
str r1, [r0, #ICMR]
|
||||
#else /* CONFIG_CPU_MONAHANS */
|
||||
/* Step 1 - Enable CP6 permission */
|
||||
mrc p15, 0, r1, c15, c1, 0 @ read CPAR
|
||||
orr r1, r1, #0x40
|
||||
mcr p15, 0, r1, c15, c1, 0
|
||||
CPWAIT r1
|
||||
|
||||
/* Step 2 - Mask ICMR & ICMR2 */
|
||||
mov r1, #0
|
||||
mcr p6, 0, r1, c1, c0, 0 @ ICMR
|
||||
mcr p6, 0, r1, c7, c0, 0 @ ICMR2
|
||||
|
||||
/* turn off all clocks but the ones we will definitly require */
|
||||
ldr r1, =CKENA
|
||||
ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
|
||||
str r2, [r1]
|
||||
ldr r1, =CKENB
|
||||
ldr r2, =(CKENB_6_IRQ)
|
||||
str r2, [r1]
|
||||
#endif /* !CONFIG_CPU_MONAHANS */
|
||||
|
||||
/* set clock speed */
|
||||
#ifdef CONFIG_CPU_MONAHANS
|
||||
ldr r0, =ACCR
|
||||
ldr r1, =(((CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
|
||||
str r1, [r0]
|
||||
#else /* !CONFIG_CPU_MONAHANS */
|
||||
#ifdef CONFIG_SYS_CPUSPEED
|
||||
ldr r0, CC_BASE
|
||||
ldr r1, cpuspeed
|
||||
str r1, [r0, #CCCR]
|
||||
mov r0, #2
|
||||
mcr p14, 0, r0, c6, c0, 0
|
||||
|
||||
setspeed_done:
|
||||
|
||||
#endif /* CONFIG_SYS_CPUSPEED */
|
||||
#endif /* CONFIG_CPU_MONAHANS */
|
||||
|
||||
/*
|
||||
* before relocating, we have to setup RAM timing
|
||||
* because memory timing is board-dependend, you will
|
||||
* find a lowlevel_init.S in your board directory.
|
||||
*/
|
||||
mov ip, lr
|
||||
bl lowlevel_init
|
||||
mov lr, ip
|
||||
|
||||
/* Memory interfaces are working. Disable MMU and enable I-cache. */
|
||||
/* mk: hmm, this is not in the monahans docs, leave it now but
|
||||
* check here if it doesn't work :-) */
|
||||
|
||||
ldr r0, =0x2001 /* enable access to all coproc. */
|
||||
mcr p15, 0, r0, c15, c1, 0
|
||||
CPWAIT r0
|
||||
|
||||
mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
|
||||
CPWAIT r0
|
||||
|
||||
mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
|
||||
CPWAIT r0
|
||||
|
||||
mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
|
||||
CPWAIT r0
|
||||
|
||||
/* Enable the Icache */
|
||||
/*
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x1800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
CPWAIT
|
||||
*/
|
||||
mov pc, lr
|
||||
#endif /* #if !defined(CONFIG_ONENAND_IPL) */
|
||||
|
||||
#ifndef CONFIG_PRELOADER
|
||||
/****************************************************************************/
|
||||
|
@ -676,6 +566,12 @@ fiq:
|
|||
/* perform a watchdog timeout for a soft reset. */
|
||||
/* */
|
||||
/****************************************************************************/
|
||||
/* Operating System Timer */
|
||||
OSTIMER_BASE: .word 0x40a00000
|
||||
#define OSMR3 0x0C
|
||||
#define OSCR 0x10
|
||||
#define OWER 0x18
|
||||
#define OIER 0x1C
|
||||
|
||||
.align 5
|
||||
.globl reset_cpu
|
||||
|
@ -703,3 +599,25 @@ reset_cpu:
|
|||
reset_endless:
|
||||
|
||||
b reset_endless
|
||||
|
||||
#ifndef CONFIG_PRELOADER
|
||||
.section .mmudata, "a"
|
||||
.align 14
|
||||
.globl mmu_table
|
||||
mmu_table:
|
||||
/* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
|
||||
.set __base, 0
|
||||
.rept 0xa00
|
||||
.word (__base << 20) | 0xc12
|
||||
.set __base, __base + 1
|
||||
.endr
|
||||
|
||||
/* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
|
||||
.word (0xa00 << 20) | 0x1c1e
|
||||
|
||||
.set __base, 0xa01
|
||||
.rept 0x1000 - 0xa01
|
||||
.word (__base << 20) | 0xc12
|
||||
.set __base, __base + 1
|
||||
.endr
|
||||
#endif
|
||||
|
|
|
@ -26,8 +26,9 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <div64.h>
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
|
@ -86,7 +87,7 @@ void __udelay (unsigned long usec)
|
|||
|
||||
void reset_timer_masked (void)
|
||||
{
|
||||
OSCR = 0;
|
||||
writel(0, OSCR);
|
||||
}
|
||||
|
||||
ulong get_timer_masked (void)
|
||||
|
@ -113,7 +114,7 @@ void udelay_masked (unsigned long usec)
|
|||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return OSCR;
|
||||
return readl(OSCR);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -27,85 +27,78 @@
|
|||
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
|
||||
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <usb.h>
|
||||
|
||||
int usb_cpu_init(void)
|
||||
{
|
||||
#if defined(CONFIG_CPU_MONAHANS)
|
||||
/* Enable USB host clock. */
|
||||
CKENA |= (CKENA_2_USBHOST | CKENA_20_UDC);
|
||||
writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
|
||||
udelay(100);
|
||||
#endif
|
||||
#if defined(CONFIG_PXA27X)
|
||||
/* Enable USB host clock. */
|
||||
CKEN |= CKEN10_USBHOST;
|
||||
writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_MONAHANS)
|
||||
/* Configure Port 2 for Host (USB Client Registers) */
|
||||
UP2OCR = 0x3000c;
|
||||
writel(0x3000c, UP2OCR);
|
||||
#endif
|
||||
|
||||
UHCHR |= UHCHR_FHR;
|
||||
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
|
||||
wait_ms(11);
|
||||
UHCHR &= ~UHCHR_FHR;
|
||||
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
|
||||
|
||||
UHCHR |= UHCHR_FSBIR;
|
||||
while (UHCHR & UHCHR_FSBIR)
|
||||
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
|
||||
while (readl(UHCHR) & UHCHR_FSBIR)
|
||||
udelay(1);
|
||||
|
||||
#if defined(CONFIG_CPU_MONAHANS)
|
||||
UHCHR &= ~UHCHR_SSEP0;
|
||||
writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
|
||||
#endif
|
||||
#if defined(CONFIG_PXA27X)
|
||||
UHCHR &= ~UHCHR_SSEP2;
|
||||
writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
|
||||
#endif
|
||||
UHCHR &= ~UHCHR_SSEP1;
|
||||
UHCHR &= ~UHCHR_SSE;
|
||||
writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_cpu_stop(void)
|
||||
{
|
||||
UHCHR |= UHCHR_FHR;
|
||||
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
|
||||
udelay(11);
|
||||
UHCHR &= ~UHCHR_FHR;
|
||||
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
|
||||
|
||||
UHCCOMS |= 1;
|
||||
writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS);
|
||||
udelay(10);
|
||||
|
||||
#if defined(CONFIG_CPU_MONAHANS)
|
||||
UHCHR |= UHCHR_SSEP0;
|
||||
writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
|
||||
#endif
|
||||
#if defined(CONFIG_PXA27X)
|
||||
UHCHR |= UHCHR_SSEP2;
|
||||
writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
|
||||
#endif
|
||||
writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
|
||||
|
||||
#if defined(CONFIG_CPU_MONAHANS)
|
||||
/* Disable USB host clock. */
|
||||
writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
|
||||
udelay(100);
|
||||
#endif
|
||||
#if defined(CONFIG_PXA27X)
|
||||
/* Disable USB host clock. */
|
||||
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
|
||||
#endif
|
||||
UHCHR |= UHCHR_SSEP1;
|
||||
UHCHR |= UHCHR_SSE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_cpu_init_fail(void)
|
||||
{
|
||||
UHCHR |= UHCHR_FHR;
|
||||
udelay(11);
|
||||
UHCHR &= ~UHCHR_FHR;
|
||||
|
||||
UHCCOMS |= 1;
|
||||
udelay(10);
|
||||
|
||||
#if defined(CONFIG_CPU_MONAHANS)
|
||||
UHCHR |= UHCHR_SSEP0;
|
||||
#endif
|
||||
#if defined(CONFIG_PXA27X)
|
||||
UHCHR |= UHCHR_SSEP2;
|
||||
#endif
|
||||
UHCHR |= UHCHR_SSEP1;
|
||||
UHCHR |= UHCHR_SSE;
|
||||
|
||||
return 0;
|
||||
return usb_cpu_stop();
|
||||
}
|
||||
|
||||
# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
|
||||
#if defined(CONFIG_AT91RM9200)
|
||||
#include <asm/arch-at91/at91rm9200.h>
|
||||
#define AT91_PMC_UHP AT91RM9200_PMC_UHP
|
||||
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
|
||||
#include <asm/arch/at91sam9260.h>
|
||||
#define AT91_BASE_MCI AT91SAM9260_BASE_MCI
|
||||
|
|
|
@ -20,13 +20,13 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __MACH_MX51_IOMUX_H__
|
||||
#define __MACH_MX51_IOMUX_H__
|
||||
#ifndef __MACH_MX5_IOMUX_H__
|
||||
#define __MACH_MX5_IOMUX_H__
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx51_pins.h>
|
||||
#include <asm/arch/mx5x_pins.h>
|
||||
|
||||
typedef unsigned int iomux_pin_name_t;
|
||||
|
||||
|
@ -190,4 +190,4 @@ void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
|
|||
unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
|
||||
void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
|
||||
|
||||
#endif /* __MACH_MX51_IOMUX_H__ */
|
||||
#endif /* __MACH_MX5_IOMUX_H__ */
|
|
@ -20,8 +20,8 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
|
||||
#define __ASM_ARCH_MXC_MX51_PINS_H__
|
||||
#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
|
||||
#define __ASM_ARCH_MX5_MX5X_PINS_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
@ -415,4 +415,4 @@ enum iomux_pins {
|
|||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */
|
||||
#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
|
|
@ -21,6 +21,19 @@
|
|||
#include <linux/config.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
/*
|
||||
* Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
|
||||
* PXA300/310/320 all have distinct register mappings in some cases, that's why
|
||||
* the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
|
||||
* drivers and compatibility glue with old source then.
|
||||
*/
|
||||
#ifndef CONFIG_CPU_MONAHANS
|
||||
#if defined(CONFIG_CPU_PXA300) || \
|
||||
defined(CONFIG_CPU_PXA310) || \
|
||||
defined(CONFIG_CPU_PXA320)
|
||||
#define CONFIG_CPU_MONAHANS
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These are statically mapped PCMCIA IO space for designs using it as a
|
||||
|
@ -51,54 +64,6 @@
|
|||
* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
|
||||
*/
|
||||
|
||||
/* FIXME: Only this does work for u-boot... find out why... [RS] */
|
||||
#define UBOOT_REG_FIX 1
|
||||
|
||||
#ifndef UBOOT_REG_FIX
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
|
||||
#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
|
||||
|
||||
/*
|
||||
* This __REG() version gives the same results as the one above, except
|
||||
* that we are fooling gcc somehow so it generates far better and smaller
|
||||
* assembly code for access to contigous registers. It's a shame that gcc
|
||||
* doesn't guess this by itself.
|
||||
*/
|
||||
#include <asm/types.h>
|
||||
typedef struct { volatile u32 offset[4096]; } __regbase;
|
||||
# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
|
||||
# define __REG(x) __REGP(io_p2v(x))
|
||||
#endif
|
||||
|
||||
/* Let's kick gcc's ass again... */
|
||||
# define __REG2(x,y) \
|
||||
( __builtin_constant_p(y) ? (__REG((x) + (y))) \
|
||||
: (*(volatile u32 *)((u32)&__REG(x) + (y))) )
|
||||
|
||||
# define __PREG(x) (io_v2p((u32)&(x)))
|
||||
|
||||
#else
|
||||
|
||||
# define __REG(x) io_p2v(x)
|
||||
# define __PREG(x) io_v2p(x)
|
||||
|
||||
# undef io_p2v
|
||||
# undef __REG
|
||||
# ifndef __ASSEMBLY__
|
||||
# define io_p2v(PhAdd) (PhAdd)
|
||||
# define __REG(x) (*((volatile u32 *)io_p2v(x)))
|
||||
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
|
||||
# else
|
||||
# define __REG(x) (x)
|
||||
# ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */
|
||||
# define __REG_2(x) (x)
|
||||
# define __REG_3(x) (x)
|
||||
# endif
|
||||
# endif
|
||||
#endif /* UBOOT_REG_FIX */
|
||||
|
||||
#include "pxa-regs.h"
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
|
|
@ -102,7 +102,11 @@
|
|||
/*
|
||||
* This macro sets up the Memory controller of the PXA2xx CPU
|
||||
*
|
||||
* Clobbered regs: r3, r4, r5
|
||||
* WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE
|
||||
* and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not
|
||||
* use this regs for other purpose inside this macro.
|
||||
*
|
||||
* Clobbered regs: r3, r4, r5, r6, r7
|
||||
*/
|
||||
.macro pxa_mem_setup
|
||||
/* This comes handy when setting MDREFR */
|
||||
|
@ -157,7 +161,7 @@
|
|||
bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
|
||||
|
||||
ldr r4, =CONFIG_SYS_MDREFR_VAL
|
||||
mov r6, r4
|
||||
mov r7, r4
|
||||
lsl r4, #20
|
||||
lsr r4, #20 /* Get a valid DRI field */
|
||||
|
||||
|
@ -187,12 +191,12 @@
|
|||
* 6) Initialize SDRAM
|
||||
*/
|
||||
|
||||
bic r6, #MDREFR_SLFRSH
|
||||
str r6, [r3, #MDREFR_OFFSET]
|
||||
bic r7, #MDREFR_SLFRSH
|
||||
str r7, [r3, #MDREFR_OFFSET]
|
||||
ldr r4, [r3, #MDREFR_OFFSET]
|
||||
|
||||
orr r6, #MDREFR_E1PIN
|
||||
str r6, [r3, #MDREFR_OFFSET]
|
||||
orr r7, #MDREFR_E1PIN
|
||||
str r7, [r3, #MDREFR_OFFSET]
|
||||
ldr r4, [r3, #MDREFR_OFFSET]
|
||||
|
||||
/*
|
||||
|
@ -250,8 +254,8 @@
|
|||
*/
|
||||
|
||||
ldr r4, [r3, #MDREFR_OFFSET]
|
||||
and r6, r6, #MDREFR_APD
|
||||
orr r4, r4, r6
|
||||
and r7, r7, #MDREFR_APD
|
||||
orr r4, r4, r7
|
||||
str r4, [r3, #MDREFR_OFFSET]
|
||||
ldr r4, [r3, #MDREFR_OFFSET]
|
||||
.endm
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -21,8 +21,9 @@
|
|||
#ifndef _ASM_CONFIG_H_
|
||||
#define _ASM_CONFIG_H_
|
||||
|
||||
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
/* Relocation to SDRAM works on all ARM boards */
|
||||
#define CONFIG_RELOC_FIXUP_WORKS
|
||||
#endif
|
||||
|
||||
#define CONFIG_LMB
|
||||
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
|
||||
#endif
|
||||
|
|
|
@ -47,6 +47,20 @@ typedef struct global_data {
|
|||
#ifdef CONFIG_FSL_ESDHC
|
||||
unsigned long sdhc_clk;
|
||||
#endif
|
||||
#ifdef CONFIG_AT91FAMILY
|
||||
/* "static data" needed by at91's clock.c */
|
||||
unsigned long cpu_clk_rate_hz;
|
||||
unsigned long main_clk_rate_hz;
|
||||
unsigned long mck_rate_hz;
|
||||
unsigned long plla_rate_hz;
|
||||
unsigned long pllb_rate_hz;
|
||||
unsigned long at91_pllb_usb_init;
|
||||
/* "static data" needed by at91's timer.c */
|
||||
unsigned long timer_rate_hz;
|
||||
unsigned long tbl;
|
||||
unsigned long tbu;
|
||||
unsigned long long timer_reset_value;
|
||||
#endif
|
||||
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
unsigned long relocaddr; /* Start address of U-Boot in RAM */
|
||||
phys_size_t ram_size; /* RAM size */
|
||||
|
|
|
@ -30,18 +30,18 @@
|
|||
#define _U_BOOT_ARM_H_ 1
|
||||
|
||||
/* for the following variables, see start.S */
|
||||
extern ulong _bss_start; /* code + data end == BSS start */
|
||||
extern ulong _bss_end; /* BSS end */
|
||||
extern ulong _bss_start_ofs; /* BSS start relative to _start */
|
||||
extern ulong _bss_end_ofs; /* BSS end relative to _start */
|
||||
extern ulong IRQ_STACK_START; /* top of IRQ stack */
|
||||
extern ulong FIQ_STACK_START; /* top of FIQ stack */
|
||||
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||
extern ulong _armboot_start; /* code start */
|
||||
extern ulong _armboot_start_ofs; /* code start */
|
||||
#else
|
||||
extern ulong _TEXT_BASE; /* code start */
|
||||
extern ulong _datarel_start;
|
||||
extern ulong _datarelrolocal_start;
|
||||
extern ulong _datarellocal_start;
|
||||
extern ulong _datarelro_start;
|
||||
extern ulong _datarel_start_ofs;
|
||||
extern ulong _datarelrolocal_start_ofs;
|
||||
extern ulong _datarellocal_start_ofs;
|
||||
extern ulong _datarelro_start_ofs;
|
||||
extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */
|
||||
#endif
|
||||
|
||||
|
|
|
@ -147,7 +147,7 @@ static int display_banner (void)
|
|||
#else
|
||||
_armboot_start,
|
||||
#endif
|
||||
_bss_start, _bss_end);
|
||||
_bss_start_ofs+_TEXT_BASE, _bss_end_ofs+_TEXT_BASE);
|
||||
#ifdef CONFIG_MODEM_SUPPORT
|
||||
debug ("Modem Support enabled\n");
|
||||
#endif
|
||||
|
@ -508,7 +508,7 @@ void board_init_f (ulong bootflag)
|
|||
|
||||
memset ((void*)gd, 0, sizeof (gd_t));
|
||||
|
||||
gd->mon_len = _bss_end - _TEXT_BASE;
|
||||
gd->mon_len = _bss_end_ofs;
|
||||
|
||||
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
|
||||
if ((*init_fnc_ptr)() != 0) {
|
||||
|
@ -670,6 +670,7 @@ static char *failed = "*** failed ***\n";
|
|||
*
|
||||
************************************************************************
|
||||
*/
|
||||
|
||||
void board_init_r (gd_t *id, ulong dest_addr)
|
||||
{
|
||||
char *s;
|
||||
|
@ -693,7 +694,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
|
||||
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
|
||||
|
||||
monitor_flash_len = _bss_start - _TEXT_BASE;
|
||||
monitor_flash_len = _bss_start_ofs;
|
||||
debug ("monitor flash len: %08lX\n", monitor_flash_len);
|
||||
board_init(); /* Setup chipselects */
|
||||
|
||||
|
@ -895,6 +896,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
|
||||
/* NOTREACHED - no way out of command loop except booting */
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||
|
||||
void hang (void)
|
||||
|
|
|
@ -26,6 +26,9 @@
|
|||
#include <image.h>
|
||||
#include <u-boot/zlib.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <fdt.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -50,12 +53,52 @@ static void setup_end_tag (bd_t *bd);
|
|||
static struct tag *params;
|
||||
#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
|
||||
|
||||
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
|
||||
static ulong get_sp(void);
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
static int bootm_linux_fdt(int machid, bootm_headers_t *images);
|
||||
#endif
|
||||
|
||||
void arch_lmb_reserve(struct lmb *lmb)
|
||||
{
|
||||
ulong sp;
|
||||
|
||||
/*
|
||||
* Booting a (Linux) kernel image
|
||||
*
|
||||
* Allocate space for command line and board info - the
|
||||
* address should be as high as possible within the reach of
|
||||
* the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
|
||||
* memory, which means far enough below the current stack
|
||||
* pointer.
|
||||
*/
|
||||
sp = get_sp();
|
||||
debug("## Current stack ends at 0x%08lx ", sp);
|
||||
|
||||
/* adjust sp by 1K to be safe */
|
||||
sp -= 1024;
|
||||
lmb_reserve(lmb, sp,
|
||||
gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
|
||||
}
|
||||
|
||||
static void announce_and_cleanup(void)
|
||||
{
|
||||
printf("\nStarting kernel ...\n\n");
|
||||
|
||||
#ifdef CONFIG_USB_DEVICE
|
||||
{
|
||||
extern void udc_disconnect(void);
|
||||
udc_disconnect();
|
||||
}
|
||||
#endif
|
||||
cleanup_before_linux();
|
||||
}
|
||||
|
||||
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
|
||||
{
|
||||
bd_t *bd = gd->bd;
|
||||
char *s;
|
||||
int machid = bd->bi_arch_number;
|
||||
void (*theKernel)(int zero, int arch, uint params);
|
||||
void (*kernel_entry)(int zero, int arch, uint params);
|
||||
|
||||
#ifdef CONFIG_CMDLINE_TAG
|
||||
char *commandline = getenv ("bootargs");
|
||||
|
@ -64,8 +107,6 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
|
|||
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
|
||||
return 1;
|
||||
|
||||
theKernel = (void (*)(int, int, uint))images->ep;
|
||||
|
||||
s = getenv ("machid");
|
||||
if (s) {
|
||||
machid = simple_strtoul (s, NULL, 16);
|
||||
|
@ -74,8 +115,15 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
|
|||
|
||||
show_boot_progress (15);
|
||||
|
||||
#ifdef CONFIG_OF_LIBFDT
|
||||
if (images->ft_len)
|
||||
return bootm_linux_fdt(machid, images);
|
||||
#endif
|
||||
|
||||
kernel_entry = (void (*)(int, int, uint))images->ep;
|
||||
|
||||
debug ("## Transferring control to Linux (at address %08lx) ...\n",
|
||||
(ulong) theKernel);
|
||||
(ulong) kernel_entry);
|
||||
|
||||
#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
|
||||
defined (CONFIG_CMDLINE_TAG) || \
|
||||
|
@ -99,27 +147,76 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
|
|||
if (images->rd_start && images->rd_end)
|
||||
setup_initrd_tag (bd, images->rd_start, images->rd_end);
|
||||
#endif
|
||||
setup_end_tag (bd);
|
||||
setup_end_tag(bd);
|
||||
#endif
|
||||
|
||||
/* we assume that the kernel is in place */
|
||||
printf ("\nStarting kernel ...\n\n");
|
||||
announce_and_cleanup();
|
||||
|
||||
#ifdef CONFIG_USB_DEVICE
|
||||
{
|
||||
extern void udc_disconnect (void);
|
||||
udc_disconnect ();
|
||||
}
|
||||
#endif
|
||||
|
||||
cleanup_before_linux ();
|
||||
|
||||
theKernel (0, machid, bd->bi_boot_params);
|
||||
kernel_entry(0, machid, bd->bi_boot_params);
|
||||
/* does not return */
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
static int fixup_memory_node(void *blob)
|
||||
{
|
||||
bd_t *bd = gd->bd;
|
||||
int bank;
|
||||
u64 start[CONFIG_NR_DRAM_BANKS];
|
||||
u64 size[CONFIG_NR_DRAM_BANKS];
|
||||
|
||||
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
|
||||
start[bank] = bd->bi_dram[bank].start;
|
||||
size[bank] = bd->bi_dram[bank].size;
|
||||
}
|
||||
|
||||
return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
|
||||
}
|
||||
|
||||
static int bootm_linux_fdt(int machid, bootm_headers_t *images)
|
||||
{
|
||||
ulong rd_len;
|
||||
bd_t *bd = gd->bd;
|
||||
char *s;
|
||||
void (*kernel_entry)(int zero, int dt_machid, void *dtblob);
|
||||
ulong bootmap_base = getenv_bootm_low();
|
||||
ulong of_size = images->ft_len;
|
||||
char **of_flat_tree = &images->ft_addr;
|
||||
ulong *initrd_start = &images->initrd_start;
|
||||
ulong *initrd_end = &images->initrd_end;
|
||||
struct lmb *lmb = &images->lmb;
|
||||
int ret;
|
||||
|
||||
kernel_entry = (void (*)(int, int, void *))images->ep;
|
||||
|
||||
rd_len = images->rd_end - images->rd_start;
|
||||
ret = boot_ramdisk_high(lmb, images->rd_start, rd_len,
|
||||
initrd_start, initrd_end);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = boot_relocate_fdt(lmb, bootmap_base, of_flat_tree, &of_size);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
debug("## Transferring control to Linux (at address %08lx) ...\n",
|
||||
(ulong) kernel_entry);
|
||||
|
||||
fdt_chosen(*of_flat_tree, 1);
|
||||
|
||||
fixup_memory_node(*of_flat_tree);
|
||||
|
||||
fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
|
||||
|
||||
announce_and_cleanup();
|
||||
|
||||
kernel_entry(0, machid, *of_flat_tree);
|
||||
/* does not return */
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
|
||||
defined (CONFIG_CMDLINE_TAG) || \
|
||||
|
@ -239,4 +336,12 @@ static void setup_end_tag (bd_t *bd)
|
|||
params->hdr.size = 0;
|
||||
}
|
||||
|
||||
static ulong get_sp(void)
|
||||
{
|
||||
ulong ret;
|
||||
|
||||
asm("mov %0, sp" : "=r"(ret) : );
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
|
||||
|
|
|
@ -38,7 +38,7 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2)
|
|||
/* disable write buffer as well (page 2-22) */
|
||||
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
|
||||
#endif
|
||||
#ifdef CONFIG_ARMCORTEXA8
|
||||
#ifdef CONFIG_ARMV7
|
||||
void v7_flush_cache_all(void);
|
||||
|
||||
v7_flush_cache_all();
|
||||
|
|
|
@ -22,5 +22,8 @@
|
|||
#define _ASM_CONFIG_H_
|
||||
|
||||
#define CONFIG_LMB
|
||||
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
|
||||
#define CONFIG_SYS_BOOT_GET_CMDLINE
|
||||
#define CONFIG_SYS_BOOT_GET_KBD
|
||||
|
||||
#endif
|
||||
|
|
|
@ -46,12 +46,9 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
|
|||
|
||||
char *of_flat_tree = NULL;
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
ulong of_size = 0;
|
||||
|
||||
/* find flattened device tree */
|
||||
ret = boot_get_fdt (flag, argc, argv, images, &of_flat_tree, &of_size);
|
||||
if (ret)
|
||||
return 1;
|
||||
/* did generic code already find a device tree? */
|
||||
if (images->ft_len)
|
||||
of_flat_tree = images->ft_addr;
|
||||
#endif
|
||||
|
||||
theKernel = (void (*)(char *, ulong, ulong))images->ep;
|
||||
|
@ -64,9 +61,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
|
|||
|
||||
show_boot_progress (15);
|
||||
|
||||
if (!(ulong) of_flat_tree)
|
||||
of_flat_tree = (char *)simple_strtoul (argv[3], NULL, 16);
|
||||
|
||||
if (!of_flat_tree && argc > 3)
|
||||
of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
|
||||
#ifdef DEBUG
|
||||
printf ("## Transferring control to Linux (at address 0x%08lx) " \
|
||||
"ramdisk 0x%08lx, FDT 0x%08lx...\n",
|
||||
|
|
|
@ -36,11 +36,9 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
|
|||
ulong initrd_end = images->rd_end;
|
||||
char *of_flat_tree = NULL;
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
ulong of_size = 0;
|
||||
|
||||
/* find flattened device tree */
|
||||
if (boot_get_fdt(flag, argc, argv, images, &of_flat_tree, &of_size))
|
||||
return 1;
|
||||
/* did generic code already find a device tree? */
|
||||
if (images->ft_len)
|
||||
of_flat_tree = images->ft_addr;
|
||||
#endif
|
||||
if (!of_flat_tree && argc > 3)
|
||||
of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
|
||||
|
|
|
@ -22,6 +22,9 @@
|
|||
#define _ASM_CONFIG_H_
|
||||
|
||||
#define CONFIG_LMB
|
||||
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
|
||||
#define CONFIG_SYS_BOOT_GET_CMDLINE
|
||||
#define CONFIG_SYS_BOOT_GET_KBD
|
||||
|
||||
#ifndef CONFIG_MAX_MEM_MAPPED
|
||||
#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
|
||||
|
|
|
@ -22,5 +22,6 @@
|
|||
#define _ASM_CONFIG_H_
|
||||
|
||||
#define CONFIG_LMB
|
||||
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
|
||||
|
||||
#endif
|
||||
|
|
|
@ -1 +0,0 @@
|
|||
CONFIG_SYS_TEXT_BASE = 0x23f00000
|
|
@ -66,7 +66,7 @@ int board_init(void)
|
|||
|
||||
gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
#ifdef CONFIG_STATUS_LED
|
||||
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
|
||||
|
@ -134,9 +134,8 @@ void reset_phy(void)
|
|||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM;
|
||||
gd->bd->bi_dram[0].size =
|
||||
get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
|
||||
CONFIG_SYS_SDRAM_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -24,4 +24,5 @@
|
|||
# MA 02110-1301 USA
|
||||
#
|
||||
|
||||
CONFIG_SYS_TEXT_BASE = 0x00100000
|
||||
# TEXT_BASE must equal the intended FLASH location of u-boot.
|
||||
CONFIG_SYS_TEXT_BASE = 0xfff90000
|
||||
|
|
|
@ -27,11 +27,6 @@ LIB = $(obj)lib$(BOARD).a
|
|||
|
||||
COBJS-y += $(BOARD).o
|
||||
COBJS-y += led.o
|
||||
COBJS-y += misc.o
|
||||
ifdef CONFIG_HAS_DATAFLASH
|
||||
COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o
|
||||
COBJS-y += partition.o
|
||||
endif
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
|
|
|
@ -1,4 +1,8 @@
|
|||
/*
|
||||
* (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
|
||||
*
|
||||
* derived from previous work
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
|
@ -23,78 +27,44 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <exports.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/AT91RM9200.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/at91_pio.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/io.h>
|
||||
#if defined(CONFIG_DRIVER_ETHER)
|
||||
#include <at91rm9200_net.h>
|
||||
#include <dm9161.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int board_init (void)
|
||||
int board_init(void)
|
||||
{
|
||||
/* Enable Ctrlc */
|
||||
console_init_f ();
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
|
||||
/*
|
||||
* Correct IRDA resistor problem
|
||||
* Set PA23_TXD in Output
|
||||
*/
|
||||
writel(AT91C_PA23_TXD2, ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER);
|
||||
|
||||
/*
|
||||
* memory and cpu-speed are setup before relocation
|
||||
* so we do _nothing_ here
|
||||
*/
|
||||
writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
|
||||
|
||||
/* arch number of AT91RM9200EK-Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init (void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
|
||||
CONFIG_SYS_SDRAM_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DRIVER_ETHER) && defined(CONFIG_CMD_NET)
|
||||
/*
|
||||
* Name:
|
||||
* at91rm9200_GetPhyInterface
|
||||
* Description:
|
||||
* Initialise the interface functions to the PHY
|
||||
* Arguments:
|
||||
* None
|
||||
* Return value:
|
||||
* None
|
||||
*/
|
||||
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
|
||||
{
|
||||
p_phyops->Init = dm9161_InitPhy;
|
||||
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
|
||||
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
|
||||
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DRIVER_AT91EMAC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
rc = at91emac_register(bis, 0);
|
||||
return rc;
|
||||
return at91emac_register(bis, (u32) AT91_EMAC_BASE);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -1 +1,2 @@
|
|||
CONFIG_SYS_TEXT_BASE = 0x21f00000
|
||||
# currently only NOR flash booting is supported
|
||||
CONFIG_SYS_TEXT_BASE = 0x10000000
|
||||
|
|
|
@ -3,6 +3,9 @@
|
|||
* Atmel Nordic AB <www.atmel.com>
|
||||
* Ulf Samuelsson <ulf@atmel.com>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Andreas Bießmann <andreas.devel@gmail.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
|
@ -23,67 +26,62 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/AT91RM9200.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
|
||||
#define GREEN_LED AT91C_PIO_PB0
|
||||
#define YELLOW_LED AT91C_PIO_PB1
|
||||
#define RED_LED AT91C_PIO_PB2
|
||||
/* bit mask in PIO port B */
|
||||
#define GREEN_LED (1<<0)
|
||||
#define YELLOW_LED (1<<1)
|
||||
#define RED_LED (1<<2)
|
||||
|
||||
void green_LED_on(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(GREEN_LED, PIOB->PIO_CODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(GREEN_LED, &pio->piob.codr);
|
||||
}
|
||||
|
||||
void yellow_LED_on(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(YELLOW_LED, PIOB->PIO_CODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(YELLOW_LED, &pio->piob.codr);
|
||||
}
|
||||
|
||||
void red_LED_on(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(RED_LED, PIOB->PIO_CODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(RED_LED, &pio->piob.codr);
|
||||
}
|
||||
|
||||
void green_LED_off(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(GREEN_LED, PIOB->PIO_SODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(GREEN_LED, &pio->piob.sodr);
|
||||
}
|
||||
|
||||
void yellow_LED_off(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(YELLOW_LED, PIOB->PIO_SODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(YELLOW_LED, &pio->piob.sodr);
|
||||
}
|
||||
|
||||
void red_LED_off(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(RED_LED, PIOB->PIO_SODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(RED_LED, &pio->piob.sodr);
|
||||
}
|
||||
|
||||
|
||||
void coloured_LED_init (void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
AT91PS_PMC PMC = AT91C_BASE_PMC;
|
||||
at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
|
||||
/* Enable PIOB clock */
|
||||
writel((1 << AT91C_ID_PIOB), PMC->PMC_PCER);
|
||||
writel(1 << AT91_ID_PIOB, &pmc->pcer);
|
||||
|
||||
/* Disable peripherals on LEDs */
|
||||
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_PER);
|
||||
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
|
||||
/* Enable pins as outputs */
|
||||
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_OER);
|
||||
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
|
||||
/* Turn all LEDs OFF */
|
||||
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_SODR);
|
||||
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
|
||||
}
|
||||
|
|
|
@ -1,38 +0,0 @@
|
|||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/io.h>
|
||||
#include <dataflash.h>
|
||||
|
||||
int AT91F_GetMuxStatus(void)
|
||||
{
|
||||
/* Set in PIO mode */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
|
||||
/* Configure in output */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
|
||||
|
||||
if(readl(AT91C_BASE_PIOB->PIO_ODSR) & CONFIG_SYS_DATAFLASH_MMC_PIO)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void AT91F_SelectMMC(void)
|
||||
{
|
||||
/* Set in PIO mode */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
|
||||
/* Configure in output */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
|
||||
/* Set Output */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_SODR);
|
||||
}
|
||||
|
||||
void AT91F_SelectSPI(void)
|
||||
{
|
||||
/* Set in PIO mode */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
|
||||
/* Configure in output */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
|
||||
/* Clear Output */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_CODR);
|
||||
}
|
47
board/balloon3/Makefile
Normal file
47
board/balloon3/Makefile
Normal file
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# Balloon3 Support
|
||||
#
|
||||
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := balloon3.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
238
board/balloon3/balloon3.c
Normal file
238
board/balloon3/balloon3.c
Normal file
|
@ -0,0 +1,238 @@
|
|||
/*
|
||||
* Balloon3 Support
|
||||
*
|
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <serial.h>
|
||||
#include <asm/io.h>
|
||||
#include <spartan3.h>
|
||||
#include <command.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void balloon3_init_fpga(void);
|
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* We have RAM, disable cache */
|
||||
dcache_disable();
|
||||
icache_disable();
|
||||
|
||||
/* arch number of vpac270 */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = 0xa0000100;
|
||||
|
||||
/* Init the FPGA */
|
||||
balloon3_init_fpga();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct serial_device *default_serial_console(void)
|
||||
{
|
||||
return &serial_stuart_device;
|
||||
}
|
||||
|
||||
extern void pxa_dram_init(void);
|
||||
int dram_init(void)
|
||||
{
|
||||
pxa_dram_init();
|
||||
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
|
||||
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
|
||||
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
int usb_board_init(void)
|
||||
{
|
||||
writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
|
||||
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
|
||||
UHCHR);
|
||||
|
||||
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
|
||||
|
||||
while (readl(UHCHR) & UHCHR_FSBIR)
|
||||
;
|
||||
|
||||
writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
|
||||
writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
|
||||
|
||||
/* Clear any OTG Pin Hold */
|
||||
if (readl(PSSR) & PSSR_OTGPH)
|
||||
writel(readl(PSSR) | PSSR_OTGPH, PSSR);
|
||||
|
||||
writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
|
||||
writel(readl(UHCRHDA) | 0x100, UHCRHDA);
|
||||
|
||||
/* Set port power control mask bits, only 3 ports. */
|
||||
writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
|
||||
|
||||
/* enable port 2 */
|
||||
writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
|
||||
UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void usb_board_init_fail(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void usb_board_stop(void)
|
||||
{
|
||||
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
|
||||
udelay(11);
|
||||
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
|
||||
|
||||
writel(readl(UHCCOMS) | 1, UHCCOMS);
|
||||
udelay(10);
|
||||
|
||||
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FPGA)
|
||||
/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
|
||||
int fpga_pgm_fn(int nassert, int nflush, int cookie)
|
||||
{
|
||||
if (nassert)
|
||||
writel(0x80, GPCR3);
|
||||
else
|
||||
writel(0x80, GPSR3);
|
||||
if (nflush)
|
||||
writel(0x100, GPCR3);
|
||||
else
|
||||
writel(0x100, GPSR3);
|
||||
return nassert;
|
||||
}
|
||||
|
||||
/* Check GPIO83 -- INITB */
|
||||
int fpga_init_fn(int cookie)
|
||||
{
|
||||
return !(readl(GPLR2) & 0x80000);
|
||||
}
|
||||
|
||||
/* Check GPIO84 -- BUSY */
|
||||
int fpga_busy_fn(int cookie)
|
||||
{
|
||||
return !(readl(GPLR2) & 0x100000);
|
||||
}
|
||||
|
||||
/* Check GPIO111 -- DONE */
|
||||
int fpga_done_fn(int cookie)
|
||||
{
|
||||
return readl(GPLR3) & 0x8000;
|
||||
}
|
||||
|
||||
/* Configure GPIO104 as GPIO and deassert it */
|
||||
int fpga_pre_config_fn(int cookie)
|
||||
{
|
||||
writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
|
||||
writel(0x100, GPCR3);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Configure GPIO104 as nSKTSEL */
|
||||
int fpga_post_config_fn(int cookie)
|
||||
{
|
||||
writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Toggle RDnWR */
|
||||
int fpga_wr_fn(int nassert_write, int flush, int cookie)
|
||||
{
|
||||
udelay(1000);
|
||||
|
||||
if (nassert_write)
|
||||
writel(0x100, GPCR3);
|
||||
else
|
||||
writel(0x100, GPSR3);
|
||||
|
||||
return nassert_write;
|
||||
}
|
||||
|
||||
/* Write program to the FPGA */
|
||||
int fpga_wdata_fn(uchar data, int flush, int cookie)
|
||||
{
|
||||
writeb(data, 0x10f00000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Toggle Clock pin -- NO-OP */
|
||||
int fpga_clk_fn(int assert_clk, int flush, int cookie)
|
||||
{
|
||||
return assert_clk;
|
||||
}
|
||||
|
||||
/* Toggle ChipSelect pin -- NO-OP */
|
||||
int fpga_cs_fn(int assert_clk, int flush, int cookie)
|
||||
{
|
||||
return assert_clk;
|
||||
}
|
||||
|
||||
Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
|
||||
fpga_pre_config_fn,
|
||||
fpga_pgm_fn,
|
||||
fpga_init_fn,
|
||||
NULL, /* err */
|
||||
fpga_done_fn,
|
||||
fpga_clk_fn,
|
||||
fpga_cs_fn,
|
||||
fpga_wr_fn,
|
||||
NULL, /* rdata */
|
||||
fpga_wdata_fn,
|
||||
fpga_busy_fn,
|
||||
NULL, /* abort */
|
||||
fpga_post_config_fn,
|
||||
};
|
||||
|
||||
Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
|
||||
(void *)&balloon3_fpga_fns, 0);
|
||||
|
||||
/* Initialize the FPGA */
|
||||
void balloon3_init_fpga(void)
|
||||
{
|
||||
fpga_init();
|
||||
fpga_add(fpga_xilinx, &fpga);
|
||||
}
|
||||
#else
|
||||
void balloon3_init_fpga(void) {}
|
||||
#endif /* CONFIG_FPGA */
|
|
@ -22,6 +22,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -65,28 +66,30 @@ int dram_init (void)
|
|||
#ifdef CONFIG_CMD_USB
|
||||
int usb_board_init(void)
|
||||
{
|
||||
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
|
||||
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
|
||||
writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
|
||||
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
|
||||
UHCHR);
|
||||
|
||||
UHCHR |= UHCHR_FSBIR;
|
||||
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
|
||||
|
||||
while (UHCHR & UHCHR_FSBIR);
|
||||
|
||||
UHCHR &= ~UHCHR_SSE;
|
||||
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
|
||||
writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
|
||||
writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
|
||||
|
||||
/* Clear any OTG Pin Hold */
|
||||
if (PSSR & PSSR_OTGPH)
|
||||
PSSR |= PSSR_OTGPH;
|
||||
if (readl(PSSR) & PSSR_OTGPH)
|
||||
writel(readl(PSSR) | PSSR_OTGPH, PSSR);
|
||||
|
||||
UHCRHDA &= ~(0x200);
|
||||
UHCRHDA |= 0x100;
|
||||
writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
|
||||
writel(readl(UHCRHDA) | 0x100, UHCRHDA);
|
||||
|
||||
/* Set port power control mask bits, only 3 ports. */
|
||||
UHCRHDB |= (0x7<<17);
|
||||
writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
|
||||
|
||||
/* enable port 2 */
|
||||
UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
|
||||
writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
|
||||
UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -98,14 +101,14 @@ void usb_board_init_fail(void)
|
|||
|
||||
void usb_board_stop(void)
|
||||
{
|
||||
UHCHR |= UHCHR_FHR;
|
||||
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
|
||||
udelay(11);
|
||||
UHCHR &= ~UHCHR_FHR;
|
||||
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
|
||||
|
||||
UHCCOMS |= 1;
|
||||
writel(readl(UHCCOMS) | 1, UHCCOMS);
|
||||
udelay(10);
|
||||
|
||||
CKEN &= ~CKEN10_USBHOST;
|
||||
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <asm/arch/pxa-regs.h>
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -92,8 +93,8 @@ set_led (int led, int color)
|
|||
int shift = led * 2;
|
||||
unsigned long mask = 0x3 << shift;
|
||||
|
||||
CRADLE_LED_CLR_REG = mask; /* clear bits */
|
||||
CRADLE_LED_SET_REG = (color << shift); /* set bits */
|
||||
writel(mask, GPCR2); /* clear bits */
|
||||
writel((color << shift), GPSR2); /* set bits */
|
||||
udelay (5000);
|
||||
}
|
||||
|
||||
|
|
|
@ -34,10 +34,10 @@ DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
|
|||
.endm
|
||||
|
||||
.macro SET_LED val
|
||||
ldr r6, =CRADLE_LED_CLR_REG
|
||||
ldr r6, =GPCR2
|
||||
ldr r7, =0
|
||||
str r7, [r6]
|
||||
ldr r6, =CRADLE_LED_SET_REG
|
||||
ldr r6, =GPSR2
|
||||
ldr r7, =\val
|
||||
str r7, [r6]
|
||||
.endm
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -108,23 +109,23 @@ void csb226_set_led(int led, int state)
|
|||
switch(led) {
|
||||
|
||||
case 0: if (state==1) {
|
||||
GPCR0 |= CSB226_USER_LED0;
|
||||
writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
|
||||
} else if (state==0) {
|
||||
GPSR0 |= CSB226_USER_LED0;
|
||||
writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
|
||||
}
|
||||
break;
|
||||
|
||||
case 1: if (state==1) {
|
||||
GPCR0 |= CSB226_USER_LED1;
|
||||
writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
|
||||
} else if (state==0) {
|
||||
GPSR0 |= CSB226_USER_LED1;
|
||||
writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
|
||||
}
|
||||
break;
|
||||
|
||||
case 2: if (state==1) {
|
||||
GPCR0 |= CSB226_USER_LED2;
|
||||
writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
|
||||
} else if (state==0) {
|
||||
GPSR0 |= CSB226_USER_LED2;
|
||||
writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <malloc.h>
|
||||
#include <command.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -110,7 +111,7 @@ static uchar kbd_command_prefix[] = "key_cmd";
|
|||
static void get_pressed_keys(uchar *s)
|
||||
{
|
||||
unsigned long val;
|
||||
val = GPLR3;
|
||||
val = readl(GPLR3);
|
||||
|
||||
if(val & (1<<31))
|
||||
*s++ = KEYBD_KP_DKIN0;
|
||||
|
@ -124,18 +125,18 @@ static void get_pressed_keys(uchar *s)
|
|||
|
||||
static void keys_init()
|
||||
{
|
||||
CKENB |= CKENB_7_GPIO;
|
||||
writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
|
||||
udelay(100);
|
||||
|
||||
/* Configure GPIOs */
|
||||
GPIO127 = 0xa840; /* KP_DKIN0 */
|
||||
GPIO114 = 0xa840; /* KP_DKIN1 */
|
||||
GPIO125 = 0xa840; /* KP_DKIN2 */
|
||||
GPIO118 = 0xa840; /* KP_DKIN5 */
|
||||
writel(0xa840, GPIO127); /* KP_DKIN0 */
|
||||
writel(0xa840, GPIO114); /* KP_DKIN1 */
|
||||
writel(0xa840, GPIO125); /* KP_DKIN2 */
|
||||
writel(0xa840, GPIO118); /* KP_DKIN5 */
|
||||
|
||||
/* Configure GPIOs as inputs */
|
||||
GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22);
|
||||
GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22);
|
||||
writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3);
|
||||
writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3);
|
||||
|
||||
udelay(100);
|
||||
}
|
||||
|
@ -283,11 +284,11 @@ int dram_init (void)
|
|||
|
||||
void i2c_init_board()
|
||||
{
|
||||
CKENB |= (CKENB_4_I2C);
|
||||
writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
|
||||
|
||||
/* setup I2C GPIO's */
|
||||
GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */
|
||||
GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */
|
||||
writel(0x801, GPIO32); /* SCL = Alt. Fkt. 1 */
|
||||
writel(0x801, GPIO33); /* SDA = Alt. Fkt. 1 */
|
||||
}
|
||||
|
||||
/* initialize the DA9030 Power Controller */
|
||||
|
@ -295,20 +296,20 @@ static void init_DA9030()
|
|||
{
|
||||
uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
|
||||
|
||||
CKENB |= CKENB_7_GPIO;
|
||||
writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
|
||||
udelay(100);
|
||||
|
||||
/* Rising Edge on EXTON to reset DA9030 */
|
||||
GPIO17 = 0x8800; /* configure GPIO17, no pullup, -down */
|
||||
GPDR0 |= (1<<17); /* GPIO17 is output */
|
||||
GSDR0 = (1<<17);
|
||||
GPCR0 = (1<<17); /* drive GPIO17 low */
|
||||
GPSR0 = (1<<17); /* drive GPIO17 high */
|
||||
writel(0x8800, GPIO17); /* configure GPIO17, no pullup, -down */
|
||||
writel(readl(GPDR0) | (1<<17), GPDR0); /* GPIO17 is output */
|
||||
writel((1<<17), GSDR0);
|
||||
writel((1<<17), GPCR0); /* drive GPIO17 low */
|
||||
writel((1<<17), GPSR0); /* drive GPIO17 high */
|
||||
|
||||
#if CONFIG_SYS_DA9030_EXTON_DELAY
|
||||
udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY); /* wait for DA9030 */
|
||||
#endif
|
||||
GPCR0 = (1<<17); /* drive GPIO17 low */
|
||||
writel((1<<17), GPCR0); /* drive GPIO17 low */
|
||||
|
||||
/* reset the watchdog and go active (0xec) */
|
||||
val = (SYS_CONTROL_A_HWRES_ENABLE |
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
|
||||
#include <nand.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_SYS_DFC_DEBUG1
|
||||
# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
|
||||
|
@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
|||
if(bytes_multi) {
|
||||
for(i=0; i<bytes_multi; i+=4) {
|
||||
long_buf = (unsigned long*) &buf[i];
|
||||
NDDB = *long_buf;
|
||||
writel(*long_buf, NDDB);
|
||||
}
|
||||
}
|
||||
if(rest) {
|
||||
|
@ -120,7 +121,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
|
|||
if(bytes_multi) {
|
||||
for(i=0; i<bytes_multi; i+=4) {
|
||||
long_buf = (unsigned long*) &buf[i];
|
||||
*long_buf = NDDB;
|
||||
*long_buf = readl(NDDB);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -166,8 +167,8 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
|
|||
unsigned long dummy;
|
||||
|
||||
if(bytes_read < 0) {
|
||||
read_buf = NDDB;
|
||||
dummy = NDDB;
|
||||
read_buf = readl(NDDB);
|
||||
dummy = readl(NDDB);
|
||||
bytes_read = 0;
|
||||
}
|
||||
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
|
||||
|
@ -181,7 +182,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
|
|||
/* calculate delta between OSCR values start and now */
|
||||
static unsigned long get_delta(unsigned long start)
|
||||
{
|
||||
unsigned long cur = OSCR;
|
||||
unsigned long cur = readl(OSCR);
|
||||
|
||||
if(cur < start) /* OSCR overflowed */
|
||||
return (cur + (start^0xffffffff));
|
||||
|
@ -192,7 +193,7 @@ static unsigned long get_delta(unsigned long start)
|
|||
/* delay function, this doesn't belong here */
|
||||
static void wait_us(unsigned long us)
|
||||
{
|
||||
unsigned long start = OSCR;
|
||||
unsigned long start = readl(OSCR);
|
||||
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
|
||||
|
||||
while (get_delta(start) < us) {
|
||||
|
@ -202,14 +203,14 @@ static void wait_us(unsigned long us)
|
|||
|
||||
static void dfc_clear_nddb(void)
|
||||
{
|
||||
NDCR &= ~NDCR_ND_RUN;
|
||||
writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
|
||||
wait_us(CONFIG_SYS_NAND_OTHER_TO);
|
||||
}
|
||||
|
||||
/* wait_event with timeout */
|
||||
static unsigned long dfc_wait_event(unsigned long event)
|
||||
{
|
||||
unsigned long ndsr, timeout, start = OSCR;
|
||||
unsigned long ndsr, timeout, start = readl(OSCR);
|
||||
|
||||
if(!event)
|
||||
return 0xff000000;
|
||||
|
@ -221,9 +222,9 @@ static unsigned long dfc_wait_event(unsigned long event)
|
|||
* OSCR_CLK_FREQ, 1000);
|
||||
|
||||
while(1) {
|
||||
ndsr = NDSR;
|
||||
ndsr = readl(NDSR);
|
||||
if(ndsr & event) {
|
||||
NDSR |= event;
|
||||
writel(readl(NDSR) | event, NDSR);
|
||||
break;
|
||||
}
|
||||
if(get_delta(start) > timeout) {
|
||||
|
@ -243,11 +244,11 @@ static void dfc_new_cmd(void)
|
|||
|
||||
while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
|
||||
/* Clear NDSR */
|
||||
NDSR = 0xFFF;
|
||||
writel(0xfff, NDSR);
|
||||
|
||||
/* set NDCR[NDRUN] */
|
||||
if(!(NDCR & NDCR_ND_RUN))
|
||||
NDCR |= NDCR_ND_RUN;
|
||||
if (!(readl(NDCR) & NDCR_ND_RUN))
|
||||
writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
|
||||
|
||||
status = dfc_wait_event(NDSR_WRCMDREQ);
|
||||
|
||||
|
@ -357,9 +358,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
|
|||
}
|
||||
|
||||
write_cmd:
|
||||
NDCB0 = ndcb0;
|
||||
NDCB0 = ndcb1;
|
||||
NDCB0 = ndcb2;
|
||||
writel(ndcb0, NDCB0);
|
||||
writel(ndcb1, NDCB0);
|
||||
writel(ndcb2, NDCB0);
|
||||
|
||||
/* wait_event: */
|
||||
dfc_wait_event(event);
|
||||
|
@ -372,36 +373,36 @@ static void dfc_gpio_init(void)
|
|||
DFC_DEBUG2("Setting up DFC GPIO's.\n");
|
||||
|
||||
/* no idea what is done here, see zylonite.c */
|
||||
GPIO4 = 0x1;
|
||||
writel(0x1, GPIO4);
|
||||
|
||||
DF_ALE_WE1 = 0x00000001;
|
||||
DF_ALE_WE2 = 0x00000001;
|
||||
DF_nCS0 = 0x00000001;
|
||||
DF_nCS1 = 0x00000001;
|
||||
DF_nWE = 0x00000001;
|
||||
DF_nRE = 0x00000001;
|
||||
DF_IO0 = 0x00000001;
|
||||
DF_IO8 = 0x00000001;
|
||||
DF_IO1 = 0x00000001;
|
||||
DF_IO9 = 0x00000001;
|
||||
DF_IO2 = 0x00000001;
|
||||
DF_IO10 = 0x00000001;
|
||||
DF_IO3 = 0x00000001;
|
||||
DF_IO11 = 0x00000001;
|
||||
DF_IO4 = 0x00000001;
|
||||
DF_IO12 = 0x00000001;
|
||||
DF_IO5 = 0x00000001;
|
||||
DF_IO13 = 0x00000001;
|
||||
DF_IO6 = 0x00000001;
|
||||
DF_IO14 = 0x00000001;
|
||||
DF_IO7 = 0x00000001;
|
||||
DF_IO15 = 0x00000001;
|
||||
writel(0x00000001, DF_ALE_nWE1);
|
||||
writel(0x00000001, DF_ALE_nWE2);
|
||||
writel(0x00000001, DF_nCS0);
|
||||
writel(0x00000001, DF_nCS1);
|
||||
writel(0x00000001, DF_nWE);
|
||||
writel(0x00000001, DF_nRE);
|
||||
writel(0x00000001, DF_IO0);
|
||||
writel(0x00000001, DF_IO8);
|
||||
writel(0x00000001, DF_IO1);
|
||||
writel(0x00000001, DF_IO9);
|
||||
writel(0x00000001, DF_IO2);
|
||||
writel(0x00000001, DF_IO10);
|
||||
writel(0x00000001, DF_IO3);
|
||||
writel(0x00000001, DF_IO11);
|
||||
writel(0x00000001, DF_IO4);
|
||||
writel(0x00000001, DF_IO12);
|
||||
writel(0x00000001, DF_IO5);
|
||||
writel(0x00000001, DF_IO13);
|
||||
writel(0x00000001, DF_IO6);
|
||||
writel(0x00000001, DF_IO14);
|
||||
writel(0x00000001, DF_IO7);
|
||||
writel(0x00000001, DF_IO15);
|
||||
|
||||
DF_nWE = 0x1901;
|
||||
DF_nRE = 0x1901;
|
||||
DF_CLE_NOE = 0x1900;
|
||||
DF_ALE_WE1 = 0x1901;
|
||||
DF_INT_RnB = 0x1900;
|
||||
writel(0x1901, DF_nWE);
|
||||
writel(0x1901, DF_nRE);
|
||||
writel(0x1900, DF_CLE_nOE);
|
||||
writel(0x1901, DF_ALE_nWE1);
|
||||
writel(0x1900, DF_INT_RnB);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -430,7 +431,7 @@ int board_nand_init(struct nand_chip *nand)
|
|||
dfc_gpio_init();
|
||||
|
||||
/* turn on the NAND Controller Clock (104 MHz @ D0) */
|
||||
CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
|
||||
writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
|
||||
|
||||
#undef CONFIG_SYS_TIMING_TIGHT
|
||||
#ifndef CONFIG_SYS_TIMING_TIGHT
|
||||
|
@ -485,17 +486,19 @@ int board_nand_init(struct nand_chip *nand)
|
|||
tRP_high = 0;
|
||||
}
|
||||
|
||||
NDTR0CS0 = (tCH << 19) |
|
||||
writel((tCH << 19) |
|
||||
(tCS << 16) |
|
||||
(tWH << 11) |
|
||||
(tWP << 8) |
|
||||
(tRP_high << 6) |
|
||||
(tRH << 3) |
|
||||
(tRP << 0);
|
||||
(tRP << 0),
|
||||
NDTR0CS0);
|
||||
|
||||
NDTR1CS0 = (tR << 16) |
|
||||
writel((tR << 16) |
|
||||
(tWHR << 4) |
|
||||
(tAR << 0);
|
||||
(tAR << 0),
|
||||
NDTR1CS0);
|
||||
|
||||
/* If it doesn't work (unlikely) think about:
|
||||
* - ecc enable
|
||||
|
@ -512,7 +515,7 @@ int board_nand_init(struct nand_chip *nand)
|
|||
*/
|
||||
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
|
||||
|
||||
NDCR = (NDCR_SPARE_EN | /* use the spare area */
|
||||
writel(NDCR_SPARE_EN | /* use the spare area */
|
||||
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
|
||||
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
|
||||
(2 << 16) | /* read id count = 7 ???? mk@tbd */
|
||||
|
@ -528,7 +531,8 @@ int board_nand_init(struct nand_chip *nand)
|
|||
NDCR_SBERRM | /* single bit error ir masked */
|
||||
NDCR_WRDREQM | /* write data request ir masked */
|
||||
NDCR_RDDREQM | /* read data request ir masked */
|
||||
NDCR_WRCMDREQM); /* write command request ir masked */
|
||||
NDCR_WRCMDREQM, /* write command request ir masked */
|
||||
NDCR);
|
||||
|
||||
|
||||
/* wait 10 us due to cmd buffer clear reset */
|
||||
|
|
|
@ -23,7 +23,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx51_pins.h>
|
||||
#include <asm/arch/mx5x_pins.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
#include <netdev.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -48,20 +49,21 @@ int i2c_init_board(void)
|
|||
|
||||
/* disable I2C controller first, otherwhise it thinks we want to */
|
||||
/* talk to the slave port... */
|
||||
icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE);
|
||||
icr = readl(ICR);
|
||||
writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR);
|
||||
|
||||
/* set gpio pin low _before_ we change direction to output */
|
||||
GPCR(70) = GPIO_bit(70);
|
||||
writel(GPIO_bit(70), GPCR(70));
|
||||
|
||||
/* now toggle between output=low and high-impedance */
|
||||
for (i = 0; i < 20; i++) {
|
||||
GPDR(70) |= GPIO_bit(70); /* output */
|
||||
writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */
|
||||
udelay(10);
|
||||
GPDR(70) &= ~GPIO_bit(70); /* input */
|
||||
writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
ICR = icr;
|
||||
writel(icr, ICR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -76,7 +78,7 @@ int misc_init_r(void)
|
|||
char *str;
|
||||
|
||||
/* determine if the software update key is pressed during startup */
|
||||
if (GPLR0 & 0x00000800) {
|
||||
if (readl(GPLR0) & 0x00000800) {
|
||||
printf("using bootcmd_normal (sw-update button not pressed)\n");
|
||||
str = getenv("bootcmd_normal");
|
||||
} else {
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
ifdef CONFIG_NAND_SPL
|
||||
CONFIG_SYS_TEXT_BASE = 0x810c0000
|
||||
else
|
||||
CONFIG_SYS_TEXT_BASE = 0x81fc0000
|
||||
CONFIG_SYS_TEXT_BASE = 0x81200000
|
||||
endif
|
||||
|
|
|
@ -1 +1,5 @@
|
|||
# with relocation CONFIG_SYS_TEXT_BASE can be anything, and making it 0
|
||||
# makes relative and absolute relocation fixups interchangeable.
|
||||
#CONFIG_SYS_TEXT_BASE = 0
|
||||
|
||||
CONFIG_SYS_TEXT_BASE = 0xc0000000
|
||||
|
|
|
@ -1 +1 @@
|
|||
CONFIG_SYS_TEXT_BASE = 0x87f00000
|
||||
CONFIG_SYS_TEXT_BASE = 0xa0000000
|
||||
|
|
|
@ -31,12 +31,18 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
int dram_init (void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
dram_init_banksize (void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
}
|
||||
|
||||
int board_init (void)
|
||||
{
|
||||
__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
|
||||
|
|
49
board/palmld/Makefile
Normal file
49
board/palmld/Makefile
Normal file
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# Palm LifeDrive Support
|
||||
#
|
||||
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := palmld.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
1
board/palmld/config.mk
Normal file
1
board/palmld/config.mk
Normal file
|
@ -0,0 +1 @@
|
|||
TEXT_BASE = 0xa1000000
|
|
@ -1,9 +1,8 @@
|
|||
/*
|
||||
* Aeronix Zipit Z2 Lowlevel Hardware Initialization
|
||||
* Palm LifeDrive Lowlevel Hardware Initialization
|
||||
*
|
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
|
@ -31,6 +30,12 @@
|
|||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
pxa_gpio_setup
|
||||
|
||||
/* Enable GPIO reset */
|
||||
ldr r0, =PCFR
|
||||
mov r1, #0x30
|
||||
str r1, [r0]
|
||||
|
||||
pxa_wait_ticks 0x8000
|
||||
pxa_mem_setup
|
||||
pxa_wakeup
|
69
board/palmld/palmld.c
Normal file
69
board/palmld/palmld.c
Normal file
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* Palm LifeDrive Support
|
||||
*
|
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <serial.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* arch number of Lubbock-Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = 0xa0000100;
|
||||
|
||||
/* Set PWM for LCD */
|
||||
writel(0x7, PWM_CTRL0);
|
||||
writel(0x16c, PWM_PERVAL0);
|
||||
writel(0x11a, PWM_PWDUTY0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct serial_device *default_serial_console(void)
|
||||
{
|
||||
return &serial_ffuart_device;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
|
||||
{
|
||||
info->portwidth = FLASH_CFI_16BIT;
|
||||
info->chipwidth = FLASH_CFI_BY16;
|
||||
info->interface = FLASH_CFI_X16;
|
||||
return 1;
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* (C) Copyright 2000-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
@ -36,7 +36,7 @@ SECTIONS
|
|||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
@ -44,12 +44,13 @@ SECTIONS
|
|||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
_end = .;
|
||||
}
|
49
board/palmtc/Makefile
Normal file
49
board/palmtc/Makefile
Normal file
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# Palm Tungsten|C Support
|
||||
#
|
||||
# Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := palmtc.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
1
board/palmtc/config.mk
Normal file
1
board/palmtc/config.mk
Normal file
|
@ -0,0 +1 @@
|
|||
TEXT_BASE = 0xa1000000
|
|
@ -1,9 +1,8 @@
|
|||
/*
|
||||
* Voipac PXA270 Lowlevel Hardware Initialization
|
||||
* Palm Tungsten|C Lowlevel Hardware Initialization
|
||||
*
|
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
|
@ -1,4 +1,7 @@
|
|||
/*
|
||||
* Palm Tungsten|C Support
|
||||
*
|
||||
* Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
|
@ -14,25 +17,43 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <dataflash.h>
|
||||
#include <command.h>
|
||||
#include <serial.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
|
||||
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
|
||||
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
|
||||
};
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
/*define the area offsets*/
|
||||
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
|
||||
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
|
||||
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
|
||||
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
|
||||
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
|
||||
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
|
||||
};
|
||||
int board_init(void)
|
||||
{
|
||||
/* Arch number of Palm Tungsten|C */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
|
||||
|
||||
/* Adress of boot parameters */
|
||||
gd->bd->bi_boot_params = 0xa0000100;
|
||||
|
||||
/* Set PWM for LCD */
|
||||
writel(0x5f, PWM_CTRL1);
|
||||
writel(0x3ff, PWM_PERVAL1);
|
||||
writel(892, PWM_PWDUTY1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct serial_device *default_serial_console(void)
|
||||
{
|
||||
return &serial_ffuart_device;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
return 0;
|
||||
}
|
|
@ -1,7 +1,6 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
* (C) Copyright 2000-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -22,29 +21,36 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/AT91RM9200.h>
|
||||
#include <at91rm9200_net.h>
|
||||
#include <dm9161.h>
|
||||
#include <net.h>
|
||||
|
||||
int board_late_init(void)
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
. = 0x00000000;
|
||||
|
||||
/* Fix Ethernet Initialization Bug when starting Linux from U-Boot */
|
||||
eth_init(gd->bd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* checks if addr is in RAM */
|
||||
int addr2ram(ulong addr)
|
||||
{
|
||||
int result = 0;
|
||||
|
||||
if((addr >= PHYS_SDRAM) && (addr < (PHYS_SDRAM + PHYS_SDRAM_SIZE)))
|
||||
result = 1;
|
||||
|
||||
return result;
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/pxa/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
_end = .;
|
||||
}
|
|
@ -33,6 +33,7 @@
|
|||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include <command.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -56,14 +57,14 @@ int board_init (void)
|
|||
|
||||
/* set PWM for LCD */
|
||||
/* a value that works is 60Hz, 77% duty cycle */
|
||||
CKEN |= CKEN0_PWM0;
|
||||
PWM_CTRL0 = 0x3f;
|
||||
PWM_PERVAL0 = 0x3ff;
|
||||
PWM_PWDUTY0 = 792;
|
||||
writel(readl(CKEN) | CKEN0_PWM0, CKEN);
|
||||
writel(0x3f, PWM_CTRL0);
|
||||
writel(0x3ff, PWM_PERVAL0);
|
||||
writel(792, PWM_PWDUTY0);
|
||||
|
||||
/* clear reset to AC97 codec */
|
||||
CKEN |= CKEN2_AC97;
|
||||
GCR = GCR_COLD_RST;
|
||||
writel(readl(CKEN) | CKEN2_AC97, CKEN);
|
||||
writel(GCR_COLD_RST, GCR);
|
||||
|
||||
/* enable LCD backlight */
|
||||
/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
|
||||
|
@ -102,11 +103,11 @@ int dram_init (void)
|
|||
void delay_c(void)
|
||||
{
|
||||
/* reset OSCR to 0 */
|
||||
OSCR = 0;
|
||||
while(OSCR > 0x10000)
|
||||
writel(0, OSCR);
|
||||
while (readl(OSCR) > 0x10000)
|
||||
;
|
||||
|
||||
while(OSCR < 0xd4000)
|
||||
while (readl(OSCR) < 0xd4000)
|
||||
;
|
||||
}
|
||||
|
||||
|
@ -114,12 +115,12 @@ void blink_c(void)
|
|||
{
|
||||
int led_bit = (1<<10);
|
||||
|
||||
GPDR0 = led_bit;
|
||||
GPCR0 = led_bit;
|
||||
writel(led_bit, GPDR0);
|
||||
writel(led_bit, GPCR0);
|
||||
delay_c();
|
||||
GPSR0 = led_bit;
|
||||
writel(led_bit, GPSR0);
|
||||
delay_c();
|
||||
GPCR0 = led_bit;
|
||||
writel(led_bit, GPCR0);
|
||||
}
|
||||
|
||||
int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
|
|
|
@ -34,6 +34,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -44,7 +45,7 @@ extern struct serial_device serial_ffuart_device;
|
|||
extern struct serial_device serial_btuart_device;
|
||||
extern struct serial_device serial_stuart_device;
|
||||
|
||||
#if CONFIG_POLARIS
|
||||
#if CONFIG_MK_POLARIS
|
||||
#define BOOT_CONSOLE "serial_stuart"
|
||||
#else
|
||||
#define BOOT_CONSOLE "serial_ffuart"
|
||||
|
@ -57,25 +58,27 @@ extern struct serial_device serial_stuart_device;
|
|||
|
||||
int usb_board_init(void)
|
||||
{
|
||||
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
|
||||
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
|
||||
writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
|
||||
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
|
||||
UHCHR);
|
||||
|
||||
UHCHR |= UHCHR_FSBIR;
|
||||
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
|
||||
|
||||
while (UHCHR & UHCHR_FSBIR);
|
||||
while (readl(UHCHR) & UHCHR_FSBIR)
|
||||
;
|
||||
|
||||
UHCHR &= ~UHCHR_SSE;
|
||||
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
|
||||
writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
|
||||
writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
|
||||
|
||||
/* Clear any OTG Pin Hold */
|
||||
if (PSSR & PSSR_OTGPH)
|
||||
PSSR |= PSSR_OTGPH;
|
||||
if (readl(PSSR) & PSSR_OTGPH)
|
||||
writel(readl(PSSR) | PSSR_OTGPH, PSSR);
|
||||
|
||||
UHCRHDA &= ~(RH_A_NPS);
|
||||
UHCRHDA |= RH_A_PSM;
|
||||
writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
|
||||
writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
|
||||
|
||||
/* Set port power control mask bits, only 3 ports. */
|
||||
UHCRHDB |= (0x7<<17);
|
||||
writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -87,14 +90,14 @@ void usb_board_init_fail(void)
|
|||
|
||||
void usb_board_stop(void)
|
||||
{
|
||||
UHCHR |= UHCHR_FHR;
|
||||
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
|
||||
udelay(11);
|
||||
UHCHR &= ~UHCHR_FHR;
|
||||
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
|
||||
|
||||
UHCCOMS |= 1;
|
||||
writel(readl(UHCCOMS) | 1, UHCCOMS);
|
||||
udelay(10);
|
||||
|
||||
CKEN &= ~CKEN10_USBHOST;
|
||||
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -26,7 +26,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx51_pins.h>
|
||||
#include <asm/arch/mx5x_pins.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <mxc_gpio.h>
|
||||
|
|
|
@ -1,10 +1,7 @@
|
|||
|
||||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# Voipac PXA270 Support
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
|
@ -27,17 +24,15 @@ include $(TOPDIR)/config.mk
|
|||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := vpac270.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
|
|
@ -1 +0,0 @@
|
|||
CONFIG_SYS_TEXT_BASE = 0xa1000000
|
|
@ -1,16 +1,7 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
|
||||
* Voipac PXA270 Support
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
|
@ -31,29 +22,24 @@
|
|||
#include <common.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <netdev.h>
|
||||
#include <serial.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
extern struct serial_device serial_ffuart_device;
|
||||
extern struct serial_device serial_btuart_device;
|
||||
extern struct serial_device serial_stuart_device;
|
||||
|
||||
struct serial_device *default_serial_console (void)
|
||||
int board_init(void)
|
||||
{
|
||||
return &serial_ffuart_device;
|
||||
}
|
||||
/* We have RAM, disable cache */
|
||||
dcache_disable();
|
||||
icache_disable();
|
||||
|
||||
int board_init (void)
|
||||
{
|
||||
/* memory and cpu-speed are setup before relocation */
|
||||
/* so we do _nothing_ here */
|
||||
|
||||
/* arch number of vpac270 */
|
||||
/* Arch number of vpac270 */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
|
||||
|
||||
/* adress of boot parameters */
|
||||
|
@ -62,41 +48,58 @@ int board_init (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int dram_init (void)
|
||||
struct serial_device *default_serial_console(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
|
||||
return &serial_ffuart_device;
|
||||
}
|
||||
|
||||
extern void pxa_dram_init(void);
|
||||
int dram_init(void)
|
||||
{
|
||||
pxa_dram_init();
|
||||
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
#ifdef CONFIG_RAM_256M
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
int usb_board_init(void)
|
||||
{
|
||||
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
|
||||
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
|
||||
writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
|
||||
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
|
||||
UHCHR);
|
||||
|
||||
UHCHR |= UHCHR_FSBIR;
|
||||
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
|
||||
|
||||
while (UHCHR & UHCHR_FSBIR);
|
||||
while (readl(UHCHR) & UHCHR_FSBIR)
|
||||
;
|
||||
|
||||
UHCHR &= ~UHCHR_SSE;
|
||||
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
|
||||
writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
|
||||
writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
|
||||
|
||||
/* Clear any OTG Pin Hold */
|
||||
if (PSSR & PSSR_OTGPH)
|
||||
PSSR |= PSSR_OTGPH;
|
||||
if (readl(PSSR) & PSSR_OTGPH)
|
||||
writel(readl(PSSR) | PSSR_OTGPH, PSSR);
|
||||
|
||||
UHCRHDA &= ~(0x200);
|
||||
UHCRHDA |= 0x100;
|
||||
writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
|
||||
writel(readl(UHCRHDA) | 0x100, UHCRHDA);
|
||||
|
||||
/* Set port power control mask bits, only 3 ports. */
|
||||
UHCRHDB |= (0x7<<17);
|
||||
writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
|
||||
|
||||
/* enable port 2 */
|
||||
UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
|
||||
writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
|
||||
UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -108,17 +111,18 @@ void usb_board_init_fail(void)
|
|||
|
||||
void usb_board_stop(void)
|
||||
{
|
||||
UHCHR |= UHCHR_FHR;
|
||||
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
|
||||
udelay(11);
|
||||
UHCHR &= ~UHCHR_FHR;
|
||||
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
|
||||
|
||||
UHCCOMS |= 1;
|
||||
writel(readl(UHCCOMS) | 1, UHCCOMS);
|
||||
udelay(10);
|
||||
|
||||
CKEN &= ~CKEN10_USBHOST;
|
||||
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DRIVER_DM9000
|
||||
int board_eth_init(bd_t *bis)
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -33,13 +34,13 @@ int board_init (void)
|
|||
* Setup GPIO stuff to get serial working
|
||||
*/
|
||||
#if defined( CONFIG_FFUART )
|
||||
GPDR1 = 0x80;
|
||||
GAFR1_L = 0x8010;
|
||||
writel(0x80, GPDR1);
|
||||
writel(0x8010, GAFR1_L);
|
||||
#elif defined( CONFIG_BTUART )
|
||||
GPDR1 = 0x800;
|
||||
GAFR1_L = 0x900000;
|
||||
writel(0x800, GPDR1);
|
||||
writel(0x900000, GAFR1_L);
|
||||
#endif
|
||||
PSSR = 0x20;
|
||||
writel(0x20, PSSR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -29,17 +29,15 @@ include $(TOPDIR)/config.mk
|
|||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := zipitz2.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
|
|
@ -1 +0,0 @@
|
|||
CONFIG_SYS_TEXT_BASE = 0xa1000000
|
|
@ -28,6 +28,7 @@
|
|||
#include <serial.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <spi.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -43,10 +44,11 @@ inline void lcd_start(void) {};
|
|||
|
||||
int board_init (void)
|
||||
{
|
||||
/* memory and cpu-speed are setup before relocation */
|
||||
/* so we do _nothing_ here */
|
||||
/* We have RAM, disable cache */
|
||||
dcache_disable();
|
||||
icache_disable();
|
||||
|
||||
/* arch number of Lubbock-Board */
|
||||
/* arch number of Z2 */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
|
||||
|
||||
/* adress of boot parameters */
|
||||
|
@ -58,24 +60,23 @@ int board_init (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
setenv("stdout", "serial");
|
||||
setenv("stderr", "serial");
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct serial_device *default_serial_console (void)
|
||||
{
|
||||
return &serial_stuart_device;
|
||||
}
|
||||
|
||||
int dram_init (void)
|
||||
extern void pxa_dram_init(void);
|
||||
int dram_init(void)
|
||||
{
|
||||
pxa_dram_init();
|
||||
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_SPI
|
||||
|
@ -129,24 +130,24 @@ void zipitz2_spi_sda(int set)
|
|||
{
|
||||
/* GPIO 13 */
|
||||
if (set)
|
||||
GPSR0 = (1 << 13);
|
||||
writel((1 << 13), GPSR0);
|
||||
else
|
||||
GPCR0 = (1 << 13);
|
||||
writel((1 << 13), GPCR0);
|
||||
}
|
||||
|
||||
void zipitz2_spi_scl(int set)
|
||||
{
|
||||
/* GPIO 22 */
|
||||
if (set)
|
||||
GPCR0 = (1 << 22);
|
||||
writel((1 << 22), GPCR0);
|
||||
else
|
||||
GPSR0 = (1 << 22);
|
||||
writel((1 << 22), GPSR0);
|
||||
}
|
||||
|
||||
unsigned char zipitz2_spi_read(void)
|
||||
{
|
||||
/* GPIO 40 */
|
||||
return !!(GPLR1 & (1 << 8));
|
||||
return !!(readl(GPLR1) & (1 << 8));
|
||||
}
|
||||
|
||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
||||
|
@ -158,13 +159,13 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
|||
void spi_cs_activate(struct spi_slave *slave)
|
||||
{
|
||||
/* GPIO 88 low */
|
||||
GPCR2 = (1 << 24);
|
||||
writel((1 << 24), GPCR2);
|
||||
}
|
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave)
|
||||
{
|
||||
/* GPIO 88 high */
|
||||
GPSR2 = (1 << 24);
|
||||
writel((1 << 24), GPSR2);
|
||||
|
||||
}
|
||||
|
||||
|
@ -176,20 +177,20 @@ void lcd_start(void)
|
|||
unsigned char dummy[3] = { 0, 0, 0 };
|
||||
|
||||
/* PWM2 AF */
|
||||
GAFR0_L |= 0x00800000;
|
||||
writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
|
||||
/* Enable clock to all PWM */
|
||||
CKEN |= 0x3;
|
||||
writel(readl(CKEN) | 0x3, CKEN);
|
||||
/* Configure PWM2 */
|
||||
PWM_CTRL2 = 0x4f;
|
||||
PWM_PWDUTY2 = 0x2ff;
|
||||
PWM_PERVAL2 = 792;
|
||||
writel(0x4f, PWM_CTRL2);
|
||||
writel(0x2ff, PWM_PWDUTY2);
|
||||
writel(792, PWM_PERVAL2);
|
||||
|
||||
/* Toggle the reset pin to reset the LCD */
|
||||
GPSR0 = (1 << 19);
|
||||
writel((1 << 19), GPSR0);
|
||||
udelay(100000);
|
||||
GPCR0 = (1 << 19);
|
||||
writel((1 << 19), GPCR0);
|
||||
udelay(20000);
|
||||
GPSR0 = (1 << 19);
|
||||
writel((1 << 19), GPSR0);
|
||||
udelay(20000);
|
||||
|
||||
/* Program the LCD init sequence */
|
||||
|
@ -208,6 +209,6 @@ void lcd_start(void)
|
|||
udelay(lcd_data[i].mdelay * 1000);
|
||||
}
|
||||
|
||||
GPSR0 = (1 << 11);
|
||||
writel((1 << 11), GPSR0);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
|
||||
|
@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
|||
if(bytes_multi) {
|
||||
for(i=0; i<bytes_multi; i+=4) {
|
||||
long_buf = (unsigned long*) &buf[i];
|
||||
NDDB = *long_buf;
|
||||
writel(*long_buf, NDDB);
|
||||
}
|
||||
}
|
||||
if(rest) {
|
||||
|
@ -125,7 +126,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
|
|||
if(bytes_multi) {
|
||||
for(i=0; i<bytes_multi; i+=4) {
|
||||
long_buf = (unsigned long*) &buf[i];
|
||||
*long_buf = NDDB;
|
||||
*long_buf = readl(NDDB);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -171,8 +172,8 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
|
|||
unsigned long dummy;
|
||||
|
||||
if(bytes_read < 0) {
|
||||
read_buf = NDDB;
|
||||
dummy = NDDB;
|
||||
read_buf = readl(NDDB);
|
||||
dummy = readl(NDDB);
|
||||
bytes_read = 0;
|
||||
}
|
||||
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
|
||||
|
@ -186,7 +187,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
|
|||
/* calculate delta between OSCR values start and now */
|
||||
static unsigned long get_delta(unsigned long start)
|
||||
{
|
||||
unsigned long cur = OSCR;
|
||||
unsigned long cur = readl(OSCR);
|
||||
|
||||
if(cur < start) /* OSCR overflowed */
|
||||
return (cur + (start^0xffffffff));
|
||||
|
@ -197,7 +198,7 @@ static unsigned long get_delta(unsigned long start)
|
|||
/* delay function, this doesn't belong here */
|
||||
static void wait_us(unsigned long us)
|
||||
{
|
||||
unsigned long start = OSCR;
|
||||
unsigned long start = readl(OSCR);
|
||||
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
|
||||
|
||||
while (get_delta(start) < us) {
|
||||
|
@ -207,14 +208,14 @@ static void wait_us(unsigned long us)
|
|||
|
||||
static void dfc_clear_nddb(void)
|
||||
{
|
||||
NDCR &= ~NDCR_ND_RUN;
|
||||
writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
|
||||
wait_us(CONFIG_SYS_NAND_OTHER_TO);
|
||||
}
|
||||
|
||||
/* wait_event with timeout */
|
||||
static unsigned long dfc_wait_event(unsigned long event)
|
||||
{
|
||||
unsigned long ndsr, timeout, start = OSCR;
|
||||
unsigned long ndsr, timeout, start = readl(OSCR);
|
||||
|
||||
if(!event)
|
||||
return 0xff000000;
|
||||
|
@ -226,9 +227,9 @@ static unsigned long dfc_wait_event(unsigned long event)
|
|||
* OSCR_CLK_FREQ, 1000);
|
||||
|
||||
while(1) {
|
||||
ndsr = NDSR;
|
||||
ndsr = readl(NDSR);
|
||||
if(ndsr & event) {
|
||||
NDSR |= event;
|
||||
writel(readl(NDSR) | event, NDSR);
|
||||
break;
|
||||
}
|
||||
if(get_delta(start) > timeout) {
|
||||
|
@ -248,11 +249,11 @@ static void dfc_new_cmd(void)
|
|||
|
||||
while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
|
||||
/* Clear NDSR */
|
||||
NDSR = 0xFFF;
|
||||
writel(0xFFF, NDSR);
|
||||
|
||||
/* set NDCR[NDRUN] */
|
||||
if(!(NDCR & NDCR_ND_RUN))
|
||||
NDCR |= NDCR_ND_RUN;
|
||||
if (!(readl(NDCR) & NDCR_ND_RUN))
|
||||
writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
|
||||
|
||||
status = dfc_wait_event(NDSR_WRCMDREQ);
|
||||
|
||||
|
@ -362,9 +363,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
|
|||
}
|
||||
|
||||
write_cmd:
|
||||
NDCB0 = ndcb0;
|
||||
NDCB0 = ndcb1;
|
||||
NDCB0 = ndcb2;
|
||||
writel(ndcb0, NDCB0);
|
||||
writel(ndcb1, NDCB0);
|
||||
writel(ndcb2, NDCB0);
|
||||
|
||||
/* wait_event: */
|
||||
dfc_wait_event(event);
|
||||
|
@ -377,36 +378,36 @@ static void dfc_gpio_init(void)
|
|||
DFC_DEBUG2("Setting up DFC GPIO's.\n");
|
||||
|
||||
/* no idea what is done here, see zylonite.c */
|
||||
GPIO4 = 0x1;
|
||||
writel(0x1, GPIO4);
|
||||
|
||||
DF_ALE_WE1 = 0x00000001;
|
||||
DF_ALE_WE2 = 0x00000001;
|
||||
DF_nCS0 = 0x00000001;
|
||||
DF_nCS1 = 0x00000001;
|
||||
DF_nWE = 0x00000001;
|
||||
DF_nRE = 0x00000001;
|
||||
DF_IO0 = 0x00000001;
|
||||
DF_IO8 = 0x00000001;
|
||||
DF_IO1 = 0x00000001;
|
||||
DF_IO9 = 0x00000001;
|
||||
DF_IO2 = 0x00000001;
|
||||
DF_IO10 = 0x00000001;
|
||||
DF_IO3 = 0x00000001;
|
||||
DF_IO11 = 0x00000001;
|
||||
DF_IO4 = 0x00000001;
|
||||
DF_IO12 = 0x00000001;
|
||||
DF_IO5 = 0x00000001;
|
||||
DF_IO13 = 0x00000001;
|
||||
DF_IO6 = 0x00000001;
|
||||
DF_IO14 = 0x00000001;
|
||||
DF_IO7 = 0x00000001;
|
||||
DF_IO15 = 0x00000001;
|
||||
writel(0x00000001, DF_ALE_nWE1);
|
||||
writel(0x00000001, DF_ALE_nWE2);
|
||||
writel(0x00000001, DF_nCS0);
|
||||
writel(0x00000001, DF_nCS1);
|
||||
writel(0x00000001, DF_nWE);
|
||||
writel(0x00000001, DF_nRE);
|
||||
writel(0x00000001, DF_IO0);
|
||||
writel(0x00000001, DF_IO8);
|
||||
writel(0x00000001, DF_IO1);
|
||||
writel(0x00000001, DF_IO9);
|
||||
writel(0x00000001, DF_IO2);
|
||||
writel(0x00000001, DF_IO10);
|
||||
writel(0x00000001, DF_IO3);
|
||||
writel(0x00000001, DF_IO11);
|
||||
writel(0x00000001, DF_IO4);
|
||||
writel(0x00000001, DF_IO12);
|
||||
writel(0x00000001, DF_IO5);
|
||||
writel(0x00000001, DF_IO13);
|
||||
writel(0x00000001, DF_IO6);
|
||||
writel(0x00000001, DF_IO14);
|
||||
writel(0x00000001, DF_IO7);
|
||||
writel(0x00000001, DF_IO15);
|
||||
|
||||
DF_nWE = 0x1901;
|
||||
DF_nRE = 0x1901;
|
||||
DF_CLE_NOE = 0x1900;
|
||||
DF_ALE_WE1 = 0x1901;
|
||||
DF_INT_RnB = 0x1900;
|
||||
writel(0x1901, DF_nWE);
|
||||
writel(0x1901, DF_nRE);
|
||||
writel(0x1900, DF_CLE_nOE);
|
||||
writel(0x1901, DF_ALE_nWE1);
|
||||
writel(0x1900, DF_INT_RnB);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -435,7 +436,7 @@ int board_nand_init(struct nand_chip *nand)
|
|||
dfc_gpio_init();
|
||||
|
||||
/* turn on the NAND Controller Clock (104 MHz @ D0) */
|
||||
CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
|
||||
writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
|
||||
|
||||
#undef CONFIG_SYS_TIMING_TIGHT
|
||||
#ifndef CONFIG_SYS_TIMING_TIGHT
|
||||
|
@ -490,17 +491,19 @@ int board_nand_init(struct nand_chip *nand)
|
|||
tRP_high = 0;
|
||||
}
|
||||
|
||||
NDTR0CS0 = (tCH << 19) |
|
||||
writel((tCH << 19) |
|
||||
(tCS << 16) |
|
||||
(tWH << 11) |
|
||||
(tWP << 8) |
|
||||
(tRP_high << 6) |
|
||||
(tRH << 3) |
|
||||
(tRP << 0);
|
||||
(tRP << 0),
|
||||
NDTR0CS0);
|
||||
|
||||
NDTR1CS0 = (tR << 16) |
|
||||
writel((tR << 16) |
|
||||
(tWHR << 4) |
|
||||
(tAR << 0);
|
||||
(tAR << 0),
|
||||
NDTR1CS0);
|
||||
|
||||
/* If it doesn't work (unlikely) think about:
|
||||
* - ecc enable
|
||||
|
@ -517,7 +520,7 @@ int board_nand_init(struct nand_chip *nand)
|
|||
*/
|
||||
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
|
||||
|
||||
NDCR = (NDCR_SPARE_EN | /* use the spare area */
|
||||
writel(NDCR_SPARE_EN | /* use the spare area */
|
||||
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
|
||||
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
|
||||
(2 << 16) | /* read id count = 7 ???? mk@tbd */
|
||||
|
@ -533,7 +536,8 @@ int board_nand_init(struct nand_chip *nand)
|
|||
NDCR_SBERRM | /* single bit error ir masked */
|
||||
NDCR_WRDREQM | /* write data request ir masked */
|
||||
NDCR_RDDREQM | /* read data request ir masked */
|
||||
NDCR_WRCMDREQM); /* write command request ir masked */
|
||||
NDCR_WRCMDREQM, /* write command request ir masked */
|
||||
NDCR);
|
||||
|
||||
|
||||
/* wait 10 us due to cmd buffer clear reset */
|
||||
|
|
14
boards.cfg
14
boards.cfg
|
@ -54,20 +54,28 @@ pm9263 arm arm926ejs - ronetix at91
|
|||
suen3 arm arm926ejs km_arm keymile kirkwood
|
||||
rd6281a arm arm926ejs - Marvell kirkwood
|
||||
jadecpu arm arm926ejs jadecpu syteco mb86r0x
|
||||
mx51evk arm armv7 mx51evk freescale mx51
|
||||
vision2 arm armv7 vision2 ttcontrol mx51
|
||||
mx51evk arm armv7 mx51evk freescale mx5
|
||||
vision2 arm armv7 vision2 ttcontrol mx5
|
||||
actux1 arm ixp
|
||||
actux2 arm ixp
|
||||
actux3 arm ixp
|
||||
actux4 arm ixp
|
||||
ixdp425 arm ixp
|
||||
balloon3 arm pxa
|
||||
cerf250 arm pxa
|
||||
cradle arm pxa
|
||||
csb226 arm pxa
|
||||
delta arm pxa
|
||||
innokom arm pxa
|
||||
lubbock arm pxa
|
||||
palmld arm pxa
|
||||
palmtc arm pxa
|
||||
pleb2 arm pxa
|
||||
polaris arm pxa trizepsiv - - trizepsiv:POLARIS
|
||||
trizepsiv arm pxa
|
||||
vpac270_nor_128 arm pxa vpac270 - - vpac270:NOR,RAM_128M
|
||||
vpac270_nor_256 arm pxa vpac270 - - vpac270:NOR,RAM_256M
|
||||
vpac270_ond_256 arm pxa vpac270 - - vpac270:ONENAND,RAM_256M
|
||||
xaeniax arm pxa
|
||||
xm250 arm pxa
|
||||
zipitz2 arm pxa
|
||||
|
@ -352,7 +360,7 @@ modnet50 arm arm720t
|
|||
lpc2292sodimm arm arm720t - - lpc2292
|
||||
eb_cpux9k2 arm arm920t - BuS at91
|
||||
at91rm9200dk arm arm920t - atmel at91rm9200
|
||||
at91rm9200ek arm arm920t - atmel at91rm9200
|
||||
at91rm9200ek arm arm920t - atmel at91
|
||||
sbc2410x arm arm920t - - s3c24x0
|
||||
smdk2400 arm arm920t - samsung s3c24x0
|
||||
smdk2410 arm arm920t - samsung s3c24x0
|
||||
|
|
|
@ -308,7 +308,6 @@ static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
|
|||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC)
|
||||
/* find flattened device tree */
|
||||
ret = boot_get_fdt (flag, argc, argv, &images,
|
||||
&images.ft_addr, &images.ft_len);
|
||||
|
@ -318,7 +317,6 @@ static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
|
|||
}
|
||||
|
||||
set_working_fdt_addr(images.ft_addr);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -474,7 +472,7 @@ static int bootm_start_standalone(ulong iflag, int argc, char * const argv[])
|
|||
static cmd_tbl_t cmd_bootm_sub[] = {
|
||||
U_BOOT_CMD_MKENT(start, 0, 1, (void *)BOOTM_STATE_START, "", ""),
|
||||
U_BOOT_CMD_MKENT(loados, 0, 1, (void *)BOOTM_STATE_LOADOS, "", ""),
|
||||
#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC)
|
||||
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
|
||||
U_BOOT_CMD_MKENT(ramdisk, 0, 1, (void *)BOOTM_STATE_RAMDISK, "", ""),
|
||||
#endif
|
||||
#ifdef CONFIG_OF_LIBFDT
|
||||
|
@ -530,7 +528,7 @@ int do_bootm_subcommand (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv
|
|||
lmb_reserve(&images.lmb, images.os.load,
|
||||
(load_end - images.os.load));
|
||||
break;
|
||||
#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC)
|
||||
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
|
||||
case BOOTM_STATE_RAMDISK:
|
||||
{
|
||||
ulong rd_len = images.rd_end - images.rd_start;
|
||||
|
|
|
@ -362,10 +362,40 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
|
|||
do_fixup_by_compat(fdt, compat, prop, &val, 4, create);
|
||||
}
|
||||
|
||||
int fdt_fixup_memory(void *blob, u64 start, u64 size)
|
||||
/*
|
||||
* Get cells len in bytes
|
||||
* if #NNNN-cells property is 2 then len is 8
|
||||
* otherwise len is 4
|
||||
*/
|
||||
static int get_cells_len(void *blob, char *nr_cells_name)
|
||||
{
|
||||
int err, nodeoffset, len = 0;
|
||||
u8 tmp[16];
|
||||
const u32 *cell;
|
||||
|
||||
cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
|
||||
if (cell && *cell == 2)
|
||||
return 8;
|
||||
|
||||
return 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write a 4 or 8 byte big endian cell
|
||||
*/
|
||||
static void write_cell(u8 *addr, u64 val, int size)
|
||||
{
|
||||
int shift = (size - 1) * 8;
|
||||
while (size-- > 0) {
|
||||
*addr++ = (val >> shift) & 0xff;
|
||||
shift -= 8;
|
||||
}
|
||||
}
|
||||
|
||||
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
|
||||
{
|
||||
int err, nodeoffset;
|
||||
int addr_cell_len, size_cell_len, len;
|
||||
u8 tmp[banks * 8];
|
||||
int bank;
|
||||
const u32 *addrcell, *sizecell;
|
||||
|
||||
err = fdt_check_header(blob);
|
||||
|
@ -391,44 +421,15 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size)
|
|||
return err;
|
||||
}
|
||||
|
||||
addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
|
||||
/* use shifts and mask to ensure endianness */
|
||||
if ((addrcell) && (*addrcell == 2)) {
|
||||
tmp[0] = (start >> 56) & 0xff;
|
||||
tmp[1] = (start >> 48) & 0xff;
|
||||
tmp[2] = (start >> 40) & 0xff;
|
||||
tmp[3] = (start >> 32) & 0xff;
|
||||
tmp[4] = (start >> 24) & 0xff;
|
||||
tmp[5] = (start >> 16) & 0xff;
|
||||
tmp[6] = (start >> 8) & 0xff;
|
||||
tmp[7] = (start ) & 0xff;
|
||||
len = 8;
|
||||
} else {
|
||||
tmp[0] = (start >> 24) & 0xff;
|
||||
tmp[1] = (start >> 16) & 0xff;
|
||||
tmp[2] = (start >> 8) & 0xff;
|
||||
tmp[3] = (start ) & 0xff;
|
||||
len = 4;
|
||||
}
|
||||
addr_cell_len = get_cells_len(blob, "#address-cells");
|
||||
size_cell_len = get_cells_len(blob, "#size-cells");
|
||||
|
||||
sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);
|
||||
/* use shifts and mask to ensure endianness */
|
||||
if ((sizecell) && (*sizecell == 2)) {
|
||||
tmp[0+len] = (size >> 56) & 0xff;
|
||||
tmp[1+len] = (size >> 48) & 0xff;
|
||||
tmp[2+len] = (size >> 40) & 0xff;
|
||||
tmp[3+len] = (size >> 32) & 0xff;
|
||||
tmp[4+len] = (size >> 24) & 0xff;
|
||||
tmp[5+len] = (size >> 16) & 0xff;
|
||||
tmp[6+len] = (size >> 8) & 0xff;
|
||||
tmp[7+len] = (size ) & 0xff;
|
||||
len += 8;
|
||||
} else {
|
||||
tmp[0+len] = (size >> 24) & 0xff;
|
||||
tmp[1+len] = (size >> 16) & 0xff;
|
||||
tmp[2+len] = (size >> 8) & 0xff;
|
||||
tmp[3+len] = (size ) & 0xff;
|
||||
len += 4;
|
||||
for (bank = 0, len = 0; bank < banks; bank++) {
|
||||
write_cell(tmp + len, start[bank], addr_cell_len);
|
||||
len += addr_cell_len;
|
||||
|
||||
write_cell(tmp + len, size[bank], size_cell_len);
|
||||
len += size_cell_len;
|
||||
}
|
||||
|
||||
err = fdt_setprop(blob, nodeoffset, "reg", tmp, len);
|
||||
|
@ -440,6 +441,11 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int fdt_fixup_memory(void *blob, u64 start, u64 size)
|
||||
{
|
||||
return fdt_fixup_memory_banks(blob, &start, &size, 1);
|
||||
}
|
||||
|
||||
void fdt_fixup_ethernet(void *fdt)
|
||||
{
|
||||
int node, i, j;
|
||||
|
|
|
@ -992,7 +992,7 @@ int boot_get_ramdisk (int argc, char * const argv[], bootm_headers_t *images,
|
|||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC)
|
||||
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
|
||||
/**
|
||||
* boot_ramdisk_high - relocate init ramdisk
|
||||
* @lmb: pointer to lmb handle, will be used for memory mgmt
|
||||
|
@ -1081,7 +1081,7 @@ int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len,
|
|||
error:
|
||||
return -1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC) */
|
||||
#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
|
||||
|
||||
#ifdef CONFIG_OF_LIBFDT
|
||||
static void fdt_error (const char *msg)
|
||||
|
@ -1252,7 +1252,7 @@ int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base,
|
|||
*of_size = of_len;
|
||||
} else {
|
||||
*of_flat_tree = fdt_blob;
|
||||
of_len = (CONFIG_SYS_BOOTMAPSZ + bootmap_base) - (ulong)fdt_blob;
|
||||
of_len = *of_size + CONFIG_SYS_FDT_PAD;
|
||||
lmb_reserve(lmb, (ulong)fdt_blob, of_len);
|
||||
fdt_set_totalsize(*of_flat_tree, of_len);
|
||||
|
||||
|
@ -1561,7 +1561,7 @@ int boot_get_fdt (int flag, int argc, char * const argv[], bootm_headers_t *imag
|
|||
goto error;
|
||||
}
|
||||
|
||||
if (be32_to_cpu (fdt_totalsize (fdt_blob)) != fdt_len) {
|
||||
if (fdt_totalsize(fdt_blob) != fdt_len) {
|
||||
fdt_error ("fdt size != image size");
|
||||
goto error;
|
||||
}
|
||||
|
@ -1575,7 +1575,7 @@ int boot_get_fdt (int flag, int argc, char * const argv[], bootm_headers_t *imag
|
|||
}
|
||||
|
||||
*of_flat_tree = fdt_blob;
|
||||
*of_size = be32_to_cpu (fdt_totalsize (fdt_blob));
|
||||
*of_size = fdt_totalsize(fdt_blob);
|
||||
debug (" of_flat_tree at 0x%08lx size 0x%08lx\n",
|
||||
(ulong)*of_flat_tree, *of_size);
|
||||
|
||||
|
@ -1588,7 +1588,7 @@ error:
|
|||
}
|
||||
#endif /* CONFIG_OF_LIBFDT */
|
||||
|
||||
#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
|
||||
#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
|
||||
/**
|
||||
* boot_get_cmdline - allocate and initialize kernel cmdline
|
||||
* @lmb: pointer to lmb handle, will be used for memory mgmt
|
||||
|
@ -1630,7 +1630,9 @@ int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start, ulong *cmd_end,
|
|||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_GET_KBD
|
||||
/**
|
||||
* boot_get_kbd - allocate and initialize kernel copy of board info
|
||||
* @lmb: pointer to lmb handle, will be used for memory mgmt
|
||||
|
@ -1663,7 +1665,7 @@ int boot_get_kbd (struct lmb *lmb, bd_t **kbd, ulong bootmap_base)
|
|||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PPC || CONFIG_M68K */
|
||||
#endif /* CONFIG_SYS_BOOT_GET_KBD */
|
||||
#endif /* !USE_HOSTCC */
|
||||
|
||||
#if defined(CONFIG_FIT)
|
||||
|
|
|
@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
static struct serial_device *serial_devices = NULL;
|
||||
static struct serial_device *serial_current = NULL;
|
||||
|
||||
#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X)
|
||||
#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA250) && !defined(CONFIG_PXA27X)
|
||||
struct serial_device *__default_serial_console (void)
|
||||
{
|
||||
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
|
||||
|
|
|
@ -1,49 +1,54 @@
|
|||
To make relocation on arm working, the following changes are done:
|
||||
|
||||
Add new compilerflag:
|
||||
At arch level: add linker flag -pie
|
||||
|
||||
-fPIC
|
||||
This causes the linker to generate fixup tables .rel.dyn and .dynsym,
|
||||
which must be applied to the relocated image before transferring
|
||||
control to it.
|
||||
|
||||
-> compiler generates position independent code
|
||||
These fixups are described in the ARM ELF documentation as type 23
|
||||
(program-base-relative) and 2 (symbol-relative)
|
||||
|
||||
changes in board code:
|
||||
At cpu level: modify linker file and add a relocation and fixup loop
|
||||
|
||||
- dram_init:
|
||||
- bd pointer is now at this point not accessible, so only
|
||||
detect the real dramsize, and store it in gd->ram_size.
|
||||
best detected with get_ram_size();
|
||||
ToDo: move there also the dram initialization on boards where
|
||||
it is possible.
|
||||
- setup the bd_t dram bank info in the new function
|
||||
dram_init_banksize().
|
||||
the linker file must be modified to include the .rel.dyn and .dynsym
|
||||
tables in the binary image, and to provide symbols for the relocation
|
||||
code to access these tables
|
||||
|
||||
- board.c code is adapted from ppc code
|
||||
The relocation and fixup loop must be executed after executing
|
||||
board_init_f at initial location and before executing board_init_r
|
||||
at final location.
|
||||
|
||||
- undef CONFIG_RELOC_FIXUP_WORKS
|
||||
At board level:
|
||||
|
||||
-> cmdtabl, and subcommand table must be handled from "hand"
|
||||
collected in section "__datarellocal_start".
|
||||
dram_init(): bd pointer is now at this point not accessible, so only
|
||||
detect the real dramsize, and store it in gd->ram_size. Bst detected
|
||||
with get_ram_size().
|
||||
|
||||
- How To fixup the sections:
|
||||
TODO: move also dram initialization there on boards where it is possible.
|
||||
|
||||
__datarel_start, __datarelrolocal_start, __datarellocal_start and
|
||||
__datarelro_start
|
||||
Setup of the the bd_t dram bank info is done in the new function
|
||||
dram_init_banksize() called after bd is accessible.
|
||||
|
||||
automatically? Then it should be possible to define again
|
||||
CONFIG_RELOC_FIXUP_WORKS
|
||||
At lib level:
|
||||
|
||||
- irq stack setup is now not longer on a fix position, instead it is
|
||||
calculated in board_init_f, and stored in gd->irq_sp
|
||||
Board.c code is adapted from ppc code
|
||||
|
||||
-------------------------------------------------------------------------------------
|
||||
At config level:
|
||||
|
||||
To compile a board without relocation, define CONFIG_SYS_ARM_WITHOUT_RELOC
|
||||
This possibility will removed!! So please fix your board to compile without
|
||||
CONFIG_SYS_ARM_WITHOUT_RELOC defined!!!
|
||||
Define CONFIG_RELOC_FIXUP_WORKS.
|
||||
Undefine CONFIG_SYS_ARM_WITHOUT_RELOC
|
||||
|
||||
-------------------------------------------------------------------------------------
|
||||
* WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING *
|
||||
|
||||
For boards which boot from nand_spl, it is possible to save a copy
|
||||
Boards which are not fixed to support relocation will be REMOVED!
|
||||
|
||||
Eventually, CONFIG_SYS_ARM_WITHOUT_RELOC and CONFIG_RELOC_FIXUP_WORKS will
|
||||
disappear and boards which have to migrated to relocation will disappear too.
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
For boards which boot from nand_spl, it is possible to save one copy
|
||||
if CONFIG_SYS_TEXT_BASE == relocation address! This prevents that uboot code
|
||||
is copied again in relocate_code().
|
||||
|
||||
|
@ -64,9 +69,9 @@ f) u-boot code steps through board_init_f() and calculates
|
|||
If CONFIG_SYS_TEXT_BASE == relocation address, the copying of u-boot
|
||||
in f) could be saved.
|
||||
|
||||
-------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
ToDo:
|
||||
TODO
|
||||
|
||||
- fill in bd_t infos (check)
|
||||
- adapt all boards
|
||||
|
@ -80,7 +85,7 @@ ToDo:
|
|||
- new function dram_init_banksize() is actual board specific. Maybe
|
||||
we make a weak default function in arch/arm/lib/board.c ?
|
||||
|
||||
-------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
Relocation with NAND_SPL (example for the tx25):
|
||||
|
||||
|
@ -98,158 +103,11 @@ Relocation with NAND_SPL (example for the tx25):
|
|||
CONFIG_SYS_TEXT_BASE from the nand_spl code), then there is no need
|
||||
to copy, just go on with bss clear and jump to board_init_r.
|
||||
|
||||
-------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
Relocation:
|
||||
How to translate flash addresses in GOT to ram addresses.
|
||||
This is automagically done from code, but this example
|
||||
shows, how this magic code works ;-)
|
||||
(example on the qong board)
|
||||
How ELF relocations 23 and 2 work.
|
||||
|
||||
Find a variable:
|
||||
|
||||
a) search it in System.map
|
||||
(for example flash_info)
|
||||
|
||||
a005b4c0 B BootpID
|
||||
a005b4c4 B BootpTry
|
||||
a005b4c8 b slave
|
||||
a005b4cc B flash_info
|
||||
^^^^^^^^
|
||||
a005c908 b saved_sector.4002
|
||||
a005c910 b cfi_mtd_info
|
||||
a005c9c0 b cfi_mtd_names
|
||||
a005c9d0 B mtd_table
|
||||
|
||||
---------------------------------------
|
||||
|
||||
b) create hexdump from u-boot code:
|
||||
|
||||
hexdump -C u-boot > gnlmpfhex
|
||||
|
||||
---------------------------------------
|
||||
|
||||
c) search the variables address in the hexdump
|
||||
|
||||
|
||||
*
|
||||
0005fc80 00 00 00 00 00 00 00 00 2c 06 01 a0 18 cd 05 a0 |........,.......|
|
||||
0005fc90 9c d4 05 a0 bc b4 05 a0 1c 7f 05 a0 f0 05 01 a0 |................|
|
||||
0005fca0 08 5a 04 a0 1c ab 05 a0 ec a4 05 a0 98 c3 01 a0 |.Z..............|
|
||||
0005fcb0 a0 d6 05 a0 04 71 05 a0 c0 f9 00 a0 3c cd 05 a0 |.....q......<...|
|
||||
0005fcc0 cc b4 05 a0 f0 fa 00 a0 f0 d6 05 a0 10 86 05 a0 |................|
|
||||
^^^^^^^^^^^
|
||||
0005fcd0 a4 16 06 a0 dc 64 05 a0 18 86 05 a0 52 48 05 a0 |.....d......RH..|
|
||||
0005fce0 c0 86 05 a0 24 6e 02 a0 b4 6c 05 a0 b0 94 01 a0 |....$n...l......|
|
||||
0005fcf0 1c 86 05 a0 50 85 05 a0 d4 0c 06 a0 bc 0b 06 a0 |....P...........|
|
||||
|
||||
|
||||
-> 0005fcc0
|
||||
|
||||
----------------------------------------
|
||||
|
||||
d) know we calculate this address in RAM
|
||||
|
||||
|
||||
8ff08000 (new address of code in RAM *1)
|
||||
|
||||
+ 0005fcc0
|
||||
|
||||
- 00008000 (offset of text *2)
|
||||
|
||||
----------
|
||||
|
||||
8ff5fcc0 -> Addr GOT in RAM
|
||||
|
||||
*1:
|
||||
activate debug and look for the line:
|
||||
Now running in RAM - U-Boot at: 8ff08000
|
||||
^^^^^^^^
|
||||
new address of u-boot code in RAM
|
||||
|
||||
*2:
|
||||
Section Headers:
|
||||
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
|
||||
[ 0] NULL 00000000 000000 000000 00 0 0 0
|
||||
[ 1] .text PROGBITS a0000000 008000 04599c 00 AX 0 0 32
|
||||
^^^^^^
|
||||
Offset of text
|
||||
|
||||
----------------------------------------
|
||||
|
||||
e) now we look in 8ff5fcc0 (RAM)
|
||||
|
||||
|
||||
QongEVB>md 0x8ff5fcc0
|
||||
8ff5fcc0 : a005b4cc a000faf0 a005d6f0 a0058610 ................
|
||||
^^^^^^^^
|
||||
Bingo, here we have the old flash address (when relocation
|
||||
is working, here is the fixed ram address. see @ f, how
|
||||
it gets calculated)
|
||||
|
||||
|
||||
----------------------------------------
|
||||
|
||||
f) now translate it in the new RAM address
|
||||
|
||||
a005b4cc
|
||||
|
||||
- a0000000 TextBase
|
||||
|
||||
+ 8ff08000 new address of u-boot in ram
|
||||
----------
|
||||
8ff634cc
|
||||
|
||||
QongEVB>mm 0x8ff5fcc0 0x8ff634cc 1
|
||||
QongEVB>md 0x8ff5fcc0
|
||||
8ff5fcc0 : 8ff634cc a000faf0 a005d6f0 a0058610 .4..............
|
||||
8ff5fcd0 : a00616a4 a00564dc a0058618 a0054852 .....d......RH..
|
||||
|
||||
As this must be done for all address in the GOT, the u-boot
|
||||
code did this automagically ... :-)
|
||||
|
||||
----------------------------------------------
|
||||
|
||||
g) check if the new address is really in the bss section:
|
||||
|
||||
bss start:
|
||||
8ff6054c (8ff08000 + 0005854C monitorlen)
|
||||
|
||||
bss end:
|
||||
8ff698ac (8ff08000 + 618AC)
|
||||
|
||||
8ff634cc is in bss :-)
|
||||
|
||||
----------------------------------------------
|
||||
|
||||
h) u-boot prints:
|
||||
|
||||
important addresses:
|
||||
|
||||
U-Boot code: A0000000 -> A005854C BSS: -> A00618AC TextBase 0xa0000000
|
||||
Now running in RAM - U-Boot at: 8ff08000 relocBase 0x8ff08000
|
||||
|
||||
|
||||
---------
|
||||
|
||||
U-Boot 2010.06-rc2-00002-gf8fbb25-dirty (Jun 18 2010 - 17:07:19)
|
||||
|
||||
U-Boot code: A0000000 -> A005854C BSS: -> A00618AC
|
||||
CPU: Freescale i.MX31 at 398 MHz
|
||||
Board: DAVE/DENX Qong
|
||||
mon: FFFFFFFF gd->monLen: 000618AC
|
||||
Top of RAM usable for U-Boot at: 90000000
|
||||
LCD panel info: 640 x 480, 16 bit/pix
|
||||
Reserving 600k for LCD Framebuffer at: 8ff6a000
|
||||
Reserving 390k for U-Boot at: 8ff08000
|
||||
Reserving 1280k for malloc() at: 8fdc8000
|
||||
Reserving 28 Bytes for Board Info at: 8fdc7fe4
|
||||
Reserving 48 Bytes for Global Data at: 8fdc7fb4
|
||||
New Stack Pointer is: 8fdc7fb0
|
||||
RAM Configuration:
|
||||
Bank #0: 80000000 256 MiB
|
||||
mon: 0005854C gd->monLen: 000618AC
|
||||
Now running in RAM - U-Boot at: 8ff08000
|
||||
TBC
|
||||
|
||||
-------------------------------------------------------------------------------------
|
||||
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
#include <asm/errno.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <part.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include "pxa_mmc.h"
|
||||
|
||||
|
@ -59,18 +60,20 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
|
|||
|
||||
debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl,
|
||||
cmdat | wide);
|
||||
MMC_STRPCL = MMC_STRPCL_STOP_CLK;
|
||||
MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF;
|
||||
while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)) ;
|
||||
MMC_CMD = cmd;
|
||||
MMC_ARGH = argh;
|
||||
MMC_ARGL = argl;
|
||||
MMC_CMDAT = cmdat | wide;
|
||||
MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES;
|
||||
MMC_STRPCL = MMC_STRPCL_START_CLK;
|
||||
while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)) ;
|
||||
writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
|
||||
writel(~MMC_I_MASK_CLK_IS_OFF, MMC_I_MASK);
|
||||
while (!(readl(MMC_I_REG) & MMC_I_REG_CLK_IS_OFF))
|
||||
;
|
||||
writel(cmd, MMC_CMD);
|
||||
writel(argh, MMC_ARGH);
|
||||
writel(argl, MMC_ARGL);
|
||||
writel(cmdat | wide, MMC_CMDAT);
|
||||
writel(~MMC_I_MASK_END_CMD_RES, MMC_I_MASK);
|
||||
writel(MMC_STRPCL_START_CLK, MMC_STRPCL);
|
||||
while (!(readl(MMC_I_REG) & MMC_I_REG_END_CMD_RES))
|
||||
;
|
||||
|
||||
status = MMC_STAT;
|
||||
status = readl(MMC_STAT);
|
||||
debug("MMC status 0x%08x\n", status);
|
||||
if (status & MMC_STAT_TIME_OUT_RESPONSE) {
|
||||
return 0;
|
||||
|
@ -80,10 +83,10 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
|
|||
* Did I mention this is Sick. We always need to
|
||||
* discard the upper 8 bits of the first 16-bit word.
|
||||
*/
|
||||
a = (MMC_RES & 0xffff);
|
||||
a = (readl(MMC_RES) & 0xffff);
|
||||
for (i = 0; i < 4; i++) {
|
||||
b = (MMC_RES & 0xffff);
|
||||
c = (MMC_RES & 0xffff);
|
||||
b = (readl(MMC_RES) & 0xffff);
|
||||
c = (readl(MMC_RES) & 0xffff);
|
||||
resp[i] = (a << 24) | (b << 8) | (c >> 8);
|
||||
a = c;
|
||||
debug("MMC resp[%d] = %#08x\n", i, resp[i]);
|
||||
|
@ -115,37 +118,38 @@ mmc_block_read(uchar * dst, ulong src, ulong len)
|
|||
/* send read command */
|
||||
argh = src >> 16;
|
||||
argl = src & 0xffff;
|
||||
MMC_STRPCL = MMC_STRPCL_STOP_CLK;
|
||||
MMC_RDTO = 0xffff;
|
||||
MMC_NOB = 1;
|
||||
MMC_BLKLEN = len;
|
||||
writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
|
||||
writel(0xffff, MMC_RDTO);
|
||||
writel(1, MMC_NOB);
|
||||
writel(len, MMC_BLKLEN);
|
||||
mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl,
|
||||
MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK |
|
||||
MMC_CMDAT_DATA_EN);
|
||||
|
||||
MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
|
||||
writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK);
|
||||
while (len) {
|
||||
if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) {
|
||||
if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) {
|
||||
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
|
||||
int i;
|
||||
for (i = min(len, 32); i; i--) {
|
||||
*dst++ = *((volatile uchar *)&MMC_RXFIFO);
|
||||
*dst++ = readb(MMC_RXFIFO);
|
||||
len--;
|
||||
}
|
||||
#else
|
||||
*dst++ = MMC_RXFIFO;
|
||||
*dst++ = readb(MMC_RXFIFO);
|
||||
len--;
|
||||
#endif
|
||||
}
|
||||
status = MMC_STAT;
|
||||
status = readl(MMC_STAT);
|
||||
if (status & MMC_STAT_ERRORS) {
|
||||
printf("MMC_STAT error %lx\n", status);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
|
||||
while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ;
|
||||
status = MMC_STAT;
|
||||
writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
|
||||
while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
|
||||
;
|
||||
status = readl(MMC_STAT);
|
||||
if (status & MMC_STAT_ERRORS) {
|
||||
printf("MMC_STAT error %lx\n", status);
|
||||
return -1;
|
||||
|
@ -176,37 +180,39 @@ mmc_block_write(ulong dst, uchar * src, int len)
|
|||
/* send write command */
|
||||
argh = dst >> 16;
|
||||
argl = dst & 0xffff;
|
||||
MMC_STRPCL = MMC_STRPCL_STOP_CLK;
|
||||
MMC_NOB = 1;
|
||||
MMC_BLKLEN = len;
|
||||
writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
|
||||
writel(1, MMC_NOB);
|
||||
writel(len, MMC_BLKLEN);
|
||||
mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, argh, argl,
|
||||
MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK |
|
||||
MMC_CMDAT_DATA_EN);
|
||||
|
||||
MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ;
|
||||
writel(~MMC_I_MASK_TXFIFO_WR_REQ, MMC_I_MASK);
|
||||
while (len) {
|
||||
if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) {
|
||||
if (readl(MMC_I_REG) & MMC_I_REG_TXFIFO_WR_REQ) {
|
||||
int i, bytes = min(32, len);
|
||||
|
||||
for (i = 0; i < bytes; i++) {
|
||||
MMC_TXFIFO = *src++;
|
||||
writel(*src++, MMC_TXFIFO);
|
||||
}
|
||||
if (bytes < 32) {
|
||||
MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL;
|
||||
writel(MMC_PRTBUF_BUF_PART_FULL, MMC_PRTBUF);
|
||||
}
|
||||
len -= bytes;
|
||||
}
|
||||
status = MMC_STAT;
|
||||
status = readl(MMC_STAT);
|
||||
if (status & MMC_STAT_ERRORS) {
|
||||
printf("MMC_STAT error %lx\n", status);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
|
||||
while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ;
|
||||
MMC_I_MASK = ~MMC_I_MASK_PRG_DONE;
|
||||
while (!(MMC_I_REG & MMC_I_REG_PRG_DONE)) ;
|
||||
status = MMC_STAT;
|
||||
writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
|
||||
while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
|
||||
;
|
||||
writel(~MMC_I_MASK_PRG_DONE, MMC_I_MASK);
|
||||
while (!(readl(MMC_I_REG) & MMC_I_REG_PRG_DONE))
|
||||
;
|
||||
status = readl(MMC_STAT);
|
||||
if (status & MMC_STAT_ERRORS) {
|
||||
printf("MMC_STAT error %lx\n", status);
|
||||
return -1;
|
||||
|
@ -559,13 +565,13 @@ mmc_legacy_init(int verbose)
|
|||
set_GPIO_mode(GPIO8_MMCCS0_MD);
|
||||
#endif
|
||||
#ifdef CONFIG_CPU_MONAHANS /* pxa3xx */
|
||||
CKENA |= CKENA_12_MMC0 | CKENA_13_MMC1;
|
||||
writel(readl(CKENA) | CKENA_12_MMC0 | CKENA_13_MMC1, CKENA);
|
||||
#else /* pxa2xx */
|
||||
CKEN |= CKEN12_MMC; /* enable MMC unit clock */
|
||||
writel(readl(CKEN) | CKEN12_MMC, CKEN); /* enable MMC unit clock */
|
||||
#endif
|
||||
MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
|
||||
MMC_RESTO = MMC_RES_TO_MAX;
|
||||
MMC_SPI = MMC_SPI_DISABLE;
|
||||
writel(MMC_CLKRT_0_3125MHZ, MMC_CLKRT);
|
||||
writel(MMC_RES_TO_MAX, MMC_RESTO);
|
||||
writel(MMC_SPI_DISABLE, MMC_SPI);
|
||||
|
||||
/* reset */
|
||||
mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0);
|
||||
|
@ -624,7 +630,7 @@ mmc_legacy_init(int verbose)
|
|||
mmc_decode_cid(cid_resp);
|
||||
}
|
||||
|
||||
MMC_CLKRT = 0; /* 20 MHz */
|
||||
writel(0, MMC_CLKRT); /* 20 MHz */
|
||||
resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1);
|
||||
|
||||
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
#include <watchdog.h>
|
||||
#include <serial.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -73,60 +74,60 @@ void pxa_setbrg_dev (unsigned int uart_index)
|
|||
switch (uart_index) {
|
||||
case FFUART_INDEX:
|
||||
#ifdef CONFIG_CPU_MONAHANS
|
||||
CKENA |= CKENA_22_FFUART;
|
||||
writel(readl(CKENA) | CKENA_22_FFUART, CKENA);
|
||||
#else
|
||||
CKEN |= CKEN6_FFUART;
|
||||
writel(readl(CKEN) | CKEN6_FFUART, CKEN);
|
||||
#endif /* CONFIG_CPU_MONAHANS */
|
||||
|
||||
FFIER = 0; /* Disable for now */
|
||||
FFFCR = 0; /* No fifos enabled */
|
||||
writel(0, FFIER); /* Disable for now */
|
||||
writel(0, FFFCR); /* No fifos enabled */
|
||||
|
||||
/* set baud rate */
|
||||
FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
|
||||
FFDLL = quot & 0xff;
|
||||
FFDLH = quot >> 8;
|
||||
FFLCR = LCR_WLS0 | LCR_WLS1;
|
||||
writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, FFLCR);
|
||||
writel(quot & 0xff, FFDLL);
|
||||
writel(quot >> 8, FFDLH);
|
||||
writel(LCR_WLS0 | LCR_WLS1, FFLCR);
|
||||
|
||||
FFIER = IER_UUE; /* Enable FFUART */
|
||||
writel(IER_UUE, FFIER); /* Enable FFUART */
|
||||
break;
|
||||
|
||||
case BTUART_INDEX:
|
||||
#ifdef CONFIG_CPU_MONAHANS
|
||||
CKENA |= CKENA_21_BTUART;
|
||||
writel(readl(CKENA) | CKENA_21_BTUART, CKENA);
|
||||
#else
|
||||
CKEN |= CKEN7_BTUART;
|
||||
writel(readl(CKEN) | CKEN7_BTUART, CKEN);
|
||||
#endif /* CONFIG_CPU_MONAHANS */
|
||||
|
||||
BTIER = 0;
|
||||
BTFCR = 0;
|
||||
writel(0, BTIER);
|
||||
writel(0, BTFCR);
|
||||
|
||||
/* set baud rate */
|
||||
BTLCR = LCR_DLAB;
|
||||
BTDLL = quot & 0xff;
|
||||
BTDLH = quot >> 8;
|
||||
BTLCR = LCR_WLS0 | LCR_WLS1;
|
||||
writel(LCR_DLAB, BTLCR);
|
||||
writel(quot & 0xff, BTDLL);
|
||||
writel(quot >> 8, BTDLH);
|
||||
writel(LCR_WLS0 | LCR_WLS1, BTLCR);
|
||||
|
||||
BTIER = IER_UUE; /* Enable BFUART */
|
||||
writel(IER_UUE, BTIER); /* Enable BFUART */
|
||||
|
||||
break;
|
||||
|
||||
case STUART_INDEX:
|
||||
#ifdef CONFIG_CPU_MONAHANS
|
||||
CKENA |= CKENA_23_STUART;
|
||||
writel(readl(CKENA) | CKENA_23_STUART, CKENA);
|
||||
#else
|
||||
CKEN |= CKEN5_STUART;
|
||||
writel(readl(CKEN) | CKEN5_STUART, CKEN);
|
||||
#endif /* CONFIG_CPU_MONAHANS */
|
||||
|
||||
STIER = 0;
|
||||
STFCR = 0;
|
||||
writel(0, STIER);
|
||||
writel(0, STFCR);
|
||||
|
||||
/* set baud rate */
|
||||
STLCR = LCR_DLAB;
|
||||
STDLL = quot & 0xff;
|
||||
STDLH = quot >> 8;
|
||||
STLCR = LCR_WLS0 | LCR_WLS1;
|
||||
writel(LCR_DLAB, STLCR);
|
||||
writel(quot & 0xff, STDLL);
|
||||
writel(quot >> 8, STDLH);
|
||||
writel(LCR_WLS0 | LCR_WLS1, STLCR);
|
||||
|
||||
STIER = IER_UUE; /* Enable STUART */
|
||||
writel(IER_UUE, STIER); /* Enable STUART */
|
||||
break;
|
||||
|
||||
default:
|
||||
|
@ -156,21 +157,21 @@ void pxa_putc_dev (unsigned int uart_index,const char c)
|
|||
switch (uart_index) {
|
||||
case FFUART_INDEX:
|
||||
/* wait for room in the tx FIFO on FFUART */
|
||||
while ((FFLSR & LSR_TEMT) == 0)
|
||||
while ((readl(FFLSR) & LSR_TEMT) == 0)
|
||||
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
||||
FFTHR = c;
|
||||
writel(c, FFTHR);
|
||||
break;
|
||||
|
||||
case BTUART_INDEX:
|
||||
while ((BTLSR & LSR_TEMT ) == 0 )
|
||||
while ((readl(BTLSR) & LSR_TEMT) == 0)
|
||||
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
||||
BTTHR = c;
|
||||
writel(c, BTTHR);
|
||||
break;
|
||||
|
||||
case STUART_INDEX:
|
||||
while ((STLSR & LSR_TEMT ) == 0 )
|
||||
while ((readl(STLSR) & LSR_TEMT) == 0)
|
||||
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
||||
STTHR = c;
|
||||
writel(c, STTHR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -188,11 +189,11 @@ int pxa_tstc_dev (unsigned int uart_index)
|
|||
{
|
||||
switch (uart_index) {
|
||||
case FFUART_INDEX:
|
||||
return FFLSR & LSR_DR;
|
||||
return readl(FFLSR) & LSR_DR;
|
||||
case BTUART_INDEX:
|
||||
return BTLSR & LSR_DR;
|
||||
return readl(BTLSR) & LSR_DR;
|
||||
case STUART_INDEX:
|
||||
return STLSR & LSR_DR;
|
||||
return readl(STLSR) & LSR_DR;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
@ -206,18 +207,21 @@ int pxa_getc_dev (unsigned int uart_index)
|
|||
{
|
||||
switch (uart_index) {
|
||||
case FFUART_INDEX:
|
||||
while (!(FFLSR & LSR_DR))
|
||||
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
||||
return (char) FFRBR & 0xff;
|
||||
while (!(readl(FFLSR) & LSR_DR))
|
||||
/* Reset HW Watchdog, if needed */
|
||||
WATCHDOG_RESET();
|
||||
return (char) readl(FFRBR) & 0xff;
|
||||
|
||||
case BTUART_INDEX:
|
||||
while (!(BTLSR & LSR_DR))
|
||||
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
||||
return (char) BTRBR & 0xff;
|
||||
while (!(readl(BTLSR) & LSR_DR))
|
||||
/* Reset HW Watchdog, if needed */
|
||||
WATCHDOG_RESET();
|
||||
return (char) readl(BTRBR) & 0xff;
|
||||
case STUART_INDEX:
|
||||
while (!(STLSR & LSR_DR))
|
||||
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
||||
return (char) STRBR & 0xff;
|
||||
while (!(readl(STLSR) & LSR_DR))
|
||||
/* Reset HW Watchdog, if needed */
|
||||
WATCHDOG_RESET();
|
||||
return (char) readl(STRBR) & 0xff;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue