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Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
parent
8993e54b6f
commit
b1b54e3520
9 changed files with 151 additions and 104 deletions
46
CHANGELOG
46
CHANGELOG
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@ -1,3 +1,49 @@
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commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6
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Author: Rafal Jaworowski <raj@semihalf.com>
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Date: Fri Jul 27 14:43:59 2007 +0200
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[ADS5121] Support for the ADS5121 board
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The following MPC5121e subsystems are supported:
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- low-level CPU init
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- NOR Boot Flash (common CFI driver)
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- DDR SDRAM
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- FEC
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- I2C
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- Watchdog
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Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
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Signed-off-by: Jan Wrobel <wrr@semihalf.com>
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commit 1863cfb7b100ba0ee3401799457a01dc058745f8
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Author: Rafal Jaworowski <raj@semihalf.com>
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Date: Fri Jul 27 14:22:04 2007 +0200
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[PPC] Remove unused MSR_USER definition
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Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
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commit cc3023b9f95d7ac959a764471a65001062aecf41
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Author: Rafal Jaworowski <raj@semihalf.com>
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Date: Thu Jul 19 17:12:28 2007 +0200
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Fix breakage of 8xx boards from recent commit.
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This patch fixes the negative consequences for 8xx of the recent
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"ppc4xx: Clean up 440 exceptions handling" commit.
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Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
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commit 3a6cab844cf74f76639d795e0be8717e02c86af7
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Author: Wolfgang Denk <wd@denx.de>
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Date: Sat Jul 14 22:51:02 2007 +0200
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Update CHANGELOG
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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commit 011595307731a7a67a7445d107c279d031e8ab97
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Author: Heiko Schocher <hs@pollux.denx.de>
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Date: Sat Jul 14 01:06:58 2007 +0200
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@ -114,7 +114,7 @@ long int fixed_sdram (void)
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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*/
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i = im->sysconf.ddrlaw.ar;
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__asm__ __volatile__ ("isync");
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@ -183,6 +183,6 @@ int checkboard (void)
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uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
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printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
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brd_rev, cpld_rev);
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brd_rev, cpld_rev);
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return 0;
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}
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@ -77,20 +77,20 @@ static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
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* Trasmit BDs init
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*/
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for (ix = 0; ix < FEC_TBD_NUM; ix++) {
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fec->bdBase->tbd[ix].status = 0;
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}
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fec->bdBase->tbd[ix].status = 0;
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}
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/*
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* Have the last TBD to close the ring
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*/
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fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
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/*
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* Have the last TBD to close the ring
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*/
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fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
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/*
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* Initialize some indices
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*/
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fec->tbdIndex = 0;
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fec->usedTbdIndex = 0;
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fec->cleanTbdNum = FEC_TBD_NUM;
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/*
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* Initialize some indices
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*/
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fec->tbdIndex = 0;
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fec->usedTbdIndex = 0;
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fec->cleanTbdNum = FEC_TBD_NUM;
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return 0;
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}
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@ -346,7 +346,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
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#if (DEBUG & 0x2)
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printf ("done.\n");
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#endif
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} else { /* MII100 */
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} else { /* MII100 */
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/*
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* Set the auto-negotiation advertisement register bits
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*/
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@ -85,8 +85,8 @@ int get_clocks (void)
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csb_clk = sys_clk / 2;
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cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
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core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
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cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
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core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
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ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
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if (ips_div != 0) {
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@ -208,8 +208,8 @@ boot_cold:
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*/
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/* Boot CS/CS0 window range */
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lis r3, CFG_IMMR@h
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ori r3, r3, CFG_IMMR@l
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lis r3, CFG_IMMR@h
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ori r3, r3, CFG_IMMR@l
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lis r4, START_REG(CFG_FLASH_BASE)
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ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE)
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@ -224,9 +224,9 @@ boot_cold:
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/*
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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*/
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lwz r4, SRAMBAR(r3)
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isync
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@ -235,11 +235,11 @@ boot_cold:
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* config register so no params can be set for it
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*/
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lis r3, (CFG_IMMR + LPC_OFFSET)@h
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ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
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ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
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lis r4, CFG_CS0_CFG@h
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ori r4, r4, CFG_CS0_CFG@l
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stw r4, CS0_CONFIG(r3)
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lis r4, CFG_CS0_CFG@h
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ori r4, r4, CFG_CS0_CFG@l
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stw r4, CS0_CONFIG(r3)
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/* Master enable all CS's */
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lis r4, CS_CTRL_ME@h
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@ -65,48 +65,49 @@
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#define CFG_SDRAM_BASE CFG_DDR_BASE
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/* DDR Controller Configuration
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SYS_CFG:
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[31:31] MDDRC Soft Reset: Diabled
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[30:30] DRAM CKE pin: Enabled
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[29:29] DRAM CLK: Enabled
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[28:28] Command Mode: Enabled (For initialization only)
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[27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
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[24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
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[20:19] Read Test: DON'T USE
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[18:18] Self Refresh: Enabled
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[17:17] 16bit Mode: Disabled
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[16:13] Ready Delay: 2
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[12:12] Half DQS Delay: Disabled
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[11:11] Quarter DQS Delay: Disabled
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[10:08] Write Delay: 2
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[07:07] Early ODT: Disabled
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[06:06] On DIE Termination: Disabled
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[05:05] FIFO Overflow Clear: DON'T USE here
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[04:04] FIFO Underflow Clear: DON'T USE here
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[03:03] FIFO Overflow Pending: DON'T USE here
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[02:02] FIFO Underlfow Pending: DON'T USE here
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[01:01] FIFO Overlfow Enabled: Enabled
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[00:00] FIFO Underflow Enabled: Enabled
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TIME_CFG0
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[31:16] DRAM Refresh Time: 0 CSB clocks
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[15:8] DRAM Command Time: 0 CSB clocks
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[07:00] DRAM Precharge Time: 0 CSB clocks
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TIME_CFG1
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[31:26] DRAM tRFC:
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[25:21] DRAM tWR1:
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[20:17] DRAM tWRT1:
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[16:11] DRAM tDRR:
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[10:05] DRAM tRC:
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[04:00] DRAM tRAS:
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TIME_CFG2
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[31:28] DRAM tRCD:
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[27:23] DRAM tFAW:
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[22:19] DRAM tRTW1:
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[18:15] DRAM tCCD:
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[14:10] DRAM tRTP:
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[09:05] DRAM tRP:
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[04:00] DRAM tRPA */
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*
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* SYS_CFG:
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* [31:31] MDDRC Soft Reset: Diabled
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* [30:30] DRAM CKE pin: Enabled
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* [29:29] DRAM CLK: Enabled
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* [28:28] Command Mode: Enabled (For initialization only)
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* [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
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* [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
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* [20:19] Read Test: DON'T USE
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* [18:18] Self Refresh: Enabled
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* [17:17] 16bit Mode: Disabled
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* [16:13] Ready Delay: 2
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* [12:12] Half DQS Delay: Disabled
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* [11:11] Quarter DQS Delay: Disabled
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* [10:08] Write Delay: 2
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* [07:07] Early ODT: Disabled
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* [06:06] On DIE Termination: Disabled
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* [05:05] FIFO Overflow Clear: DON'T USE here
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* [04:04] FIFO Underflow Clear: DON'T USE here
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* [03:03] FIFO Overflow Pending: DON'T USE here
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* [02:02] FIFO Underlfow Pending: DON'T USE here
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* [01:01] FIFO Overlfow Enabled: Enabled
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* [00:00] FIFO Underflow Enabled: Enabled
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* TIME_CFG0
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* [31:16] DRAM Refresh Time: 0 CSB clocks
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* [15:8] DRAM Command Time: 0 CSB clocks
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* [07:00] DRAM Precharge Time: 0 CSB clocks
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* TIME_CFG1
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* [31:26] DRAM tRFC:
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* [25:21] DRAM tWR1:
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* [20:17] DRAM tWRT1:
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* [16:11] DRAM tDRR:
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* [10:05] DRAM tRC:
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* [04:00] DRAM tRAS:
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* TIME_CFG2
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* [31:28] DRAM tRCD:
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* [27:23] DRAM tFAW:
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* [22:19] DRAM tRTW1:
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* [18:15] DRAM tCCD:
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* [14:10] DRAM tRTP:
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* [09:05] DRAM tRP:
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* [04:00] DRAM tRPA
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*/
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#define CFG_MDDRC_SYS_CFG 0xF8604200
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#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200
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@ -276,7 +277,7 @@ SYS_CFG:
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
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| CFG_CMD_NET \
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| CFG_CMD_PING \
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| CFG_CMD_MII \
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| CFG_CMD_MII \
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| CFG_CMD_I2C)
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#endif
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@ -384,26 +385,26 @@ SYS_CFG:
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"bootm\0" \
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"load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \
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"update=protect off fff00000 fff3ffff; " \
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"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
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"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
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"upd=run load;run update\0" \
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""
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND "run flash_self"
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