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net/phy/cortina: Add No firmware upload option

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Current Cortina phy driver assumes that firmware upload
is required during initialization and is dependent
on presence of corresponding macros like CONFIG_CORTINA_FW_ADDR
for compilation.

But Cortina phy has provision to store phy firmware in
attached dedicated EEPROM. And boards designed with such
EEPROM does not require firmware upload.

Add CORTINA_NO_FW_UPLOAD option in cortina.c to support
such boards.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Priyanka Jain 2018-01-30 12:11:08 +05:30 • committed by Joe Hershberger
parent af5484acb0
commit b321c44ac9
1 changed files with 13 additions and 0 deletions
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13
drivers/net/phy/cortina.c
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@ -4,6 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
* *
* Copyright 2014 Freescale Semiconductor, Inc. * Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
* *
*/ */
@ -27,6 +28,7 @@
#error The Cortina PHY needs 10G support #error The Cortina PHY needs 10G support
#endif #endif
#ifndef CORTINA_NO_FW_UPLOAD
struct cortina_reg_config cortina_reg_cfg[] = { struct cortina_reg_config cortina_reg_cfg[] = {
/* CS4315_enable_sr_mode */ /* CS4315_enable_sr_mode */
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
@ -215,12 +217,22 @@ void cs4340_upload_firmware(struct phy_device *phydev)
phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
} }
} }
#endif
int cs4340_phy_init(struct phy_device *phydev) int cs4340_phy_init(struct phy_device *phydev)
{ {
#ifndef CORTINA_NO_FW_UPLOAD
int timeout = 100; /* 100ms */ int timeout = 100; /* 100ms */
#endif
int reg_value; int reg_value;
/*
* Cortina phy has provision to store
* phy firmware in attached dedicated EEPROM.
* Boards designed with EEPROM attached to Cortina
* does not require FW upload.
*/
#ifndef CORTINA_NO_FW_UPLOAD
/* step1: BIST test */ /* step1: BIST test */
phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
@ -241,6 +253,7 @@ int cs4340_phy_init(struct phy_device *phydev)
/* setp2: upload ucode */ /* setp2: upload ucode */
cs4340_upload_firmware(phydev); cs4340_upload_firmware(phydev);
#endif
reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
if (reg_value) { if (reg_value) {
debug("%s checksum status failed.\n", __func__); debug("%s checksum status failed.\n", __func__);