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mx6: Set shared override bit in PL310 AUX_CTRL register
Having bit 22 cleared in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. This was inspired by a patch from Catalin Marinas [1] and also from recent discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring suggested that bootloaders should initialize the cache. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html [2] https://lkml.org/lkml/2015/2/20/199 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
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2 changed files with 10 additions and 0 deletions
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@ -523,6 +523,14 @@ void v7_outer_cache_enable(void)
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struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
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struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
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unsigned int val;
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unsigned int val;
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/*
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* Set bit 22 in the auxiliary control register. If this bit
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* is cleared, PL310 treats Normal Shared Non-cacheable
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* accesses as Cacheable no-allocate.
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*/
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setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
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#if defined CONFIG_MX6SL
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#if defined CONFIG_MX6SL
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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val = readl(&iomux->gpr[11]);
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val = readl(&iomux->gpr[11]);
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@ -16,6 +16,8 @@
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#define L2X0_STNDBY_MODE_EN (1 << 0)
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#define L2X0_STNDBY_MODE_EN (1 << 0)
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#define L2X0_CTRL_EN 1
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#define L2X0_CTRL_EN 1
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#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22)
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struct pl310_regs {
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struct pl310_regs {
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u32 pl310_cache_id;
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u32 pl310_cache_id;
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u32 pl310_cache_type;
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u32 pl310_cache_type;
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