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board: ge: bx50v3: Enable DM for PCI and ethernet
DM for PCI pulls DM for ethernet that also needs other changes described below to build u-boot and keep existing functionality - ability to update MAC addresses of FEC ethernet adapter and I210 adapter connected to the Marvell switch. - fec_mxc driver with DM needs PHYLIB; - configuration items are moved from ge_bx50v3.h to ge_bx50v3_defconfig; - FEC is marked as eth0 because it is always present, so indices changed: I210 are still probed in the same order; - board_eth_init() was used by legacy ethernet, setup for enet iomux and pcie is moved to the board_late_init(); - pci_init() is called from the board_late_init() to initiate PCI bus probing, so I210 devices are propagated to the device tree; Signed-off-by: Denis Zalevskiy <denis.zalevskiy@ge.com> [Describe PHY reset in device tree] Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
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833dd6444b
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3 changed files with 21 additions and 74 deletions
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@ -36,6 +36,8 @@
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#include "../common/ge_common.h"
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#include "../common/ge_common.h"
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#include "../common/vpd_reader.h"
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#include "../common/vpd_reader.h"
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#include "../../../drivers/net/e1000.h"
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#include "../../../drivers/net/e1000.h"
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#include <pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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static int confidx; /* Default to generic. */
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static int confidx; /* Default to generic. */
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@ -83,38 +85,6 @@ static iomux_v3_cfg_t const uart4_pads[] = {
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MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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/* AR8033 PHY Reset */
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MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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/* Reset AR8033 PHY */
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gpio_request(IMX_GPIO_NR(1, 28), "fec_rst");
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gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
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mdelay(10);
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gpio_set_value(IMX_GPIO_NR(1, 28), 1);
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mdelay(1);
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}
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static struct i2c_pads_info i2c_pad_info1 = {
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.scl = {
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.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
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.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
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@ -154,16 +124,6 @@ static struct i2c_pads_info i2c_pad_info3 = {
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}
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}
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};
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};
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static iomux_v3_cfg_t const pcie_pads[] = {
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MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_pcie(void)
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{
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imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
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}
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static void setup_iomux_uart(void)
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static void setup_iomux_uart(void)
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{
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{
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imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
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imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
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@ -455,7 +415,7 @@ static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
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static void process_vpd(struct vpd_cache *vpd)
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static void process_vpd(struct vpd_cache *vpd)
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{
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{
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int fec_index = -1;
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int fec_index = 0;
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int i210_index = -1;
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int i210_index = -1;
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if (!vpd->is_read) {
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if (!vpd->is_read) {
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@ -463,41 +423,30 @@ static void process_vpd(struct vpd_cache *vpd)
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return;
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return;
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}
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}
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if (vpd->has & VPD_HAS_MAC1)
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eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
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env_set("ethact", "eth0");
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switch (vpd->product_id) {
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switch (vpd->product_id) {
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case VPD_PRODUCT_B450:
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case VPD_PRODUCT_B450:
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env_set("confidx", "1");
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env_set("confidx", "1");
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i210_index = 0;
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i210_index = 1;
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fec_index = 1;
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break;
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break;
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case VPD_PRODUCT_B650:
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case VPD_PRODUCT_B650:
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env_set("confidx", "2");
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env_set("confidx", "2");
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i210_index = 0;
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i210_index = 1;
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fec_index = 1;
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break;
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break;
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case VPD_PRODUCT_B850:
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case VPD_PRODUCT_B850:
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env_set("confidx", "3");
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env_set("confidx", "3");
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i210_index = 1;
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i210_index = 2;
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fec_index = 2;
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break;
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break;
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}
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}
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if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
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eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
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if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
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if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
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eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
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eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
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}
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}
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int board_eth_init(bd_t *bis)
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{
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setup_iomux_enet();
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setup_pcie();
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e1000_initialize(bis);
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return cpu_eth_init(bis);
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}
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static iomux_v3_cfg_t const misc_pads[] = {
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static iomux_v3_cfg_t const misc_pads[] = {
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MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
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MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
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@ -659,6 +608,8 @@ int board_late_init(void)
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check_time();
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check_time();
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pci_init();
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return 0;
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return 0;
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}
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}
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@ -75,3 +75,11 @@ CONFIG_IMX_WATCHDOG=y
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# CONFIG_EFI_LOADER is not set
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# CONFIG_EFI_LOADER is not set
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CONFIG_SYS_MALLOC_F_LEN=0x4000
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CONFIG_SYS_MALLOC_F_LEN=0x4000
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CONFIG_SYS_WHITE_ON_BLACK=y
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CONFIG_SYS_WHITE_ON_BLACK=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_PCI_PNP=y
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CONFIG_DM_ETH=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_FEC_MXC=y
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CONFIG_ETHPRIME="FEC"
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@ -49,16 +49,6 @@
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#define CONFIG_USB_GADGET_MASS_STORAGE
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#define CONFIG_USB_GADGET_MASS_STORAGE
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#endif
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#endif
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/* Networking Configs */
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#ifdef CONFIG_NET
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 4
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#define CONFIG_PHY_ATHEROS
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#endif
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/* Serial Flash */
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/* Serial Flash */
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/* allow to overwrite serial and ethaddr */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_IMX6_PWM_PER_CLK 66000000
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#define CONFIG_IMX6_PWM_PER_CLK 66000000
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_PCIE_IMX
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#define CONFIG_PCIE_IMX
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#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
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#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
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