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mmc: sunxi: Cleanup and fix self-calibration code
Newer SoCs have a self calibration feature, which avoids us writing hard coded phase delay values into the controller. Consolidate the code by avoiding unnecessary #ifdefs, and also enabling the feature for all those newer SoCs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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commit
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1 changed files with 19 additions and 8 deletions
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@ -103,21 +103,29 @@ static int mmc_resource_init(int sdc_no)
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}
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#endif
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/*
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* All A64 and later MMC controllers feature auto-calibration. This would
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* normally be detected via the compatible string, but we need something
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* which works in the SPL as well.
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*/
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static bool sunxi_mmc_can_calibrate(void)
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{
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return IS_ENABLED(CONFIG_MACH_SUN50I) ||
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IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
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IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
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IS_ENABLED(CONFIG_MACH_SUN8I_R40);
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}
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static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
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{
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unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
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bool new_mode = IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE);
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bool calibrate = false;
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u32 val = 0;
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/* A83T support new mode only on eMMC */
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if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
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new_mode = false;
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#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_SUN50I_GEN_H6)
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calibrate = true;
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#endif
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if (hz <= 24000000) {
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pll = CCM_MMC_CTRL_OSCM24;
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pll_hz = 24000000;
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@ -179,7 +187,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
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if (new_mode) {
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val |= CCM_MMC_CTRL_MODE_SEL_NEW;
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setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
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} else if (!calibrate) {
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}
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if (!sunxi_mmc_can_calibrate()) {
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/*
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* Use hardcoded delay values if controller doesn't support
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* calibration
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@ -237,14 +247,15 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
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rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
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writel(rval, &priv->reg->clkcr);
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#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_SUN50I_GEN_H6)
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#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
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/* A64 supports calibration of delays on MMC controller and we
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* have to set delay of zero before starting calibration.
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* Allwinner BSP driver sets a delay only in the case of
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* using HS400 which is not supported by mainline U-Boot or
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* Linux at the moment
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*/
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writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
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if (sunxi_mmc_can_calibrate())
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writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
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#endif
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/* Re-enable Clock */
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