mirror of
https://github.com/Fishwaldo/u-boot.git
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powerpc/T4QDS: add two stage boot of nand/sd
Add support of 2 stage NAND/SD boot loader using SPL framework. PBL initialise the internal SRAM and copy SPL, this further initialise DDR using SPD and environment and copy u-boot from NAND/SD to DDR, finally SPL transfer control to u-boot. NOR uses CS1 instead of CS2 when NAND boot, fix it. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Shaohui Xie
York Sun
parent
cb753850e8
commit
b6036993eb
8 changed files with 310 additions and 27 deletions
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@ -4,10 +4,14 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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else
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obj-$(CONFIG_T4240QDS) += t4240qds.o
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obj-$(CONFIG_T4240EMU) += t4240emu.o
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obj-y += ddr.o
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obj-$(CONFIG_T4240QDS)+= eth.o
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obj-$(CONFIG_PCI) += pci.o
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endif
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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@ -117,11 +117,15 @@ phys_size_t initdram(int board_type)
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puts("Initializing....using SPD\n");
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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#else
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/* DDR has been initialised by first stage boot loader */
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dram_size = fsl_ddr_sdram_size();
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#endif
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return dram_size;
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}
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141
board/freescale/t4qds/spl.c
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141
board/freescale/t4qds/spl.c
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@ -0,0 +1,141 @@
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/* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/spl.h>
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#include <malloc.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <i2c.h>
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#include "../common/qixis.h"
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#include "t4240qds_qixis.h"
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#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
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DECLARE_GLOBAL_DATA_PTR;
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phys_size_t get_effective_memsize(void)
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{
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return CONFIG_SYS_L3_SIZE;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0F) {
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio, sys_clk, ccb_clk;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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#ifdef CONFIG_SPL_NAND_BOOT
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u32 porsr1, pinctl;
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#endif
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#ifdef CONFIG_SPL_NAND_BOOT
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porsr1 = in_be32(&gur->porsr1);
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pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
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out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
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#endif
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/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
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memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
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/* Update GD pointer */
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gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
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/* compiler optimization barrier needed for GCC >= 3.4 */
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__asm__ __volatile__("" : : : "memory");
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console_init_f();
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/* initialize selected port with appropriate baud rate */
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sys_clk = get_board_sys_clk();
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plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
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ccb_clk = sys_clk * plat_ratio / 2;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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ccb_clk / 16 / CONFIG_BAUDRATE);
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#ifdef CONFIG_SPL_MMC_BOOT
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puts("\nSD boot...\n");
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#elif defined(CONFIG_SPL_NAND_BOOT)
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puts("\nNAND boot...\n");
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#endif
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relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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bd_t *bd;
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bd = (bd_t *)(gd + sizeof(gd_t));
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memset(bd, 0, sizeof(bd_t));
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gd->bd = bd;
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bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
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bd->bi_memsize = CONFIG_SYS_L3_SIZE;
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probecpu();
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get_clocks();
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
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CONFIG_SPL_RELOC_MALLOC_SIZE);
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#ifdef CONFIG_SPL_NAND_BOOT
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_ENV_ADDR);
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#endif
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_initialize(bd);
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mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_ENV_ADDR);
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#endif
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gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
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gd->env_valid = 1;
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i2c_init_all();
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gd->ram_size = initdram(0);
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_boot();
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#elif defined(CONFIG_SPL_NAND_BOOT)
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nand_boot();
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#endif
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}
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@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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#ifndef CONFIG_SPL_BUILD
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/* *I*G* - PCI */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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@ -105,6 +105,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 12, BOOKE_PAGESZ_16M, 1),
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#endif
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#endif
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#ifdef CONFIG_SYS_DCSRBAR_PHYS
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SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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@ -136,6 +137,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
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0, 18, BOOKE_PAGESZ_1M, 1),
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#endif
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#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
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SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 19, BOOKE_PAGESZ_2G, 1)
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@ -971,13 +971,14 @@ Active powerpc mpc85xx - freescale t208xrdb
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Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
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Active powerpc mpc85xx - freescale t4qds T4160QDS_SECURE_BOOT T4240QDS:PPC_T4160,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
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Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale t4qds T4160QDS_NAND T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
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Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
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Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com>
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Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 -
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Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
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Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
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Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
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Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale qemu-ppce500 qemu-ppce500 - Alexander Graf <agraf@suse.de>
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@ -120,3 +120,56 @@ The override voltage takes effect when booting.
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Note: voltage adjustment needs to be done step by step. Changing voltage too
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rapidly may cause current surge. The voltage stepping is done by software.
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Users can set the final voltage directly.
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2-stage NAND/SD boot loader
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-------------------------------
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PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
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SPL further initialise DDR using SPD and environment variables
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and copy u-boot(768 KB) from NAND/SD device to DDR.
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Finally SPL transers control to u-boot for futher booting.
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SPL has following features:
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- Executes within 256K
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- No relocation required
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Run time view of SPL framework
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-------------------------------------------------
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|Area | Address |
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-------------------------------------------------
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|SecureBoot header | 0xFFFC0000 (32KB) |
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-------------------------------------------------
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|GD, BD | 0xFFFC8000 (4KB) |
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-------------------------------------------------
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|ENV | 0xFFFC9000 (8KB) |
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-------------------------------------------------
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|HEAP | 0xFFFCB000 (50KB) |
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-------------------------------------------------
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|STACK | 0xFFFD8000 (22KB) |
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-------------------------------------------------
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|U-boot SPL | 0xFFFD8000 (160KB) |
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-------------------------------------------------
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NAND Flash memory Map on T4QDS
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--------------------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF u-boot img 1MB
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0x140000 0x15FFFF u-boot env 128KB
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0x160000 0x17FFFF FMAN Ucode 128KB
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Micro SD Card memory Map on T4QDS
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----------------------------------------------------
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Block #blocks Definition Size
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0x008 2048 u-boot img 1MB
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0x800 0016 u-boot env 8KB
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0x820 0128 FMAN ucode 64KB
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Switch Settings: (ON is 1, OFF is 0)
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===============
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NAND boot SW setting:
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SW1[1:8] = 10000010
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SW2[1.1] = 0
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SW6[1:4] = 1001
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SD boot SW setting:
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SW1[1:8] = 00100000
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SW2[1.1] = 0
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@ -19,12 +19,65 @@
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#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
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#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
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#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#else
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#define CONFIG_SPL
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x00201000
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_MAX_SIZE 0x28000
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#define RESET_VECTOR_OFFSET 0x27FFC
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#define BOOT_PAGE_OFFSET 0x27000
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#ifdef CONFIG_NAND
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
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#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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#define CONFIG_SPL_NAND_BOOT
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_MMC_MINIMAL
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#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
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#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
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#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#endif
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
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#define CONFIG_SPL_MMC_BOOT
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#endif
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_SKIP_RELOCATE
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#define CONFIG_SPL_COMMON_INIT_DDR
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#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#define CONFIG_SYS_NO_FLASH
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#endif
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#endif
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#endif /* CONFIG_RAMBOOT_PBL */
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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/* Set 1M boot space */
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
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@ -64,12 +117,12 @@
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET (512 * 1658)
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#define CONFIG_ENV_OFFSET (512 * 0x800)
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#elif defined(CONFIG_NAND)
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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#define CONFIG_ENV_IS_IN_REMOTE
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#define CONFIG_ENV_ADDR 0xffe20000
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@ -244,8 +297,16 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
|
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
|
|
@ -261,6 +322,14 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
|
||||
|
|
@ -270,14 +339,6 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#endif
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
|
|
@ -379,14 +440,14 @@ unsigned long get_board_ddr_clk(void);
|
|||
#elif defined(CONFIG_SDCARD)
|
||||
/*
|
||||
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
|
||||
* about 825KB (1650 blocks), Env is stored after the image, and the env size is
|
||||
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
|
||||
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
|
||||
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
|
||||
/*
|
||||
* Slave has no ucode locally, it can fetch this from remote. When implementing
|
||||
|
|
|
|||
|
|
@ -68,7 +68,16 @@
|
|||
/*
|
||||
* Config the L3 Cache as L3 SRAM
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
|
||||
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
|
||||
#define CONFIG_SYS_L3_SIZE (512 << 10)
|
||||
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
|
||||
#endif
|
||||
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
|
||||
#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
|
||||
#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
|
||||
#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
|
||||
|
||||
#define CONFIG_SYS_DCSRBAR 0xf0000000
|
||||
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
|
||||
|
|
@ -96,7 +105,11 @@
|
|||
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
|
||||
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue