mirror of
https://github.com/Fishwaldo/u-boot.git
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rockchip: rk322x: add dts file
The dts files are from kernel and with modify to adapt U-Boot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Kever Yang
Philipp Tomsich
parent
5cc9d31a79
commit
b647442ce8
3 changed files with 1025 additions and 0 deletions
77
arch/arm/dts/rk3229-evb.dts
Normal file
77
arch/arm/dts/rk3229-evb.dts
Normal file
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@ -0,0 +1,77 @@
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+ X11
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*/
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/dts-v1/;
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#include "rk322x.dtsi"
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/ {
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model = "Rockchip RK3229 Evaluation board";
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compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
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chosen {
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stdout-path = &uart2;
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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ext_gmac: ext_gmac {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "ext_gmac";
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#clock-cells = <0>;
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};
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vcc_phy: vcc-phy-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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regulator-name = "vcc_phy";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&dmc {
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rockchip,sdram-channel = /bits/ 8 <1 10 3 2 1 0 15 15>;
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rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
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0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
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0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
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0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
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0x0 0x924>;
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rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
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rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
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0 300 3 0 120>;
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};
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&gmac {
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assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
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assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
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clock_in_out = "input";
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phy-supply = <&vcc_phy>;
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 1000000>;
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tx_delay = <0x30>;
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rx_delay = <0x10>;
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status = "okay";
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};
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&emmc {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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710
arch/arm/dts/rk322x.dtsi
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710
arch/arm/dts/rk322x.dtsi
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@ -0,0 +1,710 @@
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/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3228-cru.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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resets = <&cru SRST_CORE0>;
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operating-points = <
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/* KHz uV */
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816000 1000000
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>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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cpu1: cpu@f01 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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resets = <&cru SRST_CORE1>;
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};
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cpu2: cpu@f02 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf02>;
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resets = <&cru SRST_CORE2>;
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};
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cpu3: cpu@f03 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf03>;
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resets = <&cru SRST_CORE3>;
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};
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@110f0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x110f0000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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timer {
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compatible = "arm,armv7-timer";
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arm,cpu-registers-not-fw-configured;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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bus_intmem@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x9000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x9000>;
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smp-sram@0 {
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compatible = "rockchip,rk322x-smp-sram";
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reg = <0x00 0x10>;
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};
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ddr_sram: ddr-sram@1000 {
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compatible = "rockchip,rk322x-ddr-sram";
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reg = <0x1000 0x8000>;
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};
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};
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i2s1: i2s1@100b0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100b0000 0x4000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
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dmas = <&pdma 14>, <&pdma 15>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&i2s1_bus>;
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status = "disabled";
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};
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i2s0: i2s0@100c0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100c0000 0x4000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
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dmas = <&pdma 11>, <&pdma 12>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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i2s2: i2s2@100e0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100e0000 0x4000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
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dmas = <&pdma 0>, <&pdma 1>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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grf: syscon@11000000 {
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u-boot,dm-pre-reloc;
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compatible = "rockchip,rk3228-grf", "syscon";
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reg = <0x11000000 0x1000>;
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};
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uart0: serial@11010000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x11010000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@11020000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x11020000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@11030000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x11030000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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i2c0: i2c@11050000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11050000 0x1000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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status = "disabled";
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};
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i2c1: i2c@11060000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11060000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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status = "disabled";
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};
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i2c2: i2c@11070000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11070000 0x1000>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C2>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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status = "disabled";
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};
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i2c3: i2c@11080000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11080000 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C3>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_xfer>;
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status = "disabled";
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};
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pwm0: pwm@110b0000 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0000 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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status = "disabled";
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};
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pwm1: pwm@110b0010 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0010 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_pin>;
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status = "disabled";
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};
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pwm2: pwm@110b0020 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0020 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm2_pin>;
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status = "disabled";
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};
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pwm3: pwm@110b0030 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0030 0x10>;
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#pwm-cells = <2>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm3_pin>;
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status = "disabled";
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};
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timer: timer@110c0000 {
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compatible = "rockchip,rk3288-timer";
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reg = <0x110c0000 0x20>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>, <&cru PCLK_TIMER>;
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clock-names = "timer", "pclk";
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};
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cru: clock-controller@110e0000 {
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u-boot,dm-pre-reloc;
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compatible = "rockchip,rk3228-cru";
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reg = <0x110e0000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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assigned-clocks = <&cru PLL_GPLL>;
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assigned-clock-rates = <594000000>;
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <100>; /* milliseconds */
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polling-delay = <5000>; /* milliseconds */
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thermal-sensors = <&tsadc 0>;
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trips {
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cpu_alert0: cpu_alert0 {
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temperature = <70000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert1: cpu_alert1 {
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temperature = <75000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_crit: cpu_crit {
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temperature = <90000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT 6>;
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};
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map1 {
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trip = <&cpu_alert1>;
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cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tsadc: tsadc@11150000 {
|
||||
compatible = "rockchip,rk3228-tsadc";
|
||||
reg = <0x11150000 0x100>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
|
||||
clock-names = "tsadc", "apb_pclk";
|
||||
resets = <&cru SRST_TSADC>;
|
||||
reset-names = "tsadc-apb";
|
||||
pinctrl-names = "init", "default", "sleep";
|
||||
pinctrl-0 = <&otp_gpio>;
|
||||
pinctrl-1 = <&otp_out>;
|
||||
pinctrl-2 = <&otp_gpio>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
rockchip,hw-tshut-temp = <95000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emmc: dwmmc@30020000 {
|
||||
compatible = "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x30020000 0x4000>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <37500000>;
|
||||
max-frequency = <37500000>;
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
||||
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
|
||||
bus-width = <8>;
|
||||
default-sample-phase = <158>;
|
||||
num-slots = <1>;
|
||||
fifo-depth = <0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
||||
resets = <&cru SRST_EMMC>;
|
||||
reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac: ethernet@30200000 {
|
||||
compatible = "rockchip,rk3228-gmac";
|
||||
reg = <0x30200000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
|
||||
<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
|
||||
<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
|
||||
<&cru PCLK_GMAC>;
|
||||
clock-names = "stmmaceth", "mac_clk_rx",
|
||||
"mac_clk_tx", "clk_mac_ref",
|
||||
"clk_mac_refout", "aclk_mac",
|
||||
"pclk_mac";
|
||||
resets = <&cru SRST_GMAC>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@32010000 {
|
||||
compatible = "arm,gic-400";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
|
||||
reg = <0x32011000 0x1000>,
|
||||
<0x32012000 0x2000>,
|
||||
<0x32014000 0x2000>,
|
||||
<0x32016000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3228-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio0@11110000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x11110000 0x100>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio1@11120000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x11120000 0x100>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO1>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio2@11130000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x11130000 0x100>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO2>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio3@11140000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x11140000 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO3>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
rgmii_pins: rgmii-pins {
|
||||
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
||||
<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
||||
<2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
||||
<2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
||||
<2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
||||
<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
||||
<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
rmii_pins: rmii-pins {
|
||||
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
||||
<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
||||
<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
||||
<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
phy_pins: phy-pins {
|
||||
rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
i2c0_xfer: i2c0-xfer {
|
||||
rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
i2c1_xfer: i2c1-xfer {
|
||||
rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
i2c2_xfer: i2c2-xfer {
|
||||
rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3 {
|
||||
i2c3_xfer: i2c3-xfer {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s1 {
|
||||
i2s1_bus: i2s1-bus {
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm0 {
|
||||
pwm0_pin: pwm0-pin {
|
||||
rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm1 {
|
||||
pwm1_pin: pwm1-pin {
|
||||
rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2 {
|
||||
pwm2_pin: pwm2-pin {
|
||||
rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3 {
|
||||
pwm3_pin: pwm3-pin {
|
||||
rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
tsadc {
|
||||
otp_gpio: otp-gpio {
|
||||
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
otp_out: otp-out {
|
||||
rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_rts: uart1-rts {
|
||||
rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart2_cts: uart2-cts {
|
||||
rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart2_rts: uart2-rts {
|
||||
rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dmc: dmc@11200000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "rockchip,rk3228-dmc", "syscon";
|
||||
rockchip,cru = <&cru>;
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,msch = <&service_msch>;
|
||||
reg = <0x11200000 0x3fc
|
||||
0x12000000 0x400>;
|
||||
rockchip,sram = <&ddr_sram>;
|
||||
};
|
||||
|
||||
service_msch: syscon@31090000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "rockchip,rk3228-msch", "syscon";
|
||||
reg = <0x31090000 0x2000>;
|
||||
};
|
||||
};
|
||||
238
include/dt-bindings/clock/rk3228-cru.h
Normal file
238
include/dt-bindings/clock/rk3228-cru.h
Normal file
|
|
@ -0,0 +1,238 @@
|
|||
/*
|
||||
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_GPLL 4
|
||||
#define ARMCLK 5
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_SPI0 65
|
||||
#define SCLK_NANDC 67
|
||||
#define SCLK_SDMMC 68
|
||||
#define SCLK_SDIO 69
|
||||
#define SCLK_EMMC 71
|
||||
#define SCLK_TSADC 72
|
||||
#define SCLK_UART0 77
|
||||
#define SCLK_UART1 78
|
||||
#define SCLK_UART2 79
|
||||
#define SCLK_I2S0 80
|
||||
#define SCLK_I2S1 81
|
||||
#define SCLK_I2S2 82
|
||||
#define SCLK_SPDIF 83
|
||||
#define SCLK_TIMER0 85
|
||||
#define SCLK_TIMER1 86
|
||||
#define SCLK_TIMER2 87
|
||||
#define SCLK_TIMER3 88
|
||||
#define SCLK_TIMER4 89
|
||||
#define SCLK_TIMER5 90
|
||||
#define SCLK_I2S_OUT 113
|
||||
#define SCLK_SDMMC_DRV 114
|
||||
#define SCLK_SDIO_DRV 115
|
||||
#define SCLK_EMMC_DRV 117
|
||||
#define SCLK_SDMMC_SAMPLE 118
|
||||
#define SCLK_SDIO_SAMPLE 119
|
||||
#define SCLK_EMMC_SAMPLE 121
|
||||
#define SCLK_VOP 122
|
||||
#define SCLK_HDMI_HDCP 123
|
||||
#define SCLK_MAC_SRC 124
|
||||
#define SCLK_MAC_EXTCLK 125
|
||||
#define SCLK_MAC 126
|
||||
#define SCLK_MAC_REFOUT 127
|
||||
#define SCLK_MAC_REF 128
|
||||
#define SCLK_MAC_RX 129
|
||||
#define SCLK_MAC_TX 130
|
||||
#define SCLK_MAC_PHY 131
|
||||
#define SCLK_MAC_OUT 132
|
||||
|
||||
/* dclk gates */
|
||||
#define DCLK_VOP 190
|
||||
#define DCLK_HDMI_PHY 191
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC 194
|
||||
#define ACLK_PERI 210
|
||||
#define ACLK_VOP 211
|
||||
#define ACLK_GMAC 212
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GPIO3 323
|
||||
#define PCLK_GRF 329
|
||||
#define PCLK_I2C0 332
|
||||
#define PCLK_I2C1 333
|
||||
#define PCLK_I2C2 334
|
||||
#define PCLK_I2C3 335
|
||||
#define PCLK_SPI0 338
|
||||
#define PCLK_UART0 341
|
||||
#define PCLK_UART1 342
|
||||
#define PCLK_UART2 343
|
||||
#define PCLK_TSADC 344
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_PERI 363
|
||||
#define PCLK_HDMI_CTRL 364
|
||||
#define PCLK_HDMI_PHY 365
|
||||
#define PCLK_GMAC 367
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_I2S0_8CH 442
|
||||
#define HCLK_I2S1_8CH 443
|
||||
#define HCLK_I2S2_2CH 444
|
||||
#define HCLK_SPDIF_8CH 445
|
||||
#define HCLK_VOP 452
|
||||
#define HCLK_NANDC 453
|
||||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO 457
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
#define SRST_CORE2_PO 2
|
||||
#define SRST_CORE3_PO 3
|
||||
#define SRST_CORE0 4
|
||||
#define SRST_CORE1 5
|
||||
#define SRST_CORE2 6
|
||||
#define SRST_CORE3 7
|
||||
#define SRST_CORE0_DBG 8
|
||||
#define SRST_CORE1_DBG 9
|
||||
#define SRST_CORE2_DBG 10
|
||||
#define SRST_CORE3_DBG 11
|
||||
#define SRST_TOPDBG 12
|
||||
#define SRST_ACLK_CORE 13
|
||||
#define SRST_NOC 14
|
||||
#define SRST_L2C 15
|
||||
|
||||
#define SRST_CPUSYS_H 18
|
||||
#define SRST_BUSSYS_H 19
|
||||
#define SRST_SPDIF 20
|
||||
#define SRST_INTMEM 21
|
||||
#define SRST_ROM 22
|
||||
#define SRST_OTG_ADP 23
|
||||
#define SRST_I2S0 24
|
||||
#define SRST_I2S1 25
|
||||
#define SRST_I2S2 26
|
||||
#define SRST_ACODEC_P 27
|
||||
#define SRST_DFIMON 28
|
||||
#define SRST_MSCH 29
|
||||
#define SRST_EFUSE1024 30
|
||||
#define SRST_EFUSE256 31
|
||||
|
||||
#define SRST_GPIO0 32
|
||||
#define SRST_GPIO1 33
|
||||
#define SRST_GPIO2 34
|
||||
#define SRST_GPIO3 35
|
||||
#define SRST_PERIPH_NOC_A 36
|
||||
#define SRST_PERIPH_NOC_BUS_H 37
|
||||
#define SRST_PERIPH_NOC_P 38
|
||||
#define SRST_UART0 39
|
||||
#define SRST_UART1 40
|
||||
#define SRST_UART2 41
|
||||
#define SRST_PHYNOC 42
|
||||
#define SRST_I2C0 43
|
||||
#define SRST_I2C1 44
|
||||
#define SRST_I2C2 45
|
||||
#define SRST_I2C3 46
|
||||
|
||||
#define SRST_PWM 48
|
||||
#define SRST_A53_GIC 49
|
||||
#define SRST_DAP 51
|
||||
#define SRST_DAP_NOC 52
|
||||
#define SRST_CRYPTO 53
|
||||
#define SRST_SGRF 54
|
||||
#define SRST_GRF 55
|
||||
#define SRST_GMAC 56
|
||||
#define SRST_PERIPH_NOC_H 58
|
||||
#define SRST_MACPHY 63
|
||||
|
||||
#define SRST_DMA 64
|
||||
#define SRST_NANDC 68
|
||||
#define SRST_USBOTG 69
|
||||
#define SRST_OTGC 70
|
||||
#define SRST_USBHOST0 71
|
||||
#define SRST_HOST_CTRL0 72
|
||||
#define SRST_USBHOST1 73
|
||||
#define SRST_HOST_CTRL1 74
|
||||
#define SRST_USBHOST2 75
|
||||
#define SRST_HOST_CTRL2 76
|
||||
#define SRST_USBPOR0 77
|
||||
#define SRST_USBPOR1 78
|
||||
#define SRST_DDRMSCH 79
|
||||
|
||||
#define SRST_SMART_CARD 80
|
||||
#define SRST_SDMMC 81
|
||||
#define SRST_SDIO 82
|
||||
#define SRST_EMMC 83
|
||||
#define SRST_SPI 84
|
||||
#define SRST_TSP_H 85
|
||||
#define SRST_TSP 86
|
||||
#define SRST_TSADC 87
|
||||
#define SRST_DDRPHY 88
|
||||
#define SRST_DDRPHY_P 89
|
||||
#define SRST_DDRCTRL 90
|
||||
#define SRST_DDRCTRL_P 91
|
||||
#define SRST_HOST0_ECHI 92
|
||||
#define SRST_HOST1_ECHI 93
|
||||
#define SRST_HOST2_ECHI 94
|
||||
#define SRST_VOP_NOC_A 95
|
||||
|
||||
#define SRST_HDMI_P 96
|
||||
#define SRST_VIO_ARBI_H 97
|
||||
#define SRST_IEP_NOC_A 98
|
||||
#define SRST_VIO_NOC_H 99
|
||||
#define SRST_VOP_A 100
|
||||
#define SRST_VOP_H 101
|
||||
#define SRST_VOP_D 102
|
||||
#define SRST_UTMI0 103
|
||||
#define SRST_UTMI1 104
|
||||
#define SRST_UTMI2 105
|
||||
#define SRST_UTMI3 106
|
||||
#define SRST_RGA 107
|
||||
#define SRST_RGA_NOC_A 108
|
||||
#define SRST_RGA_A 109
|
||||
#define SRST_RGA_H 110
|
||||
#define SRST_HDCP_A 111
|
||||
|
||||
#define SRST_VPU_A 112
|
||||
#define SRST_VPU_H 113
|
||||
#define SRST_VPU_NOC_A 116
|
||||
#define SRST_VPU_NOC_H 117
|
||||
#define SRST_RKVDEC_A 118
|
||||
#define SRST_RKVDEC_NOC_A 119
|
||||
#define SRST_RKVDEC_H 120
|
||||
#define SRST_RKVDEC_NOC_H 121
|
||||
#define SRST_RKVDEC_CORE 122
|
||||
#define SRST_RKVDEC_CABAC 123
|
||||
#define SRST_IEP_A 124
|
||||
#define SRST_IEP_H 125
|
||||
#define SRST_GPU_A 126
|
||||
#define SRST_GPU_NOC_A 127
|
||||
|
||||
#define SRST_CORE_DBG 128
|
||||
#define SRST_DBG_P 129
|
||||
#define SRST_TIMER0 130
|
||||
#define SRST_TIMER1 131
|
||||
#define SRST_TIMER2 132
|
||||
#define SRST_TIMER3 133
|
||||
#define SRST_TIMER4 134
|
||||
#define SRST_TIMER5 135
|
||||
#define SRST_VIO_H2P 136
|
||||
#define SRST_HDMIPHY 139
|
||||
#define SRST_VDAC 140
|
||||
#define SRST_TIMER_6CH_P 141
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue