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x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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6 changed files with 34 additions and 12 deletions
13
arch/x86/include/asm/arch-queensbay/gpio.h
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13
arch/x86/include/asm/arch-queensbay/gpio.h
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@ -0,0 +1,13 @@
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _X86_ARCH_GPIO_H_
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#define _X86_ARCH_GPIO_H_
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/* Where in config space is the register that points to the GPIO registers? */
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#define PCI_CFG_GPIOBASE 0x44
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#endif /* _X86_ARCH_GPIO_H_ */
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@ -11,7 +11,7 @@
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#include <asm-generic/gpio.h>
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struct ich6_bank_platdata {
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uint32_t base_addr;
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uint16_t base_addr;
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const char *bank_name;
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};
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@ -147,7 +147,7 @@ struct pch_gpio_map {
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} set3;
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};
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void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio);
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void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
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void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
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#endif /* _X86_GPIO_H_ */
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@ -16,7 +16,7 @@ int arch_early_init_r(void)
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return 0;
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}
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void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
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void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
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{
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return;
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}
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@ -125,7 +125,7 @@ int board_early_init_f(void)
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return 0;
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}
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void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
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void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
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{
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/* GPIO Set 1 */
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if (gpio->set1.level)
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@ -19,3 +19,8 @@ int board_early_init_f(void)
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return 0;
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}
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void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
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{
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return;
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}
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@ -39,9 +39,9 @@
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struct ich6_bank_priv {
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/* These are I/O addresses */
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uint32_t use_sel;
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uint32_t io_sel;
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uint32_t lvl;
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uint16_t use_sel;
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uint16_t io_sel;
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uint16_t lvl;
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};
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/* TODO: Move this to device tree, or platform data */
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@ -57,7 +57,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
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u8 tmpbyte;
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u16 tmpword;
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u32 tmplong;
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u32 gpiobase;
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u16 gpiobase;
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int offset;
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/* Where should it be? */
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@ -116,11 +116,15 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
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/*
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* GPIOBASE moved to its current offset with ICH6, but prior to
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* that it was unused (or undocumented). Check that it looks
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* okay: not all ones or zeros, and mapped to I/O space (bit 0).
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* okay: not all ones or zeros.
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*
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* Note we don't need check bit0 here, because the Tunnel Creek
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* GPIO base address register bit0 is reserved (read returns 0),
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* while on the Ivybridge the bit0 is used to indicate it is an
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* I/O space.
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*/
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tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
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if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
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!(tmplong & 0x00000001)) {
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if (tmplong == 0x00000000 || tmplong == 0xffffffff) {
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debug("%s: unexpected GPIOBASE value\n", __func__);
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return -ENODEV;
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}
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@ -131,7 +135,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
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* at the offset that we just read. Bit 0 indicates that it's
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* an I/O address, not a memory address, so mask that off.
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*/
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gpiobase = tmplong & 0xfffffffe;
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gpiobase = tmplong & 0xfffe;
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offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
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if (offset == -1) {
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debug("%s: Invalid register offset %d\n", __func__, offset);
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