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ARM: Add workaround for Cortex-A9 errata 761320
Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
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README
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README
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@ -567,6 +567,7 @@ The following options need to be configured:
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CONFIG_ARM_ERRATA_743622
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CONFIG_ARM_ERRATA_743622
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CONFIG_ARM_ERRATA_751472
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CONFIG_ARM_ERRATA_751472
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CONFIG_ARM_ERRATA_794072
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CONFIG_ARM_ERRATA_794072
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CONFIG_ARM_ERRATA_761320
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If set, the workarounds for these ARM errata are applied early
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If set, the workarounds for these ARM errata are applied early
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during U-Boot startup. Note that these options force the
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during U-Boot startup. Note that these options force the
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@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15)
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orr r0, r0, #1 << 11 @ set bit #11
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orr r0, r0, #1 << 11 @ set bit #11
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#endif
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#ifdef CONFIG_ARM_ERRATA_761320
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 21 @ set bit #21
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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mov pc, lr @ back to my caller
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mov pc, lr @ back to my caller
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ENDPROC(cpu_init_cp15)
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ENDPROC(cpu_init_cp15)
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