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mips: octeon: mrvl, cn73xx.dtsi: Add AHCI/SATA DT node

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Add the AHCI compatible SATA DT node to the Octeon CN73xx dtsi file.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Stefan Roese 2021-04-07 09:12:37 +02:00
parent 9201200c6f
commit b8f0146473
1 changed files with 19 additions and 0 deletions
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19
arch/mips/dts/mrvl,cn73xx.dtsi
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@ -246,5 +246,24 @@
0x02000000 0x00000000 0xe0000000 0x00011b00 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x02000000 0x00000000 0xe0000000 0x00011b00 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
0x43000000 0x00011c00 0x00000000 0x00011c00 0x00000000 0x00000010 0x00000000>;/* prefetchable memory */ 0x43000000 0x00011c00 0x00000000 0x00011c00 0x00000000 0x00000010 0x00000000>;/* prefetchable memory */
}; };
uctl@118006c000000 {
compatible = "cavium,octeon-7130-sata-uctl", "simple-bus";
reg = <0x11800 0x6c000000 0x0 0x100>;
ranges; /* Direct mapping */
#address-cells = <2>;
#size-cells = <2>;
portmap = <0x3>;
staggered-spinup;
cavium,qlm-trim = "4,sata";
sata: sata@16c0000000000 {
compatible = "cavium,octeon-7130-ahci";
reg = <0x16c00 0x00000000 0x0 0x200>;
#address-cells = <2>;
#size-cells = <2>;
interrupts = <0x6c010 4>;
};
};
}; };
}; };