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arm:mx6sx add QSPI support

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Add QSPI support for mx6solox.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This commit is contained in:
Peng Fan 2014-12-31 11:01:38 +08:00 • committed by Jagannadha Sutradharudu Teki
parent ed0c81c654
commit b93ab2ee75
4 changed files with 76 additions and 6 deletions
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50
arch/arm/cpu/armv7/mx6/clock.c
View file

@ -434,6 +434,56 @@ static u32 get_mmdc_ch0_clk(void)
}
#endif
#ifdef CONFIG_MX6SX
/* qspi_num can be from 0 - 1 */
void enable_qspi_clk(int qspi_num)
{
u32 reg = 0;
/* Enable QuadSPI clock */
switch (qspi_num) {
case 0:
/* disable the clock gate */
clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
/* set 50M : (50 = 396 / 2 / 4) */
reg = readl(&imx_ccm->cscmr1);
reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
(2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
writel(reg, &imx_ccm->cscmr1);
/* enable the clock gate */
setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
break;
case 1:
/*
* disable the clock gate
* QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
* disable both of them.
*/
clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
/* set 50M : (50 = 396 / 2 / 4) */
reg = readl(&imx_ccm->cs2cdr);
reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
writel(reg, &imx_ccm->cs2cdr);
/*enable the clock gate*/
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
break;
default:
break;
}
}
#endif
#ifdef CONFIG_FEC_MXC
int enable_fec_anatop_clock(enum enet_freq freq)
{

1
arch/arm/include/asm/arch-mx6/clock.h
View file

@ -67,5 +67,6 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
void enable_qspi_clk(int qspi_num);
void enable_thermal_clk(void);
#endif /* __ASM_ARCH_CLOCK_H */

12
arch/arm/include/asm/arch-mx6/imx-regs.h
View file

@ -92,10 +92,10 @@
#define AIPS3_END_ADDR 0x022FFFFF
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI1_ARB_BASE_ADDR 0x60000000
#define QSPI1_ARB_END_ADDR 0x6FFFFFFF
#define QSPI2_ARB_BASE_ADDR 0x70000000
#define QSPI2_ARB_END_ADDR 0x7FFFFFFF
#define QSPI0_AMBA_BASE 0x60000000
#define QSPI0_AMBA_END 0x6FFFFFFF
#define QSPI1_AMBA_BASE 0x70000000
#define QSPI1_AMBA_END 0x7FFFFFFF
#else
#define SATA_ARB_BASE_ADDR 0x02200000
#define SATA_ARB_END_ADDR 0x02203FFF
@ -262,8 +262,8 @@
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
#ifdef CONFIG_MX6SX
#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#else
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)

19
drivers/spi/fsl_qspi.c
View file

@ -14,7 +14,11 @@
#include "fsl_qspi.h"
#define RX_BUFFER_SIZE 0x80
#ifdef CONFIG_MX6SX
#define TX_BUFFER_SIZE 0x200
#else
#define TX_BUFFER_SIZE 0x40
#endif
#define OFFSET_BITS_MASK 0x00ffffff
@ -53,10 +57,16 @@
static unsigned long spi_bases[] = {
QSPI0_BASE_ADDR,
#ifdef CONFIG_MX6SX
QSPI1_BASE_ADDR,
#endif
};
static unsigned long amba_bases[] = {
QSPI0_AMBA_BASE,
#ifdef CONFIG_MX6SX
QSPI1_AMBA_BASE,
#endif
};
struct fsl_qspi {
@ -159,8 +169,17 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
#ifdef CONFIG_MX6SX
/*
* To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
* So, Use IDATSZ in IPCR to determine the size and here set 0.
*/
qspi_write32(&regs->lut[lut_base + 1], OPRND0(0) |
PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
#else
qspi_write32(&regs->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
#endif
qspi_write32(&regs->lut[lut_base + 2], 0);
qspi_write32(&regs->lut[lut_base + 3], 0);