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microblaze: Support little-endian microblaze target
Microblaze little-endian toolchain should export __MICROBLAZEEL__. Signed-off-by: Michal Simek <monstr@monstr.eu>
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2 changed files with 55 additions and 9 deletions
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@ -32,6 +32,22 @@ _start:
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mts rmsr, r0 /* disable cache */
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mts rmsr, r0 /* disable cache */
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addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
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addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
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addi r1, r1, -4 /* Decrement SP to top of memory */
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addi r1, r1, -4 /* Decrement SP to top of memory */
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/* Find-out if u-boot is running on BIG/LITTLE endian platform
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* There are some steps which is necessary to keep in mind:
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* 1. Setup offset value to r6
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* 2. Store word offset value to address 0x0
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* 3. Load just byte from address 0x0
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* 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
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* value that's why is on address 0x0
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* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
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*/
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addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
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swi r6, r0, 0
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lbui r10, r0, 0
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swi r6, r0, 0x40
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swi r10, r0, 0x50
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/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
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/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
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addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
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addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
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swi r6, r0, 0x0 /* reset address */
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swi r6, r0, 0x0 /* reset address */
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@ -75,26 +91,52 @@ _start:
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/* user_vector_exception */
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/* user_vector_exception */
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addik r6, r0, _exception_handler
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addik r6, r0, _exception_handler
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sw r6, r1, r0
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sw r6, r1, r0
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lhu r7, r1, r0
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/*
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shi r7, r0, 0xa
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* BIG ENDIAN memory map for user exception
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shi r6, r0, 0xe
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* 0x8: 0xB000XXXX
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* 0xC: 0xB808XXXX
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*
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* then it is necessary to count address for storing the most significant
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* 16bits from _exception_handler address and copy it to
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* 0xa address. Big endian use offset in r10=0 that's why is it just
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* 0xa address. The same is done for the least significant 16 bits
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* for 0xe address.
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*
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* LITTLE ENDIAN memory map for user exception
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* 0x8: 0xXXXX00B0
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* 0xC: 0xXXXX08B8
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*
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* Offset is for little endian setup to 0x2. rsubi instruction decrease
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* address value to ensure that points to proper place which is
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* 0x8 for the most significant 16 bits and
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* 0xC for the least significant 16 bits
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*/
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lhu r7, r1, r10
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rsubi r8, r10, 0xa
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sh r7, r0, r8
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rsubi r8, r10, 0xe
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sh r6, r0, r8
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#endif
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#endif
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#ifdef CONFIG_SYS_INTC_0
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#ifdef CONFIG_SYS_INTC_0
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/* interrupt_handler */
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/* interrupt_handler */
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addik r6, r0, _interrupt_handler
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addik r6, r0, _interrupt_handler
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sw r6, r1, r0
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sw r6, r1, r0
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lhu r7, r1, r0
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lhu r7, r1, r10
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shi r7, r0, 0x12
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rsubi r8, r10, 0x12
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shi r6, r0, 0x16
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sh r7, r0, r8
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rsubi r8, r10, 0x16
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sh r6, r0, r8
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#endif
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#endif
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/* hardware exception */
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/* hardware exception */
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addik r6, r0, _hw_exception_handler
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addik r6, r0, _hw_exception_handler
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sw r6, r1, r0
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sw r6, r1, r0
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lhu r7, r1, r0
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lhu r7, r1, r10
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shi r7, r0, 0x22
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rsubi r8, r10, 0x22
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shi r6, r0, 0x26
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sh r7, r0, r8
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rsubi r8, r10, 0x26
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sh r6, r0, r8
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/* enable instruction and data cache */
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/* enable instruction and data cache */
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mfs r12, rmsr
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mfs r12, rmsr
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@ -50,6 +50,10 @@ static __inline__ __u16 ___arch__swab16 (__u16 half_word)
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#endif /* __GNUC__ */
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#endif /* __GNUC__ */
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#ifdef __MICROBLAZEEL__
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#include <linux/byteorder/little_endian.h>
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#else
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#include <linux/byteorder/big_endian.h>
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#include <linux/byteorder/big_endian.h>
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#endif
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#endif /* __MICROBLAZE_BYTEORDER_H__ */
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#endif /* __MICROBLAZE_BYTEORDER_H__ */
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