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malta: IDE support

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This patch adds IDE support to the MIPS Malta board. The IDE controller
is enabled after probing the PCI bus and otherwise just makes use of
U-boot generic IDE support.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Paul Burton 2015-01-29 10:38:20 +00:00 • committed by Daniel Schwierzeck
parent 8755d50706
commit ba21a453a5
3 changed files with 35 additions and 0 deletions
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5
arch/mips/include/asm/malta.h
View file

@ -64,4 +64,9 @@
#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16) #define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16)
#define PCI_CFG_PIIX4_IDETIM_PRI 0x40
#define PCI_CFG_PIIX4_IDETIM_SEC 0x42
#define PCI_CFG_PIIX4_IDETIM_IDE (1 << 15)
#endif /* _MIPS_ASM_MALTA_H */ #endif /* _MIPS_ASM_MALTA_H */

19
board/imgtec/malta/malta.c
View file

@ -6,6 +6,7 @@
*/ */
#include <common.h> #include <common.h>
#include <ide.h>
#include <netdev.h> #include <netdev.h>
#include <pci.h> #include <pci.h>
#include <pci_gt64120.h> #include <pci_gt64120.h>
@ -217,4 +218,22 @@ void pci_init_board(void)
pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8); pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT; val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8); pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB, 0);
if (bdf == -1)
panic("Failed to find PIIX4 IDE controller\n");
/* enable bus master & IO access */
val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
pci_write_config_dword(bdf, PCI_COMMAND, val32);
/* set latency */
pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
/* enable IDE/ATA */
pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
PCI_CFG_PIIX4_IDETIM_IDE);
pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
PCI_CFG_PIIX4_IDETIM_IDE);
} }

11
include/configs/malta.h
View file

@ -106,6 +106,16 @@
#define CONFIG_ENV_ADDR \ #define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE) (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
/*
* IDE/ATA
*/
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 2
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
#define CONFIG_SYS_ATA_DATA_OFFSET 0
#define CONFIG_SYS_ATA_REG_OFFSET 0
/* /*
* Commands * Commands
*/ */
@ -118,6 +128,7 @@
#define CONFIG_CMD_DATE #define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP #define CONFIG_CMD_DHCP
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PCI #define CONFIG_CMD_PCI
#define CONFIG_CMD_PING #define CONFIG_CMD_PING