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quad100hd: Update NAND driver to new API.

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Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Scott Wood 2008-08-13 18:03:40 -05:00
parent f64cb652a8
commit ba22d10f39
1 changed files with 13 additions and 23 deletions
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36
board/quad100hd/nand.c
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@ -25,35 +25,25 @@
#include <config.h> #include <config.h>
#if defined(CONFIG_CMD_NAND) #if defined(CONFIG_CMD_NAND)
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/io.h>
#include <nand.h> #include <nand.h>
/* /*
* hardware specific access to control-lines * hardware specific access to control-lines
*/ */
static void quad100hd_hwcontrol(struct mtd_info *mtd, int cmd) static void quad100hd_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{ {
switch(cmd) { struct nand_chip *this = mtd->priv;
case NAND_CTL_SETCLE:
gpio_write_bit(CFG_NAND_CLE, 1);
break;
case NAND_CTL_CLRCLE:
gpio_write_bit(CFG_NAND_CLE, 0);
break;
case NAND_CTL_SETALE: if (ctrl & NAND_CTRL_CHANGE) {
gpio_write_bit(CFG_NAND_ALE, 1); gpio_write_bit(CFG_NAND_CLE, !!(ctrl & NAND_CLE));
break; gpio_write_bit(CFG_NAND_ALE, !!(ctrl & NAND_ALE));
case NAND_CTL_CLRALE: gpio_write_bit(CFG_NAND_CE, !(ctrl & NAND_NCE));
gpio_write_bit(CFG_NAND_ALE, 0);
break;
case NAND_CTL_SETNCE:
gpio_write_bit(CFG_NAND_CE, 0);
break;
case NAND_CTL_CLRNCE:
gpio_write_bit(CFG_NAND_CE, 1);
break;
} }
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
} }
static int quad100hd_nand_ready(struct mtd_info *mtd) static int quad100hd_nand_ready(struct mtd_info *mtd)
@ -67,9 +57,9 @@ static int quad100hd_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand) int board_nand_init(struct nand_chip *nand)
{ {
/* Set address of hardware control function */ /* Set address of hardware control function */
nand->hwcontrol = quad100hd_hwcontrol; nand->cmd_ctrl = quad100hd_hwcontrol;
nand->dev_ready = quad100hd_nand_ready; nand->dev_ready = quad100hd_nand_ready;
nand->eccmode = NAND_ECC_SOFT; nand->ecc.mode = NAND_ECC_SOFT;
/* 15 us command delay time */ /* 15 us command delay time */
nand->chip_delay = 20; nand->chip_delay = 20;