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rockchip: clk: rk3399: 24MHz is not a power of 2
The clock driver for the RK3399 mistakenly used (24 * 2^20) where it should have used (24 * 10^6) in a few calculations. This commits fixes this. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
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1 changed files with 2 additions and 2 deletions
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@ -667,7 +667,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
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if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
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== CLK_EMMC_PLL_SEL_24M)
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return DIV_TO_RATE(24*1024*1024, div);
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return DIV_TO_RATE(24*1000*1000, div);
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else
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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@ -685,7 +685,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
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if (src_clk_div > 127) {
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/* use 24MHz source for 400KHz clock */
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src_clk_div = 24*1024*1024 / set_rate;
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src_clk_div = 24*1000*1000 / set_rate;
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rk_clrsetreg(&cru->clksel_con[16],
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CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
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CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
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