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rockchip: clk: rk3399: 24MHz is not a power of 2

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The clock driver for the RK3399 mistakenly used (24 * 2^20) where it
should have used (24 * 10^6) in a few calculations.

This commits fixes this.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Philipp Tomsich 2017-03-24 19:35:37 +01:00 • committed by Simon Glass
parent ca0ab2736e
commit ba3bf3879e
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk_rk3399.c
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@ -667,7 +667,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
== CLK_EMMC_PLL_SEL_24M)
return DIV_TO_RATE(24*1024*1024, div);
return DIV_TO_RATE(24*1000*1000, div);
else
return DIV_TO_RATE(GPLL_HZ, div);
}
@ -685,7 +685,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
if (src_clk_div > 127) {
/* use 24MHz source for 400KHz clock */
src_clk_div = 24*1024*1024 / set_rate;
src_clk_div = 24*1000*1000 / set_rate;
rk_clrsetreg(&cru->clksel_con[16],
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |