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driver/mtd/IFC:Wait tWB time, poll R/B before command execution
IFC_FIR_OP_CMD0 issues command for execution without checking flash readiness. It may cause problem if flash is not ready. Instead use IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or time-out, before issuing command. NAND_CMD_READID command implemention does not fulfill above requirement. So update its programming. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Hemant Nautiyal <hemant.nautiyal@freescale.com>
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1 changed files with 2 additions and 2 deletions
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@ -391,7 +391,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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timing = IFC_FIR_OP_RBCD;
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
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(timing << IFC_NAND_FIR0_OP2_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fcr0,
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@ -758,7 +758,7 @@ static void fsl_ifc_sram_init(void)
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/* READID */
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fcr0,
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