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ARMV7: OMAP: Configure Overo's second network chip

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Confiures GPMC timings for both chips and also configures pinmux
for GPIO_65, which is used as the interrupt signal for the second chip

Signed-off-by: Scott Ellis <scott@jumpnowtek.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Steve Sakoman 2010-08-12 21:07:02 -07:00 • committed by Sandeep Paulraj
parent 06b95bd50d
commit ba9a11e4ea
2 changed files with 19 additions and 9 deletions
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26
board/overo/overo.c
View file

@ -43,6 +43,17 @@
static void setup_net_chip(void); static void setup_net_chip(void);
#endif #endif
/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
static const u32 gpmc_lan_config[] = {
NET_LAN9221_GPMC_CONFIG1,
NET_LAN9221_GPMC_CONFIG2,
NET_LAN9221_GPMC_CONFIG3,
NET_LAN9221_GPMC_CONFIG4,
NET_LAN9221_GPMC_CONFIG5,
NET_LAN9221_GPMC_CONFIG6,
/*CONFIG7- computed as params */
};
/* /*
* Routine: board_init * Routine: board_init
* Description: Early hardware init. * Description: Early hardware init.
@ -131,14 +142,13 @@ static void setup_net_chip(void)
{ {
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */ /* first lan chip */
writel(NET_LAN9221_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
writel(NET_LAN9221_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); GPMC_SIZE_16M);
writel(NET_LAN9221_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
writel(NET_LAN9221_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); /* second lan chip */
writel(NET_LAN9221_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 0x2B000000,
writel(NET_LAN9221_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); GPMC_SIZE_16M);
writel(NET_LAN9221_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);

2
board/overo/overo.h
View file

@ -138,7 +138,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
/* - SMSC911X_NRES*/\ /* - SMSC911X_NRES*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
/*DSS*/\ /*DSS*/\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\