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x86: Add the root-complex block to common intel registers

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This is similar to MCH in that it is used in various drivers. Add it to
the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2016-03-11 22:06:56 -07:00 • committed by Bin Meng
parent 06d336cca2
commit bb096b9fad
4 changed files with 9 additions and 7 deletions
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1
arch/x86/cpu/ivybridge/bd82x6x.c
View file

@ -11,6 +11,7 @@
#include <pch.h> #include <pch.h>
#include <syscon.h> #include <syscon.h>
#include <asm/cpu.h> #include <asm/cpu.h>
#include <asm/intel_regs.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/lapic.h> #include <asm/lapic.h>
#include <asm/pci.h> #include <asm/pci.h>

6
arch/x86/cpu/ivybridge/lpc.c
View file

@ -13,6 +13,7 @@
#include <rtc.h> #include <rtc.h>
#include <pci.h> #include <pci.h>
#include <asm/acpi.h> #include <asm/acpi.h>
#include <asm/intel_regs.h>
#include <asm/interrupt.h> #include <asm/interrupt.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/ioapic.h> #include <asm/ioapic.h>
@ -420,7 +421,7 @@ static void enable_spi_prefetch(struct udevice *pch)
static void enable_port80_on_lpc(struct udevice *pch) static void enable_port80_on_lpc(struct udevice *pch)
{ {
/* Enable port 80 POST on LPC */ /* Enable port 80 POST on LPC */
dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1); dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
clrbits_le32(RCB_REG(GCS), 4); clrbits_le32(RCB_REG(GCS), 4);
} }
@ -552,7 +553,8 @@ static int bd82x6x_lpc_early_init(struct udevice *dev)
{ {
/* Setting up Southbridge. In the northbridge code. */ /* Setting up Southbridge. In the northbridge code. */
debug("Setting up static southbridge registers\n"); debug("Setting up static southbridge registers\n");
dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1); dm_pci_write_config32(dev->parent, PCH_RCBA_BASE,
RCB_BASE_ADDRESS | 1);
dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1); dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */ /* Enable ACPI BAR */

5
arch/x86/include/asm/arch-ivybridge/pch.h
View file

@ -211,11 +211,6 @@
#define SMBUS_TIMEOUT (10 * 1000 * 100) #define SMBUS_TIMEOUT (10 * 1000 * 100)
/* Root Complex Register Block */
#define DEFAULT_RCBA 0xfed1c000
#define RCB_REG(reg) (DEFAULT_RCBA + (reg))
#define PCH_RCBA_BASE 0xf0 #define PCH_RCBA_BASE 0xf0
#define VCH 0x0000 /* 32bit */ #define VCH 0x0000 /* 32bit */

4
arch/x86/include/asm/intel_regs.h
View file

@ -12,4 +12,8 @@
#define MCH_BASE_SIZE 0x8000 #define MCH_BASE_SIZE 0x8000
#define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg)) #define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg))
/* Access the Root Complex Register Block */
#define RCB_BASE_ADDRESS 0xfed1c000
#define RCB_REG(reg) (RCB_BASE_ADDRESS + (reg))
#endif #endif