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ppc4xx: Use correct io accessors for esd 405/440 boards

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This patch replaces in/out8/16/32 macros by in/out_8/_be16/_be32
macros. Also volatile pointer references are replaced by the
new accessors.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Matthias Fuchs 2009-02-20 10:19:19 +01:00 • committed by Wolfgang Denk
parent 049216f045
commit bb57ad4be7
15 changed files with 216 additions and 181 deletions
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14
board/esd/common/fpga.c
View file

@ -24,6 +24,7 @@
#include <common.h> #include <common.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/io.h>
#include <command.h> #include <command.h>
/* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */
@ -55,7 +56,7 @@
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ #define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
#ifndef SET_FPGA #ifndef SET_FPGA
# define SET_FPGA(data) out32(GPIO0_OR, data) # define SET_FPGA(data) out_be32((void *)GPIO0_OR, data)
#endif #endif
#ifdef FPGA_PROG_ACTIVE_HIGH #ifdef FPGA_PROG_ACTIVE_HIGH
@ -85,10 +86,10 @@
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
#ifndef FPGA_DONE_STATE #ifndef FPGA_DONE_STATE
# define FPGA_DONE_STATE (in32(GPIO0_IR) & FPGA_DONE) # define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE)
#endif #endif
#ifndef FPGA_INIT_STATE #ifndef FPGA_INIT_STATE
# define FPGA_INIT_STATE (in32(GPIO0_IR) & FPGA_INIT) # define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT)
#endif #endif
@ -139,8 +140,11 @@ static int fpga_boot (const unsigned char *fpgadata, int size)
* Setup port pins for fpga programming * Setup port pins for fpga programming
*/ */
#ifndef CONFIG_M5249 #ifndef CONFIG_M5249
out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */ out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */ /* setup for output */
out_be32 ((void *)GPIO0_TCR,
in_be32 ((void *)GPIO0_TCR) |
FPGA_PRG | FPGA_CLK | FPGA_DATA);
#endif #endif
SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */ SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */

8
board/esd/common/lcd.h
View file

@ -42,10 +42,10 @@
#define S1D_WRITE_PALETTE(p,i,r,g,b) \ #define S1D_WRITE_PALETTE(p,i,r,g,b) \
{ \ { \
((volatile uchar*)(p))[palette_index] = (uchar)(i); \ out_8(&((uchar*)(p))[palette_index], (uchar)(i)); \
((volatile uchar*)(p))[palette_value] = (uchar)(r); \ out_8(&((uchar*)(p))[palette_index], (uchar)(r)); \
((volatile uchar*)(p))[palette_value] = (uchar)(g); \ out_8(&((uchar*)(p))[palette_index], (uchar)(g)); \
((volatile uchar*)(p))[palette_value] = (uchar)(b); \ out_8(&((uchar*)(p))[palette_index], (uchar)(b)); \
} }
typedef struct typedef struct

5
board/esd/common/xilinx_jtag/ports.c
View file

@ -32,6 +32,7 @@
#include <common.h> #include <common.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/io.h>
#include "ports.h" #include "ports.h"
@ -68,7 +69,7 @@ void setPort(short p,short val)
} else { } else {
output &= ~JTAG_TCK; output &= ~JTAG_TCK;
} }
out32(GPIO0_OR, output); out_be32((void *)GPIO0_OR, output);
} }
} }
@ -98,7 +99,7 @@ unsigned char readTDOBit(void)
{ {
unsigned long inputs; unsigned long inputs;
inputs = in32(GPIO0_IR); inputs = in_be32((void *)GPIO0_IR);
if (inputs & JTAG_TDO) if (inputs & JTAG_TDO)
return 1; return 1;
else else

14
board/esd/dp405/dp405.c
View file

@ -23,6 +23,7 @@
#include <common.h> #include <common.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/io.h>
#include <command.h> #include <command.h>
#include <malloc.h> #include <malloc.h>
@ -66,9 +67,11 @@ int board_early_init_f (void)
/* /*
* Reset CPLD via GPIO13 (CS4) pin * Reset CPLD via GPIO13 (CS4) pin
*/ */
out32(GPIO0_OR, in32(GPIO0_OR) & ~(0x80000000 >> 13)); out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13));
udelay(1000); /* wait 1ms */ udelay(1000); /* wait 1ms */
out32(GPIO0_OR, in32(GPIO0_OR) | (0x80000000 >> 13)); out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | (0x80000000 >> 13));
udelay(1000); /* wait 1ms */ udelay(1000); /* wait 1ms */
return 0; return 0;
@ -104,9 +107,10 @@ int checkboard (void)
puts(str); puts(str);
} }
id1 = trans[(~(in32(GPIO0_IR) >> 5)) & 0x0000000f]; id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f];
id2 = trans[(~(in32(GPIO0_IR) >> 9)) & 0x0000000f]; id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f];
printf(" (ID=0x%1X%1X, PLD=0x%02X)\n", id2, id1, in8(0xf0001000)); printf(" (ID=0x%1X%1X, PLD=0x%02X)\n",
id2, id1, in_8((void *)0xf0001000));
return 0; return 0;
} }

4
board/esd/du405/du405.c
View file

@ -188,8 +188,8 @@ int checkboard (void)
/* /*
* Reset external DUART via FPGA * Reset external DUART via FPGA
*/ */
*(volatile unsigned char *) FPGA_MODE_REG = 0xff; /* reset high active */ out_8((void *)FPGA_MODE_REG, 0xff); /* reset high active */
*(volatile unsigned char *) FPGA_MODE_REG = 0x00; /* low again */ out_8((void *)FPGA_MODE_REG, 0x00); /* low again */
return 0; return 0;
} }

13
board/esd/du440/du440.c
View file

@ -310,8 +310,8 @@ int misc_init_r(void)
int pld_revision(void) int pld_revision(void)
{ {
out8(CONFIG_SYS_CPLD_BASE, 0x00); out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
return (int)(in8(CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK); return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
} }
int board_revision(void) int board_revision(void)
@ -872,12 +872,12 @@ static int got_pldirq;
static int pld_interrupt(u32 arg) static int pld_interrupt(u32 arg)
{ {
int rc = -1; /* not for us */ int rc = -1; /* not for us */
u8 status = in8(CONFIG_SYS_CPLD_BASE); u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
/* check for PLD interrupt */ /* check for PLD interrupt */
if (status & PWR_INT_FLAG) { if (status & PWR_INT_FLAG) {
/* reset this int */ /* reset this int */
out8(CONFIG_SYS_CPLD_BASE, 0); out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
rc = 0; rc = 0;
got_pldirq = 1; /* trigger backend */ got_pldirq = 1; /* trigger backend */
} }
@ -890,7 +890,7 @@ int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
got_pldirq = 0; got_pldirq = 0;
/* clear any pending interrupt */ /* clear any pending interrupt */
out8(CONFIG_SYS_CPLD_BASE, 0); out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
irq_install_handler(CPLD_IRQ, irq_install_handler(CPLD_IRQ,
(interrupt_handler_t *)pld_interrupt, 0); (interrupt_handler_t *)pld_interrupt, 0);
@ -906,7 +906,8 @@ int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (got_pldirq) { if (got_pldirq) {
printf("Got interrupt!\n"); printf("Got interrupt!\n");
printf("Power %sready!\n", printf("Power %sready!\n",
in8(CONFIG_SYS_CPLD_BASE) & PWR_RDY ? "":"NOT "); in_8((void *)CONFIG_SYS_CPLD_BASE) &
PWR_RDY ? "":"NOT ");
} }
irq_free_handler(CPLD_IRQ); irq_free_handler(CPLD_IRQ);

166
board/esd/hh405/hh405.c
View file

@ -29,6 +29,7 @@
#include <common.h> #include <common.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/io.h>
#include <command.h> #include <command.h>
#include <malloc.h> #include <malloc.h>
#include <pci.h> #include <pci.h>
@ -36,6 +37,26 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* FPGA internal regs */
#define FPGA_CTRL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000))
#define FPGA_STATUS ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002))
#define FPGA_CTR ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004))
#define FPGA_BL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006))
/* FPGA Control Reg */
#define FPGA_CTRL_REV0 0x0001
#define FPGA_CTRL_REV1 0x0002
#define FPGA_CTRL_VGA0_BL 0x0004
#define FPGA_CTRL_VGA0_BL_MODE 0x0008
#define FPGA_CTRL_CF_RESET 0x0040
#define FPGA_CTRL_PS2_PWR 0x0080
#define FPGA_CTRL_CF_PWRN 0x0100 /* low active */
#define FPGA_CTRL_CF_BUS_EN 0x0200
#define FPGA_CTRL_LCD_CLK 0x7000 /* mask for lcd clock */
#define FPGA_CTRL_OW_ENABLE 0x8000
#define FPGA_STATUS_CF_DETECT 0x8000
#ifdef CONFIG_VIDEO_SM501 #ifdef CONFIG_VIDEO_SM501
#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ #define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
@ -297,22 +318,22 @@ int board_revision(void)
/* /*
* Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO) * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
*/ */
osrh_reg = in32(GPIO0_OSRH); osrh_reg = in_be32((void *)GPIO0_OSRH);
isr1h_reg = in32(GPIO0_ISR1H); isr1h_reg = in_be32((void *)GPIO0_ISR1H);
tcr_reg = in32(GPIO0_TCR); tcr_reg = in_be32((void *)GPIO0_TCR);
out32(GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */ out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */
out32(GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */ out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */
out32(GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */ out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */
udelay(1000); /* wait some time before reading input */ udelay(1000); /* wait some time before reading input */
value = in32(GPIO0_IR) & 0x80400000; /* get config bits */ value = in_be32((void *)GPIO0_IR) & 0x80400000; /* get config bits */
/* /*
* Restore GPIO settings * Restore GPIO settings
*/ */
out32(GPIO0_OSRH, osrh_reg); /* output select */ out_be32((void *)GPIO0_OSRH, osrh_reg); /* output select */
out32(GPIO0_ISR1H, isr1h_reg); /* input select */ out_be32((void *)GPIO0_ISR1H, isr1h_reg); /* input select */
out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
if (value & 0x80000000) { if (value & 0x80000000) {
/* Revision 1.0 or 1.1 detected */ /* Revision 1.0 or 1.1 detected */
@ -353,7 +374,7 @@ int board_early_init_f (void)
/* /*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/ */
mtebc (epcr, 0xa8400000); /* ebc always driven */ mtebc(epcr, 0xa8400000); /* ebc always driven */
return 0; return 0;
} }
@ -362,27 +383,26 @@ int cf_enable(void)
{ {
int i; int i;
volatile unsigned short *fpga_ctrl =
(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
volatile unsigned short *fpga_status =
(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2);
if (gd->board_type >= 2) { if (gd->board_type >= 2) {
if (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT) { if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) {
if (!(*fpga_ctrl & CONFIG_SYS_FPGA_CTRL_CF_BUS_EN)) { if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) {
*fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_PWRN; out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN);
for (i=0; i<300; i++) for (i=0; i<300; i++)
udelay(1000); udelay(1000);
*fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_BUS_EN; out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN);
for (i=0; i<20; i++) for (i=0; i<20; i++)
udelay(1000); udelay(1000);
} }
} else { } else {
*fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_BUS_EN; out_be16(FPGA_CTRL,
*fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_PWRN; in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN);
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN);
} }
} }
@ -391,12 +411,6 @@ int cf_enable(void)
int misc_init_r (void) int misc_init_r (void)
{ {
volatile unsigned short *fpga_ctrl =
(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
volatile unsigned short *lcd_contrast =
(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
volatile unsigned short *lcd_backlight =
(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
unsigned char *dst; unsigned char *dst;
ulong len = sizeof(fpgadata); ulong len = sizeof(fpgadata);
int status; int status;
@ -460,36 +474,43 @@ int misc_init_r (void)
/* /*
* Reset FPGA via FPGA_INIT pin * Reset FPGA via FPGA_INIT pin
*/ */
out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ /* setup FPGA_INIT as output */
out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */ out_be32((void *)GPIO0_TCR,
in_be32((void *)GPIO0_TCR) | FPGA_INIT);
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~FPGA_INIT); /* reset low */
udelay(1000); /* wait 1ms */ udelay(1000); /* wait 1ms */
out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */ out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | FPGA_INIT); /* reset high */
udelay(1000); /* wait 1ms */ udelay(1000); /* wait 1ms */
/* /*
* Write Board revision into FPGA * Write Board revision into FPGA
*/ */
*fpga_ctrl |= gd->board_type & 0x0003; out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
/* /*
* Setup and enable EEPROM write protection * Setup and enable EEPROM write protection
*/ */
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP); out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
/* /*
* Reset touch-screen controller * Reset touch-screen controller
*/ */
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST); out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
udelay(1000); udelay(1000);
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_TOUCH_RST); out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
/* /*
* Enable power on PS/2 interface (with reset) * Enable power on PS/2 interface (with reset)
*/ */
*fpga_ctrl &= ~(CONFIG_SYS_FPGA_CTRL_PS2_PWR); out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
for (i=0;i<500;i++) for (i=0;i<500;i++)
udelay(1000); udelay(1000);
*fpga_ctrl |= (CONFIG_SYS_FPGA_CTRL_PS2_PWR); out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
/* /*
* Get contrast value from environment variable * Get contrast value from environment variable
@ -498,7 +519,8 @@ int misc_init_r (void)
if (str) { if (str) {
contrast0 = simple_strtol(str, NULL, 16); contrast0 = simple_strtol(str, NULL, 16);
if (contrast0 > 255) { if (contrast0 > 255) {
printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0); printf("ERROR: contrast0 value too high (0x%lx)!\n",
contrast0);
contrast0 = 0xffffffff; contrast0 = 0xffffffff;
} }
} }
@ -512,8 +534,9 @@ int misc_init_r (void)
/* /*
* Switch backlight on * Switch backlight on
*/ */
*fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL; out_be16(FPGA_CTRL,
*lcd_backlight = 0x0000; in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
out_be16(FPGA_BL, 0x0000);
lcd_setup(1, 0); lcd_setup(1, 0);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
@ -524,8 +547,9 @@ int misc_init_r (void)
/* /*
* Switch backlight on * Switch backlight on
*/ */
*fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_VGA0_BL; out_be16(FPGA_CTRL,
*lcd_backlight = 0x0000; in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
out_be16(FPGA_BL, 0x0000);
lcd_setup(1, 0); lcd_setup(1, 0);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
@ -537,19 +561,22 @@ int misc_init_r (void)
* Set default display contrast voltage * Set default display contrast voltage
*/ */
if (contrast0 == 0xffffffff) { if (contrast0 == 0xffffffff) {
*lcd_contrast = 0x0082; out_be16(FPGA_CTR, 0x0082);
} else { } else {
*lcd_contrast = contrast0; out_be16(FPGA_CTR, contrast0);
} }
*lcd_backlight = 0xffff; out_be16(FPGA_BL, 0xffff);
/* /*
* Switch backlight on * Switch backlight on
*/ */
*fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE; out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) |
FPGA_CTRL_VGA0_BL |
FPGA_CTRL_VGA0_BL_MODE);
/* /*
* Set lcd clock (small epson) * Set lcd clock (small epson)
*/ */
*fpga_ctrl |= LCD_CLK_06250; out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
udelay(100); /* wait for 100 us */ udelay(100); /* wait for 100 us */
lcd_setup(0, 1); lcd_setup(0, 1);
@ -562,19 +589,25 @@ int misc_init_r (void)
* Set default display contrast voltage * Set default display contrast voltage
*/ */
if (contrast0 == 0xffffffff) { if (contrast0 == 0xffffffff) {
*lcd_contrast = 0x0060; out_be16(FPGA_CTR, 0x0060);
} else { } else {
*lcd_contrast = contrast0; out_be16(FPGA_CTR, contrast0);
} }
*lcd_backlight = 0xffff; out_be16(FPGA_BL, 0xffff);
/* /*
* Switch backlight on * Switch backlight on
*/ */
*fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE; out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) |
FPGA_CTRL_VGA0_BL |
FPGA_CTRL_VGA0_BL_MODE);
/* /*
* Set lcd clock (small epson), enable 1-wire interface * Set lcd clock (small epson), enable 1-wire interface
*/ */
*fpga_ctrl |= LCD_CLK_08330 | CONFIG_SYS_FPGA_CTRL_OW_ENABLE; out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) |
LCD_CLK_08330 |
FPGA_CTRL_OW_ENABLE);
lcd_setup(0, 1); lcd_setup(0, 1);
lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
@ -593,10 +626,10 @@ int misc_init_r (void)
puts("VGA: SM501 with 8 MB "); puts("VGA: SM501 with 8 MB ");
if (strcmp(str, "ppc221") == 0) { if (strcmp(str, "ppc221") == 0) {
printf("(800*600, %dbpp)\n", BPP); printf("(800*600, %dbpp)\n", BPP);
*lcd_backlight = 0x002d; /* max. allowed brightness */ out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
} else if (strcmp(str, "ppc231") == 0) { } else if (strcmp(str, "ppc231") == 0) {
printf("(1024*768, %dbpp)\n", BPP); printf("(1024*768, %dbpp)\n", BPP);
*lcd_backlight = 0x0000; out_be16(FPGA_BL, 0x0000);
} else { } else {
printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
return 0; return 0;
@ -646,21 +679,21 @@ int checkboard (void)
#ifdef CONFIG_IDE_RESET #ifdef CONFIG_IDE_RESET
void ide_set_reset(int on) void ide_set_reset(int on)
{ {
volatile unsigned short *fpga_mode = if (((gd->board_type >= 2) &&
(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) ||
volatile unsigned short *fpga_status =
(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2);
if (((gd->board_type >= 2) && (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT)) ||
(gd->board_type < 2)) { (gd->board_type < 2)) {
/* /*
* Assert or deassert CompactFlash Reset Pin * Assert or deassert CompactFlash Reset Pin
*/ */
if (on) { /* assert RESET */ if (on) { /* assert RESET */
cf_enable(); cf_enable();
*fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET); out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) &
~FPGA_CTRL_CF_RESET);
} else { /* release RESET */ } else { /* release RESET */
*fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET; out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) |
FPGA_CTRL_CF_RESET);
} }
} }
} }
@ -684,17 +717,20 @@ int eeprom_write_enable (unsigned dev_addr, int state)
switch (state) { switch (state) {
case 1: case 1:
/* Enable write access, clear bit GPIO_SINT2. */ /* Enable write access, clear bit GPIO_SINT2. */
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
state = 0; state = 0;
break; break;
case 0: case 0:
/* Disable write access, set bit GPIO_SINT2. */ /* Disable write access, set bit GPIO_SINT2. */
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP); out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
state = 0; state = 0;
break; break;
default: default:
/* Read current status back. */ /* Read current status back. */
state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); state = (0 == (in_be32((void *)GPIO0_OR) &
CONFIG_SYS_EEPROM_WP));
break; break;
} }
} }

56
board/esd/hub405/hub405.c
View file

@ -23,6 +23,7 @@
#include <common.h> #include <common.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/io.h>
#include <command.h> #include <command.h>
#include <malloc.h> #include <malloc.h>
@ -44,22 +45,22 @@ int board_revision(void)
/* /*
* Setup GPIO pin(s) (IRQ6/GPIO23) * Setup GPIO pin(s) (IRQ6/GPIO23)
*/ */
osrl_reg = in32(GPIO0_OSRH); osrl_reg = in_be32((void *)GPIO0_OSRH);
isr1l_reg = in32(GPIO0_ISR1H); isr1l_reg = in_be32((void *)GPIO0_ISR1H);
tcr_reg = in32(GPIO0_TCR); tcr_reg = in_be32((void *)GPIO0_TCR);
out32(GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */ out_be32((void *)GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */
out32(GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */ out_be32((void *)GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */
out32(GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */ out_be32((void *)GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */
udelay(1000); /* wait some time before reading input */ udelay(1000); /* wait some time before reading input */
value = in32(GPIO0_IR) & 0x00000100; /* get config bits */ value = in_be32((void *)GPIO0_IR) & 0x00000100; /* get config bits */
/* /*
* Restore GPIO settings * Restore GPIO settings
*/ */
out32(GPIO0_OSRH, osrl_reg); /* output select */ out_be32((void *)GPIO0_OSRH, osrl_reg); /* output select */
out32(GPIO0_ISR1H, isr1l_reg); /* input select */ out_be32((void *)GPIO0_ISR1H, isr1l_reg); /* input select */
out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
if (value & 0x00000100) { if (value & 0x00000100) {
/* Revision 1.1 or 1.2 detected */ /* Revision 1.1 or 1.2 detected */
@ -101,13 +102,9 @@ int board_early_init_f (void)
return 0; return 0;
} }
#define LED_REG (DUART0_BA + 0x20)
int misc_init_r (void) int misc_init_r (void)
{ {
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
volatile unsigned char *led_reg = (unsigned char *)((ulong)DUART0_BA + 0x20);
unsigned long val; unsigned long val;
int delay, flashcnt; int delay, flashcnt;
char *str; char *str;
@ -116,16 +113,17 @@ int misc_init_r (void)
/* /*
* Enable interrupts in exar duart mcr[3] * Enable interrupts in exar duart mcr[3]
*/ */
*duart0_mcr = 0x08; out_8((void *)(DUART0_BA + 4), 0x08);
*duart1_mcr = 0x08; out_8((void *)(DUART1_BA + 4), 0x08);
*duart2_mcr = 0x08; out_8((void *)(DUART2_BA + 4), 0x08);
*duart3_mcr = 0x08; out_8((void *)(DUART3_BA + 4), 0x08);
/* /*
* Set RS232/RS422 control (RS232 = high on GPIO) * Set RS232/RS422 control (RS232 = high on GPIO)
*/ */
val = in32(GPIO0_OR); val = in_be32((void *)GPIO0_OR);
val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 | CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232); val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 |
CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232);
str = getenv("phys0"); str = getenv("phys0");
if (!str || (str && (str[0] == '0'))) if (!str || (str && (str[0] == '0')))
@ -143,7 +141,7 @@ int misc_init_r (void)
if (!str || (str && (str[0] == '0'))) if (!str || (str && (str[0] == '0')))
val |= CONFIG_SYS_UART5_RS232; val |= CONFIG_SYS_UART5_RS232;
out32(GPIO0_OR, val); out_be32((void *)GPIO0_OR, val);
/* /*
* check board type and setup AP power * check board type and setup AP power
@ -160,23 +158,27 @@ int misc_init_r (void)
* Flash LEDs * Flash LEDs
*/ */
for (flashcnt = 0; flashcnt < 3; flashcnt++) { for (flashcnt = 0; flashcnt < 3; flashcnt++) {
*led_reg = led_reg_default; /* LED_A..D off */ /* LED_A..D off */
out_8((void *)LED_REG, led_reg_default);
for (delay = 0; delay < 100; delay++) for (delay = 0; delay < 100; delay++)
udelay(1000); udelay(1000);
*led_reg = led_reg_default | 0xf0; /* LED_A..D on */ /* LED_A..D on */
out_8((void *)LED_REG, led_reg_default | 0xf0);
for (delay = 0; delay < 50; delay++) for (delay = 0; delay < 50; delay++)
udelay(1000); udelay(1000);
} }
*led_reg = led_reg_default; out_8((void *)LED_REG, led_reg_default);
} }
} }
/* /*
* Reset external DUARTs * Reset external DUARTs
*/ */
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */ out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
udelay(10); /* wait 10us */ udelay(10); /* wait 10us */
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */ out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */ udelay(1000); /* wait 1ms */
/* /*

8
board/esd/pci405/pci405.c
View file

@ -338,17 +338,17 @@ int checkboard (void)
} }
/* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */
#define UART1_MCR 0xef600404
int wpeeprom(int wp) int wpeeprom(int wp)
{ {
int wp_state = wp; int wp_state = wp;
volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404;
if (wp == 1) { if (wp == 1) {
*uart1_mcr &= ~0x02; out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
} else if (wp == 0) { } else if (wp == 0) {
*uart1_mcr |= 0x02; out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
} else { } else {
if (*uart1_mcr & 0x02) { if (in_8((void *)UART1_MCR) & 0x02) {
wp_state = 0; wp_state = 0;
} else { } else {
wp_state = 1; wp_state = 1;

10
board/esd/plu405/plu405.c
View file

@ -237,18 +237,18 @@ int checkboard (void)
} }
#ifdef CONFIG_IDE_RESET #ifdef CONFIG_IDE_RESET
#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
void ide_set_reset(int on) void ide_set_reset(int on)
{ {
volatile unsigned short *fpga_mode =
(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
/* /*
* Assert or deassert CompactFlash Reset Pin * Assert or deassert CompactFlash Reset Pin
*/ */
if (on) { /* assert RESET */ if (on) { /* assert RESET */
*fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET); out_be16((void *)FPGA_CTRL,
in_be16((void *)FPGA_CTRL) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else { /* release RESET */ } else { /* release RESET */
*fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET; out_be16((void *)FPGA_CTRL,
in_be16((void *)FPGA_CTRL) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
} }
} }
#endif /* CONFIG_IDE_RESET */ #endif /* CONFIG_IDE_RESET */

2
board/esd/pmc440/cmd_pmc440.c
View file

@ -242,7 +242,7 @@ int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
"address %08x\n", "address %08x\n",
n, data, f); n, data, f);
for (i=0; i<n; i++) for (i=0; i<n; i++)
out32(f, data); out_be32((void *)f, data);
} }
} else { } else {
printf("Usage:\nfifo %s\n", cmdtp->help); printf("Usage:\nfifo %s\n", cmdtp->help);

57
board/esd/pmc440/pmc440.c
View file

@ -107,31 +107,31 @@ int board_early_init_f(void)
* Setup the GPIO pins * Setup the GPIO pins
* TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
*/ */
out32(GPIO0_OR, 0x40000102); out_be32((void *)GPIO0_OR, 0x40000102);
out32(GPIO0_TCR, 0x4c90011f); out_be32((void *)GPIO0_TCR, 0x4c90011f);
out32(GPIO0_OSRL, 0x28051400); out_be32((void *)GPIO0_OSRL, 0x28051400);
out32(GPIO0_OSRH, 0x55005000); out_be32((void *)GPIO0_OSRH, 0x55005000);
out32(GPIO0_TSRL, 0x08051400); out_be32((void *)GPIO0_TSRL, 0x08051400);
out32(GPIO0_TSRH, 0x55005000); out_be32((void *)GPIO0_TSRH, 0x55005000);
out32(GPIO0_ISR1L, 0x54000000); out_be32((void *)GPIO0_ISR1L, 0x54000000);
out32(GPIO0_ISR1H, 0x00000000); out_be32((void *)GPIO0_ISR1H, 0x00000000);
out32(GPIO0_ISR2L, 0x44000000); out_be32((void *)GPIO0_ISR2L, 0x44000000);
out32(GPIO0_ISR2H, 0x00000100); out_be32((void *)GPIO0_ISR2H, 0x00000100);
out32(GPIO0_ISR3L, 0x00000000); out_be32((void *)GPIO0_ISR3L, 0x00000000);
out32(GPIO0_ISR3H, 0x00000000); out_be32((void *)GPIO0_ISR3H, 0x00000000);
out32(GPIO1_OR, 0x80002408); out_be32((void *)GPIO1_OR, 0x80002408);
out32(GPIO1_TCR, 0xd6003c08); out_be32((void *)GPIO1_TCR, 0xd6003c08);
out32(GPIO1_OSRL, 0x0a5a0000); out_be32((void *)GPIO1_OSRL, 0x0a5a0000);
out32(GPIO1_OSRH, 0x00000000); out_be32((void *)GPIO1_OSRH, 0x00000000);
out32(GPIO1_TSRL, 0x00000000); out_be32((void *)GPIO1_TSRL, 0x00000000);
out32(GPIO1_TSRH, 0x00000000); out_be32((void *)GPIO1_TSRH, 0x00000000);
out32(GPIO1_ISR1L, 0x00005555); out_be32((void *)GPIO1_ISR1L, 0x00005555);
out32(GPIO1_ISR1H, 0x40000000); out_be32((void *)GPIO1_ISR1H, 0x40000000);
out32(GPIO1_ISR2L, 0x04010000); out_be32((void *)GPIO1_ISR2L, 0x04010000);
out32(GPIO1_ISR2H, 0x00000000); out_be32((void *)GPIO1_ISR2H, 0x00000000);
out32(GPIO1_ISR3L, 0x01400000); out_be32((void *)GPIO1_ISR3L, 0x01400000);
out32(GPIO1_ISR3H, 0x00000000); out_be32((void *)GPIO1_ISR3H, 0x00000000);
/* patch PLB:PCI divider for 66MHz PCI */ /* patch PLB:PCI divider for 66MHz PCI */
mfcpr(clk_spcid, reg); mfcpr(clk_spcid, reg);
@ -804,17 +804,20 @@ int eeprom_write_enable(unsigned dev_addr, int state)
switch (state) { switch (state) {
case 1: case 1:
/* Enable write access, clear bit GPIO_SINT2. */ /* Enable write access, clear bit GPIO_SINT2. */
out32(GPIO0_OR, in32(GPIO0_OR) & ~GPIO0_EP_EEP); out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
state = 0; state = 0;
break; break;
case 0: case 0:
/* Disable write access, set bit GPIO_SINT2. */ /* Disable write access, set bit GPIO_SINT2. */
out32(GPIO0_OR, in32(GPIO0_OR) | GPIO0_EP_EEP); out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
state = 0; state = 0;
break; break;
default: default:
/* Read current status back. */ /* Read current status back. */
state = (0 == (in32(GPIO0_OR) & GPIO0_EP_EEP)); state = (0 == (in_be32((void *)GPIO0_OR)
& GPIO0_EP_EEP));
break; break;
} }
} }

7
board/esd/tasreg/tasreg.c
View file

@ -25,6 +25,7 @@
#include <command.h> #include <command.h>
#include <malloc.h> #include <malloc.h>
#include <asm/m5249.h> #include <asm/m5249.h>
#include <asm/io.h>
/* Prototypes */ /* Prototypes */
@ -118,7 +119,7 @@ phys_size_t initdram (int board_type) {
/** Precharge sequence **/ /** Precharge sequence **/
mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
*((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */ out_be32((void *)0, junk); /* write to a memory location to init. precharge */
udelay(0x10); /* Allow several Precharge cycles */ udelay(0x10); /* Allow several Precharge cycles */
/** Refresh Sequence **/ /** Refresh Sequence **/
@ -127,7 +128,7 @@ phys_size_t initdram (int board_type) {
/** Mode Register initialization **/ /** Mode Register initialization **/
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ out_be32((void *)0x800, junk); /* Access RAM to initialize the mode register */
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}; };
@ -258,7 +259,7 @@ int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{ {
uchar buf[8]; uchar buf[8];
*(volatile ushort *)0xe0000000 = 0x4000; out_be16((void *)0xe0000000, 0x4000);
udelay(5000); /* wait for 5ms */ udelay(5000); /* wait for 5ms */

10
board/esd/voh405/voh405.c
View file

@ -297,18 +297,18 @@ int checkboard (void)
} }
#ifdef CONFIG_IDE_RESET #ifdef CONFIG_IDE_RESET
#define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
void ide_set_reset(int on) void ide_set_reset(int on)
{ {
volatile unsigned short *fpga_mode =
(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
/* /*
* Assert or deassert CompactFlash Reset Pin * Assert or deassert CompactFlash Reset Pin
*/ */
if (on) { /* assert RESET */ if (on) { /* assert RESET */
*fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET); out_be16((void *)FPGA_MODE,
in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else { /* release RESET */ } else { /* release RESET */
*fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET; out_be16((void *)FPGA_MODE,
in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
} }
} }
#endif /* CONFIG_IDE_RESET */ #endif /* CONFIG_IDE_RESET */

17
include/configs/HH405.h
View file

@ -413,23 +413,6 @@
#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
/* FPGA internal regs */
#define CONFIG_SYS_FPGA_CTRL 0x000
/* FPGA Control Reg */
#define CONFIG_SYS_FPGA_CTRL_REV0 0x0001
#define CONFIG_SYS_FPGA_CTRL_REV1 0x0002
#define CONFIG_SYS_FPGA_CTRL_VGA0_BL 0x0004
#define CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE 0x0008
#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0040
#define CONFIG_SYS_FPGA_CTRL_PS2_PWR 0x0080
#define CONFIG_SYS_FPGA_CTRL_CF_PWRN 0x0100 /* low active */
#define CONFIG_SYS_FPGA_CTRL_CF_BUS_EN 0x0200
#define CONFIG_SYS_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */
#define CONFIG_SYS_FPGA_CTRL_OW_ENABLE 0x8000
#define CONFIG_SYS_FPGA_STATUS_CF_DETECT 0x8000
#define LCD_CLK_OFF 0x0000 /* Off */ #define LCD_CLK_OFF 0x0000 /* Off */
#define LCD_CLK_02083 0x1000 /* 2.083 MHz */ #define LCD_CLK_02083 0x1000 /* 2.083 MHz */
#define LCD_CLK_03135 0x2000 /* 3.135 MHz */ #define LCD_CLK_03135 0x2000 /* 3.135 MHz */