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ARM: tegra: import latest Jetson TK1 spreadsheet

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This imports v11 of "Jetson TK1 Development Platform Pin Mux" from
https://developer.nvidia.com/embedded/downloads.

The new version defines the mux option for the MIPI pad ctrl selection.
The OWR pin no longer has an entry in the configuration table because
the only mux option it support is OWR, that feature isn't supported, and
hence can't conflict with any other pin. This pin can only usefully be
used as a GPIO.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2016-04-21 16:03:37 -06:00 • committed by Tom Warren
parent f5c6db84e7
commit bbca7108db
2 changed files with 14 additions and 1 deletions
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3
board/nvidia/jetson-tk1/jetson-tk1.c
View file

@ -31,6 +31,9 @@ void pinmux_init(void)
pinmux_config_drvgrp_table(jetson_tk1_drvgrps, pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
ARRAY_SIZE(jetson_tk1_drvgrps)); ARRAY_SIZE(jetson_tk1_drvgrps));
pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
} }
#ifdef CONFIG_PCI_TEGRA #ifdef CONFIG_PCI_TEGRA

12
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
View file

@ -276,7 +276,6 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
}; };
@ -296,4 +295,15 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = { static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
}; };
#define MIPIPADCTRLCFG(_grp, _mux) \
{ \
.grp = PMUX_MIPIPADCTRLGRP_##_grp, \
.func = PMUX_FUNC_##_mux, \
}
static const struct pmux_mipipadctrlgrp_config jetson_tk1_mipipadctrlgrps[] = {
/* grp, mux */
MIPIPADCTRLCFG(DSI_B, DSI_B),
};
#endif /* PINMUX_CONFIG_JETSON_TK1_H */ #endif /* PINMUX_CONFIG_JETSON_TK1_H */